XP8255 PLCC44
XD8255-2 DIP-40
The 8255 is a high performance CMOS version of the
industry standard 8255 and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may
be used with many different microprocessors. There are 24
I/O pins which may be individually programmed in 2 groups
of 12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
8255 make it compatible with the 8086, 8088 and
other microprocessors.
Features
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
• Direct Bit Set/Reset Capability
• Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
• Pin Compatible with NMOS 8255
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 8086 and 8088
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . . .10µA
Ordering Information
PART NUMBERS
PART
MARKING
5MHz
XD8255-2
XD8255-2
8MHz
XD8255-2
PART
MARKING
XD8255-2
XP8255
TEMP.
RANGE (°C)
0 to +70
PACKAGE
PKG. DWG. #
40 Ld PDIP (Pb-free)
0 to +70
44 Ld PLCC (Pb-free)
-40 to +85
44 Ld PLCC (Pb-free)
E40.6
N44.65
Pinouts
8255 (PDIP, CERDIP)
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
9
10
11
12
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 VCC
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
13
14
15
16
17
18
19
20
8255 (PLCC)
TOP VIEW
PA4
PA5
PA6
PA7
WR
RESET
D0
D1
6 5 4 3 2 1 44 43 42 41 40
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 1920 21 22 23 24 25 26 27 28
1
PB2
NC
PB3
PB4
PB5
PB6
PB7
40
39
38
37
36
35
34
33
RD
PA0
PA1
PA2
PA3
NC
PA4
PA5
PA6
PA7
WR
1
2
3
4
5
6
7
8
PC2
PC3
PB0
PB1
PA3
PA2
PA1
PA0
RD
CS
GND
A1
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
VCC
XP8255 PLCC44
XD8255-2 DIP-40
Pin Description
SYMBOL
TYPE
DESCRIPTION
VCC
VCC: The +5V power supply pin. A 0.1F capacitor between VCC and GND is recommended for decoupling.
GND
GROUND
D0-D7
I/O
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET
I
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus
Hold” circuitry turned on.
CS
I
CHIP SELECT: Chip select is an active low input used to enable the 8255 onto the Data Bus for CPU
communications.
RD
I
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WR
I
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 8255.
A0-A1
I
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PA0-PA7
I/O
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port.
PB0-PB7
I/O
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PC0-PC7
I/O
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
Functional Diagram
POWER
SUPPLIES
+5V
GND
GROUP A
PORT A
(8)
GROUP A
CONTROL
GROUP A
PORT C
UPPER
(4)
BIDIRECTIONAL
DATA BUS
D7-D0
DATA BUS
BUFFER
8-BIT
INTERNAL
DATA BUS
RD
WR
A1
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
A0
RESET
CS
2
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
XP8255 PLCC44
XD8255-2 DIP-40
Functional Description
Data Bus Buffer
POWER
SUPPLIES
This three-state bidirectional 8-bit buffer is used to interface the
8255 to the system data bus.
Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information
are also transferred through the data bus buffer.
BIDIRECTIONAL
DATA BUS
DATA
BUS
D7-D0
BUFFER
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words. It
accepts inputs from the CPU Address and Control busses and
in turn, issues commands to both of the Control Groups.
RD
WR
A1
A0
RESET
(CS) Chip Select. A “low” on this input pin enables the
communication between the 8255 and the CPU.
0
0
0
1
0
Port A Data Bus
0
1
0
1
0
Port B Data Bus
1
0
0
1
0
Port C Data Bus
1
1
0
1
0
Control Word Data Bus
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PC3PC0
I/O
PB7PB0
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
INPUT OPERATION
(READ)
CS
8-BIT
INTERNAL
DATA BUS
GROUP B
PORT C
LOWER
(4)
I/O
PC7PC4
Group A and Group B Controls
8255 BASIC OPERATION
WR
GROUP A
PORT C
UPPER
(4)
The functional configuration of each port is programmed by the
systems software. In essence, the CPU “outputs” a control
word to the 8255. The control word contains information
such as “mode”, “bit set”, “bit reset”, etc., that initializes the
functional configuration of the 8255.
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control the
selection of one of the three ports or the control word register.
They are normally connected to the least significant bits of the
address bus (A0 and A1).
RD
GROUP A
PORT A
(8)
FIGURE 1. 8255 BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
(WR) Write. A “low” on this input pin enables the CPU to write
data or control words into the 8255.
A0
READ
WRITE
CONTROL
LOGIC
GROUP A
CONTROL
CS
(RD) Read. A “low” on this input pin enables 8255 to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 8255.
A1
+5V
GND
I/O
PA7PA0
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations. When
the control word is read, bit D7 will always be a logic “1”, as this
implies control word mode information.
OUTPUT OPERATION
(WRITE)
0
0
1
0
0
Data Bus Port A
0
1
1
0
0
Data Bus Port B
Ports A, B, and C
1
0
1
0
0
Data Bus Port C
1
1
1
0
0
Data Bus Control
The 8255 contains three 8-bit ports (A, B, and C). All can be
configured to a wide variety of functional characteristics by the
system software but each has its own special features or
“personality” to further enhance the power and flexibility of the
8255.
DISABLE FUNCTION
X
X
X
X
1
Data Bus Three-State
X
X
1
1
0
Data Bus Three-State
Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices are
present on Port A. See Figure 2A.
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input mode.
“Bus hold” devices internal to the 8255 will hold the I/O port
inputs to a logic “1” state with a maximum hold current of
400A.
Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
3
XP8255 PLCC44
XD8255-2 DIP-40
two 4-bit ports under the mode control. Each 4-bit port contains
a 4-bit latch and it can be used for the control signal output and
status signal inputs in conjunction with ports A and B. See
Figure 2B.
ADDRESS BUS
CONTROL BUS
DATA BUS
INPUT MODE
MASTER
RESET
OR MODE
CHANGE
RD, WR
INTERNAL
DATA IN
EXTERNAL
PORT A PIN
MODE 0
INTERNAL
DATA OUT
(LATCHED)
OUTPUT MODE
I/O
PB7-PB0
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
MODE 1
VCC
EXTERNAL
PORT B, C
PIN
INTERNAL
DATA OUT
(LATCHED)
4
I/O
PC7-PC4
I/O
8
CONTROL CONTROL
OR I/O
OR I/O
C
I/O
PA7-PA0
A
8
I/O
PA7-PA0
A
BIDIRECTIONAL
I/O
PB7-PB0
OUTPUT MODE
I/O
PC3-PC0
B
8
A
C
PB7-PB0
MODE 2
4
B
8
P
INTERNAL
DATA IN
A0-A1
CS
C
B
8
RESET
OR MODE
CHANGE
D7-D0
8255
CONTROL
PA7-PA0
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
CONTROL WORD
Operational Description
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
Mode Selection
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
There are three basic modes of operation than can be selected
by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1
When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
8255 can remain in the input mode with no additional
initialization required. This eliminates the need to pull-up or
pull-down resistors in all-CMOS designs. The control word
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 8255 to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output port
is initialized to all zeros when the control word is written.
GROUP A
PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
4
XP8255 PLCC44
XD8255-2 DIP-40
INTE Flip-Flop Definition
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the Port
A and Port B definitions. All of the output registers, including
the status flip-flops, will be reset whenever the mode is
changed. Modes may be combined so that their functional
definition can be “tailored” to almost any I/O structure. For
instance: Group B can be programmed in Mode 0 to monitor
simple switch closings or display computational results, Group
A could be programmed in Mode 1 to monitor a keyboard or
tape reader on an interrupt-driven basis.
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode
selection and device Reset.
Operating Modes
Mode 0 (Basic Input/Output). This functional configuration
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply written
to or read from a specific port.
The mode definitions and possible mode combinations may
seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 8255 has taken into account
things such as efficient PC board layout, control signal
definition vs. PC layout and complete functional flexibility to
support almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
• Inputs are not latched
• 16 different Input/Output configurations possible
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software
requirements in control-based applications.
MODE 0 PORT DEFINITION
A
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
B
GROUP A
PORT C
PORT A (Upper)
GROUP B
D3
D1
D0
0
0
0
0
Output
Output
0
Output
Output
0
0
0
1
Output
Output
1
Output
Input
0
0
1
0
Output
Output
2
Input
Output
0
0
1
1
Output
Output
3
Input
Input
0
1
0
0
Output
Input
4
Output
Output
0
1
0
1
Output
Input
5
Output
Input
0
1
1
0
Output
Input
6
Input
Output
0
1
1
1
Output
Input
7
Input
Input
1
0
0
0
Input
Output
8
Output
Output
1
0
0
1
Input
Output
9
Output
Input
1
0
1
0
Input
Output
10
Input
Output
1
0
1
1
Input
Output
11
Input
Input
1
1
0
0
Input
Input
12
Output
Output
Interrupt Control Functions
1
1
0
1
Input
Input
13
Output
Input
When the 8255 is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled by
setting or resetting the associated INTE flip-flop, using the bit
set/reset function of port C.
1
1
1
0
Input
Input
14
Input
Output
1
1
1
1
Input
Input
15
Input
Input
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
DON’T
CARE
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
0 1 2 3 4
0 1 0 1 0
0 0 1 1 0
0 0 0 0 1
5
1
0
1
6
0
1
1
7
1 B0
1 B1
1 B2
BIT SET/RESET FLAG
0 = ACTIVE
FIGURE 5. BIT SET/RESET FORMAT
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
5
#
PORT C
PORT B (Lower)
D4
XP8255 PLCC44
XD8255-2 DIP-40
Mode 0 (Basic Input)
tRR
RD
tIR
tHR
INPUT
tAR
tRA
CS, A1, A0
D7-D0
tRD
tDF
Mode 0 (Basic Output)
tWW
WR
tWD
tDW
D7-D0
tAW
tWA
CS, A1, A0
OUTPUT
tWB
Mode 0 Configurations
CONTROL WORD #0
CONTROL WORD #2
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
0
A
8255
1
8
4
C
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
4
B
8
0
0
0
0
1
0
8255
4
PC7 - PC4
C
D7 - D0
8
4
PC3 - PC0
PB7 - PB0
B
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
CONTROL WORD #3
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
1
A
8255
D7 - D0
0
A
D7 D6 D5 D4 D3 D2 D1 D0
0
0
PA7 - PA0
CONTROL WORD #1
1
0
1
8
4
C
4
B
8
0
0
0
0
0
1
1
PA7 - PA0
A
8255
4
PC7 - PC4
D7 - D0
C
4
PC3 - PC0
PB7 - PB0
B
6
8
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
XP8255 PLCC44
XD8255-2 DIP-40
Mode 0 Configurations (Continued)
CONTROL WORD #4
CONTROL WORD #8
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
0
A
8255
1
8
4
C
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
0
4
B
8
0
0
1
0
0
D7 - D0
PB7 - PB0
1
0
1
8
8
PC7 - PC4
PC3 - PC0
PB7 - PB0
0
1
0
0
0
1
A
8255
4
PC7 - PC4
C
D7 - D0
8
4
PC3 - PC0
PB7 - PB0
B
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
D7 D6 D5 D4 D3 D2 D1 D0
1
8
4
C
D7 - D0
4
B
8
0
0
1
0
0
1
0
PA7 - PA0
A
8255
C
D7 - D0
8
4
PC7 - PC4
4
PC3 - PC0
PB7 - PB0
B
CONTROL WORD #7
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
CONTROL WORD #11
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
1
A
8255
D7 - D0
0
PA7 - PA0
0
8255
0
8
PA7 - PA0
CONTROL WORD #10
A
0
4
B
D7 D6 D5 D4 D3 D2 D1 D0
0
C
D7 - D0
8
4
PC3 - PC0
CONTROL WORD #6
1
0
PC7 - PC4
1
4
B
0
0
D7 D6 D5 D4 D3 D2 D1 D0
4
C
0
0
8255
1
8255
0
0
CONTROL WORD #9
A
1
1
A
D7 D6 D5 D4 D3 D2 D1 D0
0
0
PA7 - PA0
CONTROL WORD #5
1
0
1
8
4
C
4
B
8
0
0
1
0
0
1
1
PA7 - PA0
A
8255
4
PC7 - PC4
D7 - D0
C
4
PC3 - PC0
PB7 - PB0
B
7
8
8
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
XP8255 PLCC44
XD8255-2 DIP-40
Mode 0 Configurations (Continued)
CONTROL WORD #12
CONTROL WORD #14
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
A
8255
1
8
4
C
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
0
4
B
8
0
1
1
1
0
1
0
8
A
8255
4
PC7 - PC4
C
D7 - D0
4
PC3 - PC0
PB7 - PB0
8
B
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0
0
0
PA7 - PA0
CONTROL WORD #13
1
0
1
0
0
A
8255
D7 - D0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
8
4
C
4
B
8
0
0
1
1
0
1
1
PA7 - PA0
8
A
8255
4
PC7 - PC4
C
D7 - D0
4
PC3 - PC0
PB7 - PB0
8
B
Operating Modes
PA7 - PA0
PC7 - PC4
PC3 - PC0
PB7 - PB0
MODE 1 (PORT A)
Mode 1 - (Strobed Input/Output). This functional configuration
provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “hand shaking”
signals. In mode 1, port A and port B use the lines on port C to
generate or accept these “hand shaking” signals.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1/0
INTE
A
PC6, PC7
1 = INPUT
0 = OUTPUT
Mode 1 Basic Function Definitions:
8
PA7-PA0
PC4
STBA
PC5
IBFA
INTRA
PC3
• Two Groups (Group A and Group B)
RD
• Each group contains one 8-bit port and one 4-bit control/data
port
• The 8-bit data port can be either input or output. Both inputs
and outputs are latched.
PC6, PC7
2
I/O
MODE 1 (PORT B)
• The 4-bit port is used for control and status of the 8-bit port.
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
Input Control Signal Definition
1
(Figures 6 and 7)
1
1
PB7-PB0
INTE
B
PC2
8
STBB
PC1
IBFB
PC0
INTRB
STB (Strobe Input)
A “low” on this input loads data into the input latch.
RD
IBF (Input Buffer Full F/F)
A “high” on this output indicates that the data has been loaded
into the input latch: in essence, an acknowledgment. IBF is set
by STB input being low and is reset by the rising edge of the
RD input.
FIGURE 6. MODE 1 INPUT
8
XP8255 PLCC44
XD8255-2 DIP-40
tST
STB
tSIB
IBF
tSIT
tRIB
INTR
tRIT
RD
tPH
INPUT FROM
PERIPHERAL
tPS
FIGURE 7. MODE 1 (STROBED INPUT)
INTR (Interrupt Request)
INTE A
A “high” on this output can be used to interrupt the CPU when
an input device is requesting service. INTR is set by the
condition: STB is a “one”, IBF is a “one” and INTE is a “one”. It
is reset by the falling edge of RD. This procedure allows an
input device to request service from the CPU by simply
strobing its data into the port.
Controlled by Bit Set/Reset of PC6.
INTE B
Controlled by Bit Set/Reset of PC2.
NOTE:
1. To strobe data into the peripheral device, the user must operate the
strobe line in a hand shaking mode. The user needs to send OBF
to the peripheral device, generates an ACK from the peripheral
device and then latch data into the peripheral device on the rising
edge of OBF.
INTE A
Controlled by bit set/reset of PC4.
INTE B
Controlled by bit set/reset of PC2.
MODE 1 (PORT A)
Output Control Signal Definition
PA7-PA0
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
(Figure 8 and 9)
1
OBF - (Output Buffer Full F/F). The OBF output will go “low”
to indicate that the CPU has written data out to the specified
port. This does not mean valid data is sent out of the port at
this time since OBF can go true before data is available. Data
is guaranteed valid at the rising edge of OBF, (See Note 1).
The OBF F/F will be set by the rising edge of the WR input and
reset by ACK input being low.
0
1
1
1/0
PC4, PC5
1 = INPUT
0 = OUTPUT
INTE
A
8
PC7
OBFA
PC6
ACKA
INTRA
PC3
WR
ACK - (Acknowledge Input). A “low” on this input informs the
8255 that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).
PC4, PC5
2
MODE 1 (PORT B)
PB7-PB0
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
INTR - (Interrupt Request). A “high” on this output can be used
to interrupt the CPU when an output device has accepted data
transmitted by the CPU. INTR is set when ACK is a “one”, OBF
is a “one” and INTE is a “one”. It is reset by the falling edge of
WR.
1
1
0
INTE
B
WR
FIGURE 8. MODE 1 OUTPUT
9
8
PC1
OBFB
PC2
ACKB
PC0
INTRB
XP8255 PLCC44
XD8255-2 DIP-40
tWOB
WR
tAOB
OBF
INTR
tWIT
ACK
tAK
tAIT
OUTPUT
tWB
FIGURE 9. MODE 1 (STROBED OUTPUT)
8
PA7-PA0
RD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1/0
1
PC4
STBA
PC5
IIBFA
PC6, PC7
1 = INPUT
0 = OUTPUT
PC6, PC7
2
PB7, PB0
WR
WR
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
INTRA
PC3
0
PA7-PA0
1
0
1
0
1/0
I/O
OBFB
PC2
PC0
PC7
OBFA
PC6
ACKA
INTRA
PC3
1
PC4, PC5
1 = INPUT
0 = OUTPUT
8
PC1
1
8
PC4, PC5
PB7, PB0
2
I/O
8
PC2
STBB
ACKB
PC1
IBFB
INTRB
PC0
INTRB
RD
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
Operating Modes
Output Operations
Mode 2 (Strobed Bidirectional Bus I/O)
OBF - (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
This functional configuration provides a means for
communicating with a peripheral device or structure on a single
8-bit bus for both transmitting and receiving data (bidirectional
bus I/O). “Hand shaking” signals are provided to maintain proper
bus flow discipline similar to Mode 1. Interrupt generation and
enable/disable functions are also available.
ACK - (Acknowledge). A “low” on this input enables the threestate output buffer of port A to send out the data. Otherwise, the
output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF). Controlled
by bit set/reset of PC4.
Mode 2 Basic Functional Definitions:
Input Operations
• Used in Group A only
STB - (Strobe Input). A “low” on this input loads data into the
input latch.
• One 8-bit, bidirectional bus Port (Port A) and a 5-bit control
Port (Port C)
IBF - (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and status
for the 8-bit, bidirectional bus port (Port A)
INTE 2 - (The INTE flip-flop associated with IBF). Controlled by
bit set/reset of PC4.
Bidirectional Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR - (Interrupt Request). A high on this output can be used
to interrupt the CPU for both input or output operations.
10
XP8255 PLCC44
XD8255-2 DIP-40
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1
INTRA
PC3
1/0 1/0 1/0
PA7-PA0
PC2-PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
8
PC7
OBFA
INTE
1
PC6
ACKA
INTE
2
PC4
STBA
PC5
IBFA
WR
GROUP B MODE
0 = MODE 0
1 = MODE 1
PC2-PC0
RD
FIGURE 11. MODE CONTROL WORD
3
I/O
FIGURE 12. MODE 2
DATA FROM
CPU TO 8255
WR
tAOB
OBF
tWOB
INTR
tAK
ACK
tST
STB
tSIB
IBF
tAD
tPS
tKD
PERIPHERAL
BUS
tRIB
tPH
RD
DATA FROM
PERIPHERAL TO 8255
DATA FROM
8255 TO PERIPHERAL
DATA FROM
8255 TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD + OBF MASK
ACK WR)
FIGURE 13. MODE 2 (BIDIRECTIONAL)
11
XP8255 PLCC44
XD8255-2 DIP-40
MODE 2 AND MODE 0 (INPUT)
MODE 2 AND MODE 0 (OUTPUT)
PC3
PA7-PA0
1
1
0
1
1/0
PC2-PC0
1 = INPUT
0 = OUTPUT
PA7-PA0
8
OBFA
PC7
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
PC6
ACKA
PC4
STBA
PC5
IBFA
PC2-PC0
PC3
INTRA
3
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1
I/O
PB7-PB0
PC6
ACKA
PC4
STBA
PC5
IBFA
PC2-PC0
3
I/O
8
MODE 2 AND MODE 1 (INPUT)
PA7-PA0
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
0
PC3
INTRA
PA7-PA0
8
PC7
OBFA
PC6
ACKA
PC4
STBA
PC5
IBFA
PB7-PB0
WR
OBFA
WR
PC3
RD
PC7
PB7, PB0
8
MODE 2 AND MODE 1 (OUTPUT)
1
1/0
8
RD
WR
1
0
PC2-PC0
1 = INPUT
0 = OUTPUT
RD
1
0
INTRA
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
1
PC1
OBFB
PC2
ACKB
PC0
INTRB
RD
WR
FIGURE 14. MODE 2 COMBINATIONS
12
8
PC7
OBFA
PC6
ACKA
PC4
STBA
PC5
IBFA
PB7-PB0
8
INTRA
8
PC2
STBB
PC1
IBFB
PC0
INTRB
XP8255 PLCC44
XD8255-2 DIP-40
MODE DEFINITION SUMMARY
MODE 0
MODE 1
MODE 2
IN
OUT
IN
OUT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
INTRB
IBFB
STBB
INTRA
STBA
IBFA
I/O
I/O
INTRB
OBFB
ACKB
INTRA
I/O
I/O
ACKA
OBFA
Special Mode Combination Considerations
GROUP A ONLY
Mode 0
or Mode 1
Only
I/O
I/O
I/O
INTRA
STBA
IBFA
ACKA
OBFA
INPUT CONFIGURATION
There are several combinations of modes possible. For any
combination, some or all of Port C lines are used for control or
status. The remaining bits are either inputs or outputs as
defined by a “Set Mode” command.
D7
D6
D5
I/O
I/O
IBFA
D4
D3
D2
INTEA INTRA INTEB
GROUP A
During a read of Port C, the state of all the Port C lines, except
the ACK and STB lines, will be placed on the data bus. In place
of the ACK and STB line states, flag status will appear on the
data bus in the PC2, PC4, and PC6 bit positions as illustrated
by Figure 17.
D1
D0
IBFB
INTRB
GROUP B
OUTPUT CONFIGURATION
D7
D6
OBFA INTEA
D5
D4
I/O
I/O
D3
D2
D0
INTRA INTEB OBFB INTRB
GROUP A
Through a “Write Port C” command, only the Port C pins
programmed as outputs in a Mode 0 group can be written. No
other pins can be affected by a “Write Port C” command, nor
can the interrupt enable flags be accessed. To write to any Port
C output programmed as an output in Mode 1 group or to
change an interrupt enable flag, the “Set/Reset Port C Bit”
command must be used.
D1
GROUP B
FIGURE 15. MODE 1 STATUS WORD FORMAT
D7
D6
OBFA INTE1
D5
IBFA
D4
D3
INTE2 INTRA
D2
D1
D0
X
X
X
GROUP A
GROUP B
(Defined by Mode 0 or Mode 1 Selection)
With a “Set/Reset Port C Bit” command, any Port C line
programmed as an output (including IBF and OBF) can be
written, or an interrupt enable flag can be either set or reset.
Port C lines programmed as inputs, including ACK and STB
lines, associated with Port C are not affected by a “Set/Reset
Port C Bit” command. Writing to the corresponding Port C bit
positions of the ACK and STB lines with the “Set Reset Port C
Bit” command will affect the Group A and Group B interrupt
enable flags, as illustrated in Figure 17.
FIGURE 16. MODE 2 STATUS WORD FORMAT
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5mA. This
feature allows the 8255 to directly drive Darlington type
drivers and high-voltage displays that require such sink or
source current.
Reading Port C Status (Figures 15 and 16)
In Mode 0, Port C transfers data to or from the peripheral
device. When the 8255 is programmed to function in Modes
13
XP8255 PLCC44
XD8255-2 DIP-40
Applications of the 8255
1 or 2, Port C generates or accepts “hand shaking” signals with
the peripheral device. Reading the contents of Port C allows
the programmer to test or verify the “status” of each peripheral
device and change the program flow accordingly.
The 8255 is a very powerful tool for interfacing peripheral
equipment to the microcomputer system. It represents the
optimum use of available pins and is flexible enough to
interface almost any I/O device without the need for additional
external logic.
There is not a special instruction to read the status information
from Port C. A normal read operation of Port C is executed to
perform this function.
INTERRUPT
ENABLE FLAG
POSITION
INTE B
PC2
ACKB (Output Mode 1)
or STBB (Input Mode 1)
INTE A2
PC4
STBA (Input Mode 1 or Mode
2)
INTE A1
PC6
ACKA (Output Mode 1 or
Mode 2)
Each peripheral device in a microcomputer system usually has
a “service routine” associated with it. The routine manages the
software interface between the device and the CPU. The
functional definition of the 8255 is programmed by the I/O
service routine and becomes an extension of the system
software. By examining the I/O devices interface
characteristics for both data transfer and timing, and matching
this information to the examples and tables in the detailed
operational description, a control word can easily be developed
to initialize the 8255 to exactl y “fit” the application. Figures
18 through 24 present a few examples of typical applications of
the 8255.
ALTERNATE PORT C
PIN SIGNAL (MODE)
FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2
INTERRUPT
REQUEST
PC3
MODE 1
(OUTPUT)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC7
PC6
PC5
PC4
8255
HIGH SPEED
PRINTER
HAMMER
RELAYS
DATA READY
ACK
PAPER FEED
FORWARD/REV.
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5
(OUTPUT) PB6
PB7
PC1
PC2
PAPER FEED
FORWARD/REV.
RIBBON
CARRIAGE SEN.
DATA READY
ACK
PC0
INTERRUPT
REQUEST
CONTROL LOGIC
AND DRIVERS
FIGURE 18. PRINTER INTERFACE
14
XP8255 PLCC44
XD8255-2 DIP-40
INTERRUPT
REQUEST
PC3
MODE 1
(INPUT)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R0
R1
R2
FULLY
R3
DECODED
R4
KEYBOARD
R5
SHIFT
CONTROL
PC4
PC5
STROBE
ACK
INTERRUPT
REQUEST
PC3
MODE 1
(INPUT)
8255
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5
(OUTPUT) PB6
PB7
B0
B1
B2
BURROUGHS
SELF-SCAN
B3
DISPLAY
B4
B5
BACKSPACE
CLEAR
8255
MODE 0
(INPUT)
DATA READY
ACK
BLANKING
CANCEL WORD
PC1
PC2
PC6
PC7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R0
R1
R2
FULLY
R3
DECODED
R4
KEYBOARD
R5
SHIFT
CONTROL
PC4
PC5
PC6
PC7
STROBE
ACK
BUST LT
TEST LT
TERMINAL
ADDRESS
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
INTERRUPT
REQUEST
FIGURE 20. KEYBOARD AND TERMINAL ADDRESS
INTERFACE
FIGURE 19. KEYBOARD AND DISPLAY INTERFACE
INTERRUPT
REQUEST
PA0
PA1
PA2
PA3
PA4
MODE 0 PA5
(OUTPUT) PA6
PA7
PC4
PC5
PC6
PC7
8255
PC0
PC1
BIT
SET/RESET PC2
PC3
LSB
PB0
PB1
PB2
LSB
MODE 0
(INPUT)
PB3
PB4
PB5
PB6
PB7
PC3
12-BIT
D/A
CONVERTER
(DAC)
PA0
PA1
PA2
PA3
PA4
PA5
MODE 1
(OUTPUT) PA6
PA7
ANALOG
OUTPUT
MSB
8255
STB DATA
SAMPLE EN
STB
8-BIT
A/D
CONVERTER
(ADC)
PC7
PC6
PC5
PC4
DATA READY
ACK
BLANKED
BLACK/WHITE
PC2
PC1
PC0
ROW STB
COLUMN STB
CURSOR H/V STB
PB0
MODE 0 PB1
(OUTPUT) PB2
PB3
PB4
PB5
PB6
PB7
ANALOG
INPUT
MSB
FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL
R0
R1
R2
CRT CONTROLLER
R3
² CHARACTER GEN.
² REFRESH BUFFER
R4
² CURSOR CONTROL
R5
SHIFT
CONTROL
CURSOR/ROW/COLUMN
ADDRESS
H&V
FIGURE 22. BASIC CRT CONTROLLER INTERFACE
15
XP8255 PLCC44
XD8255-2 DIP-40
INTERRUPT
REQUEST
INTERRUPT
REQUEST
PC3
MODE 2
8255
PC3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
D0
D1
D2
D3
D4
D5
D6
D7
PC4
PC5
PC7
PC6
DATA STB
ACK (IN)
DATA READY
ACK (OUT)
PC2
PC1
PC0
TRACK “0” SENSOR
SYNC READY
INDEX
PB0
PB1
PB2
MODE 0 PB3
(OUTPUT) PB4
PB5
PB6
PB7
FLOPPY DISK
CONTROLLER
AND DRIVE
MODE 1
(INPUT)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R0
R1
R2
R3
R4
R5
R6
R7
PC4
PC5
PC6
STB
ACK
STOP/GO
MACHINE TOOL
8255
MODE 0
(INPUT)
ENGAGE HEAD
FORWARD/REV.
READ ENABLE
WRITE ENABLE
DISC SELECT
ENABLE CRC
TEST
BUSY LT
PC0
PC1
PC2
PB0
PB1
PB2
MODE 0 PB3
(OUTPUT) PB4
PB5
PB6
PB7
FIGURE 23. BASIC FLOPPY DISC INTERFACE
B LEVEL
PAPER
TAPE
READER
START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID
CHANGE TOOL
LEFT/RIGHT
UP/DOWN
HOR. STEP STROBE
VERT. STEP STROBE
SLEW/STEP
FLUID ENABLE
EMERGENCY STOP
FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE
16
XP8255 PLCC44
XD8255-2 DIP-40
Absolute Maximum Ratings TA = +25°C
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . . GND-0.5V to VCC+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
JA (°C/W)
JC(°C/W)
CERDIP Package. . . . . . . . . . . . . . . . .
50
10
CLCC Package . . . . . . . . . . . . . . . . . .
65
14
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
PLCC Package. . . . . . . . . . . . . . . . . . .
55
N/A
MQFP Package . . . . . . . . . . . . . . . . . .
62
N/A
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature
CDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(PLCC and MQFP Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V
Operating Temperature Range
8255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
8255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
8255 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C
Die Characteristics
Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
SYMBOL
VCC = 5.0V ±10%; TA = Operating Temperature Range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
VIH
Logical One Input Voltage
2.0
2.2
-
V
VIL
Logical Zero Input Voltage
-
0.8
V
3.0
VCC -0.4
-
V
-
0.4
V
VOH
Logical One Output Voltage
IOH = -2.5mA,
IOH = -100A
VOL
Logical Zero Output Voltage
IOL +2.5mA
II
Input Leakage Current
VIN = VCC or GND, RD, CS, A1, A0, RESET, WR
-1.0
+1.0
A
IO
I/O Pin Leakage Current
VO = VCC or GND, D0 - D7
-10
+10
A
Bus Hold High Current
VO = 3.0V. Ports A, B, C
TA = -55°C
-50
-450
A
TA = +128°C
-50
-400
A
TA = -55°C
50
450
A
TA = +128°C
50
400
A
-2.5
Note 2, 4
mA
IBHH
IBHL
IDAR
Bus Hold Low Current
VO = 1.0V. Port A ONLY
Darlington Drive Current
Ports A, B, C. Test Condition 3
ICCSB
Standby Power Supply Current
VCC = 5.5V, VIN = VCC or GND. Output Open
-
10
A
ICCOP
Operating Power Supply Current
TA = +25°C, VCC = 5.0V, Typical (See Note 3)
-
1
mA/MHz
NOTES:
2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.
3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0s I/O Read/Write cycle time = 1mA).
4. Tested as VOH at -2.5mA.
Capacitance TA = +25°C
SYMBOL
PARAMETER
TYPICAL
UNITS
CIN
Input Capacitance
10
pF
CI/O
I/O Capacitance
20
pF
17
TEST CONDITIONS
FREQ = 1MHz, All Measurements are referenced to
device GND
XP8255 PLCC44
XD8255-2 DIP-40
AC Electrical Specifications
VCC = +5V 10%, GND = 0V; TA = Operating Temperature Range
8255-5
SYMBOL
PARAMETER
8255
MIN
MAX
MIN
MAX
UNITS
TEST
CONDITIONS
READ TIMING
(1) tAR
Address Stable Before RD
0
-
0
-
ns
(2) tRA
Address Stable After RD
0
-
0
-
ns
(3) tRR
RD Pulse Width
250
-
150
-
ns
(4) tRD
Data Valid From RD
-
200
-
120
ns
1
(5) tDF
Data Float After RD
10
75
10
75
ns
2
(6) tRV
Time Between RDs and/or WRs
300
-
300
-
ns
WRITE TIMING
(7) tAW
Address Stable Before WR
0
-
0
-
ns
(8) tWA
Address Stable After WR
20
-
20
-
ns
(9) tWW
WR Pulse Width
100
-
100
-
ns
(10) tDW
Data Valid to WR High
100
-
100
-
ns
(11) tWD
Data Valid After WR High
30
-
30
-
ns
OTHER TIMING
(12) tWB
WR = 1 to Output
-
350
-
350
ns
(13) tIR
Peripheral Data Before RD
0
-
0
-
ns
(14) tHR
Peripheral Data After RD
0
-
0
-
ns
(15) tAK
ACK Pulse Width
200
-
200
-
ns
(16) tST
STB Pulse Width
100
-
100
-
ns
(17) tPS
Peripheral Data Before STB High
20
-
20
-
ns
(18) tPH
Peripheral Data After STB High
50
-
50
-
ns
(19) tAD
ACK = 0 to Output
-
175
-
175
ns
1
(20) tKD
ACK = 1 to Output Float
20
250
20
250
ns
2
(21) tWOB
WR = 1 to OBF = 0
-
150
-
150
ns
1
(22) tAOB
ACK = 0 to OBF = 1
-
150
-
150
ns
1
(23) tSIB
STB = 0 to IBF = 1
-
150
-
150
ns
1
(24) tRIB
RD = 1 to IBF = 0
-
150
-
150
ns
1
(25) tRIT
RD = 0 to INTR = 0
-
200
-
200
ns
1
(26) tSIT
STB = 1 to INTR = 1
-
150
-
150
ns
1
(27) tAIT
ACK = 1 to INTR = 1
-
150
-
150
ns
1
(28) tWIT
WR = 0 to INTR = 0
-
200
-
200
ns
1
(29) tRES
Reset Pulse Width
500
-
500
-
ns
1, (Note)
NOTE: Period of initial Reset pulse after power-on must be at least 50sec. Subsequent Reset pulses may be 500ns minimum.
18
1
XP8255 PLCC44
XD8255-2 DIP-40
Timing Waveforms
tRR (3)
RD
tIR (13)
tHR (14)
INPUT
tAR (1)
tRA (2)
CS, A1, A0
D7-D0
tRD (4)
tDF (5)
FIGURE 25. MODE 0 (BASIC INPUT)
tWW (9)
WR
tDW
(10)
tWD (11)
D7-D0
tAW (7)
tWA (8)
CS, A1, A0
OUTPUT
tWS (12)
FIGURE 26. MODE 0 (BASIC OUTPUT)
tST (16)
STB
IBF
tSIB
(23)
tSIT
(26)
tRIB (24)
tRIT
(25)
INTR
RD
tPH
(18)
INPUT FROM
PERIPHERAL
tPS (17)
FIGURE 27. MODE 1 (STROBED INPUT)
19
XP8255 PLCC44
XD8255-2 DIP-40
Timing Waveforms
(Continued)
tWOB (21)
WR
tAOB (22)
OBF
tWIT
(28)
INTR
ACK
tAK (15)
tAIT (27)
OUTPUT
tWB (12)
FIGURE 28. MODE 1 (STROBED OUTPUT)
DATA FROM
CPU TO 8255
WR
(NOTE)
tAOB
(22)
OBF
tWOB
(21)
INTR
tAK
(15)
ACK
tST
(16)
STB
(NOTE)
IBF
tSIB
(23)
tAD (19)
tPS (17)
tKD
(20)
PERIPHERAL
BUS
tRIB (24)
tPH (18)
RD
DATA FROM
PERIPHERAL TO 8255
DATA FROM
8255 TO PERIPHERAL
DATA FROM
8255 TO CPU
FIGURE 29. MODE 2 (BIDIRECTIONAL)
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD OBF MASK
ACK WR)
20
XP8255 PLCC44
XD8255-2 DIP-40
Timing Waveforms
(Continued)
A0-A1,
CS
A0-A1,
CS
tWA (8)
tAW (7)
tDW (10)
tRA (2)
tAR (1)
DATA
BUS
tRR (3)
RD
tWD (11)
(4) tRD
WR
tDF (5)
DATA
BUS
VALID
tWW (9)
HIGH IMPEDANCE
FIGURE 30. WRITE TIMING
FIGURE 31. READ TIMING
AC Test Circuit
AC Testing Input, Output Waveforms
V1
INPUT
OUTPUT
VIH + 0.4V
VOH
1.5V
R1
OUTPUT FROM
DEVICE UNDER
TEST
VIL - 0.4V
TEST
POINT
R2
1.5V
VOL
AC Testing: All AC Parameters tested as per test circuits. Input RISE
and FALL times are driven at 1ns/V.
C1
(SEE NOTE)
TEST CONDITION DEFINITION TABLE
NOTE: Includes STRAY and JIG Capacitance
21
TEST CONDITION
V1
R1
R2
C1
1
1.7V
523
Open
150pF
2
VCC
2k
1.7k
50pF
3
1.5V
750
Open
50pF
XP8255 PLCC44
XD8255-2 DIP-40
Burn-In Circuits
F14
F4
5
36
F2
F3
6
35
F5
F5
F11
9
37
F15
F12
F1
10
36
F11
F13
F10
11
35
F12
F14
F6
12
34
F13
F15
F7
13
33
F14
F8
14
32
F15
F9
15
31
F11
F10
16
30
F12
F6
17
29
13
F9
14
27
F10
15
26
F6
16
25
F13
F7
17
24
F14
F8
18
23
F15
19
22
F11
20
21
F12
F9
F10
F11
F12
VCC
C1
18 19 20 21 22 23 24 25 26 27 28
C1
NOTES:
NOTES:
1. VCC = 5.5V 0.5V
1. C1 = 0.01F minimum
2. VIH = 4.5V 10%
2. All resistors are 47k 5%
3. VIL = -0.2V to 0.4V
3. f0 = 100kHz 10%
4. GND = 0V
4. f1 = f0 2; f2 = f1 2; . . . ; f15 = f14 2
22
F13
F8
VCC
28
38
F0
F15
F14
29
39
8
F15
12
30
1 44 43 42 41 40
F11
F7
11
31
2
F12
F6
10
32
3
F10
F10
9
33
4
F9
F1
8
34
5
F8
F0
7
6
7
F7
GND
GND
F2
37
F14
4
F13
F13
F9
F11
38
F12
3
F7
F12
F8
F8
F11
39
F9
40
2
F4
1
F7
F3
F6
F6
PLCC
CERDIP
XP8255 PLCC44
XD8255-2 DIP-40
23
22
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