XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
1 Features
•
•
•
•
•
1
The 2004 devices have a 10.5-kΩ series base
resistor to allow operation directly from CMOS
devices that use supply voltages of 6 V to 15 V. The
required input current of the 2004 device is
below that of the 2003 devices, and the required
voltage is less than that required by the XD/L200X
device.
500-mA-Rated Collector Current (Single Output)
High-Voltage Outputs: 50 V
Output Clamp Diodes
Inputs Compatible With Various Types of Logic
Relay-Driver Applications
2 Applications
•
•
•
•
•
•
Relay Drivers
Stepper and DC Brushed Motor Drivers
Lamp Drivers
Display Drivers (LED and Gas Discharge)
Line Drivers
Logic Buffers
4 Simplified Block Diagram
9
COM
1
16
1B
1C
2
15
2B
3 Description
.
The XD/L200X devices are high-voltage, high-current
Darlington transistor arrays. Each consists of seven
NPN Darlington pairs that feature high-voltage
outputs with common-cathode clamp diodes for
switching inductive loads.
2C
3
14
3B
.
3C
4
13
4B
4C
5
12
5B
The collector-current rating of a single Darlington pair
is 500 mA. The Darlington pairs can be paralleled for
higher current capability. Applications include relay
drivers, hammer drivers, lamp drivers, display drivers
(LED and gas discharge), line drivers, and logic
buffers. For 100-V (otherwise interchangeable)
versions of the 2003 devices, see the SLRS023
data sheet for the SN75468 and SN75469 devices.
5C
6
11
6B
6C
7
7B
The XD/L200X device is designed specifically for use
with 14-V to 25-V PMOS devices. Each input of this
device has a Zener diode and resistor in series to
control the input current to a safe limit. The
2003 devices have a 2.7-kΩ series base resistor
for each Darlington pair for operation directly with
TTL or 5-V CMOS devices.
1
1
10
7C
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
5 Pin Configuration and Functions
1B
2B
3B
4B
5B
6B
7B
E
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1C
2C
3C
4C
5C
6C
7C
COM
Pin Functions
PIN
NAME
NO.
1B
1
2B
2
3B
3
4B
4
5B
5
6B
6
7B
7
1C
16
2C
15
3C
14
4C
13
5C
12
6C
11
7C
10
COM
E
(1)
I/O (1)
DESCRIPTION
I
Channel 1 through 7 Darlington base input
O
Channel 1 through 7 Darlington collector output
9
—
Common cathode node for flyback diodes (required for inductive loads)
8
—
Common emitter shared by all channels (typically tied to ground)
I = Input, O = Output
2
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted) (1)
MIN
VCC
Collector-emitter voltage
Clamp diode reverse voltage
VI
IOK
(2)
50
V
V
Peak collector current, See Figure 4 and Figure 5
500
mA
Output clamp current
500
mA
Total emitter-terminal current
–2.5
A
TJ
Operating virtual junction temperature
XD/L200X
–20
70
–40
105
–40
85
–40
105
Lead temperature for 1.6 mm (1/16 inch) from case for 10 seconds
(2)
V
30
Operating free-air temperature range
(1)
UNIT
50
Input voltage (2)
TA
Tstg
MAX
Storage temperature
–65
°C
150
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Collector-emitter voltage (non-V devices)
TJ
Junction temperature
MIN
MAX
0
50
UNIT
V
–40
125
°C
6.4 Thermal Information
XD/L200X
THERMAL METRIC (1)
D
(SOIC)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
73
67
64
108
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
36
54
n/a
33.6
°C/W
RθJB
Junction-to-board thermal resistance
n/a
n/a
n/a
51.9
°C/W
ψJT
Junction-to-top characterization parameter
n/a
n/a
n/a
2.1
°C/W
ψJB
Junction-to-board characterization parameter
n/a
n/a
n/a
51.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
3
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
6.5 Electrical Characteristics: XD/L2002
TA = 25°C
PARAMETER
TEST FIGURE
VI(on)
ON-state input voltage
Figure 14
VCE = 2 V,
VOH
High-level output voltage after
switching
Figure 18
VS = 50 V, IO = 300 mA
VCE(sat)
Collector-emitter saturation
voltage
Figure 12
VF
Clamp forward voltage
ICEX
Collector cutoff current
XD/L2002
TEST CONDITIONS
MIN
TYP
IC = 300 mA
13
mV
IC = 100 mA
0.9
1.1
II = 350 μA,
IC = 200 mA
1
1.3
II = 500 μA,
IC = 350 mA
1.2
1.6
Figure 15
IF = 350 mA
Figure 9
VCE = 50 V,
II = 0
50
Figure 10
VCE = 50 V,
TA = 70°C
II = 0
100
VI = 6 V
500
IC = 500 μA
OFF-state input current
Figure 10
VCE = 50 V,
II
Input current
Figure 11
VI = 17 V
IR
Clamp reverse current
Figure 14
Ci
Input capacitance
VR = 50 V
1.7
50
V
2
V
μA
μA
65
0.82
1.25
TA = 70°C
mA
100
VR = 50 V
VI = 0,
V
VS – 20
II = 250 μA,
II(off)
UNIT
MAX
μA
50
f = 1 MHz
25
pF
6.6 Electrical Characteristics: 2003 and 2004
TA = 25°C
PARAMETER
TEST
FIGURE
TEST CONDITIONS
2003
MIN
2004
TYP
MAX
MIN
TYP
IC = 125 mA
VI(on)
ON-state input
voltage
Figure 14
VCE = 2 V
2.4
IC = 250 mA
2.7
6
IC = 275 mA
7
Figure 18
VCE(sat)
Collector-emitter
saturation voltage
Figure 13
ICEX
Collector cutoff
current
VS = 50 V, IO = 300 mA
8
VS – 20
VS – 20
IC = 100 mA
0.9
1.1
0.9
1.1
II = 350 μA,
IC = 200 mA
1
1.3
1
1.3
II = 500 μA,
IC = 350 mA
1.2
1.6
1.2
1.6
Figure 9
VCE = 50 V,
II = 0
50
50
Figure 10
VCE = 50 V,
TA = 70°C
II = 0
100
100
Clamp forward
voltage
Figure 16
IF = 350 mA
II(off)
Off-state input
current
Figure 11
VCE = 50 V,
TA = 70°C,
II
Input current
Figure 12
VI = 6 V
IC = 500 μA
50
2
65
0.93
Ci
Input capacitance
Figure 15
VR = 50 V
TA = 70°C
VI = 0,
f = 1 MHz
4
μA
15
2
V
μA
65
1.35
VI = 5 V
VR = 50 V
1.7
50
VI = 12 V
Clamp reverse
current
V
500
1.7
VI = 3.85 V
IR
mV
II = 250 μA,
VF
V
3
IC = 350 mA
VOH
UNIT
5
IC = 200 mA
IC = 300 mA
High-level output
voltage after
switching
MAX
0.35
0.5
1
1.45
50
50
100
100
25
15
25
mA
μA
pF
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
6.7 Electrical Characteristics: 2003
TA = 25°C
PARAMETER
VI(on)
VOH
VCE(sat)
ON-state input voltage
High-level output voltage after
switching
Collector-emitter saturation voltage
TEST FIGURE
Figure 14
VCE = 2 V
Figure 18
2003
TEST
CONDITIONS
MIN
2.4
IC = 250 mA
2.7
IC = 300 mA
3
II = 250 μA,
IC = 100 mA
II = 350 μA,
II = 500 μA,
II = 0
ICEX
Collector cutoff current
Figure 9
VCE = 50 V,
VF
Clamp forward voltage
Figure 16
IF = 350 mA
II(off)
OFF-state input current
Figure 11
VCE = 50 V,
II
Input current
Figure 12
VI = 3.85 V
IR
Clamp reverse current
Figure 15
VR = 50 V
Ci
Input capacitance
VI = 0,
MAX
IC = 200 mA
VS = 50 V, IO = 300 mA
Figure 13
TYP
VS – 50
1.1
IC = 200 mA
1
1.3
IC = 350 mA
1.2
1.6
1.7
50
15
V
50
μA
2
V
μA
65
0.93
f = 1 MHz
V
mV
0.9
IC = 500 μA
UNIT
1.35
mA
50
μA
25
pF
6.8 Electrical Characteristics: 2003
TA = –40°C to 105°C
PARAMETER
VI(on)
VOH
VCE(sat)
ON-state input voltage
High-level output voltage after
switching
Collector-emitter saturation voltage
TEST FIGURE
Figure 14
TEST CONDITIONS
VCE = 2 V
Figure 18
2.9
IC = 300 mA
3
II = 350 μA,
II = 500 μA,
II = 0
Collector cutoff current
Figure 9
VCE = 50 V,
Clamp forward voltage
Figure 16
IF = 350 mA
II(off)
OFF-state input current
Figure 11
VCE = 50 V,
II
Input current
Figure 12
VI = 3.85 V
IR
Clamp reverse current
Figure 15
VR = 50 V
Ci
Input capacitance
VI = 0,
5
MAX
2.7
IC = 100 mA
VF
TYP
IC = 250 mA
II = 250 μA,
ICEX
MIN
IC = 200 mA
VS = 50 V, IO = 300 mA
Figure 13
2003
VS – 50
1.2
IC = 200 mA
1
1.4
IC = 350 mA
1.2
1.7
1.7
30
15
V
100
μA
2.2
V
1.35
mA
100
μA
25
pF
μA
65
0.93
f = 1 MHz
V
mV
0.9
IC = 500 μA
UNIT
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
6.9 Electrical Characteristics: 2003 and 2004
over recommended operating conditions (unless otherwise noted)
TEST
FIGURE
PARAMETER
TEST CONDITIONS
2003
MIN
2004
TYP
MAX
MIN
TYP
MAX
IC = 125 mA
ON-state input
voltage
VI(on)
Figure 14
VCE = 2 V
5
IC = 200 mA
2.7
IC = 250 mA
2.9
6
IC = 275 mA
7
IC = 300 mA
High-level output
voltage after
switching
VCE(sat)
Collector-emitter
saturation voltage
Collector cutoff
current
ICEX
Figure 18
VS = 50 V, IO = 300 mA
8
VS – 50
II = 350 μA,
II = 500 μA,
Figure 9
VCE = 50 V,
II = 0
Figure 10
VCE = 50 V,
TA = 70°C
II = 0
100
VI = 6 V
500
Clamp forward
voltage
Figure 16
IF = 350 mA
II(off)
OFF-state input
current
Figure 11
VCE = 50 V,
TA = 70°C,
0.9
1.2
IC = 200 mA
1
IC = 350 mA
1.2
Figure 12
0.9
1.1
1.4
1
1.3
1.7
1.2
1.6
100
1.7
IC = 500 μA
VI = 3.85 V
Input current
mV
IC = 100 mA
VF
II
VS – 50
II = 250 μA,
Figure 13
2.3
1.7
65
0.93
Clamp reverse
current
Ci
Input capacitance
Figure 15
50
TA = 25°C
VR = 50 V
VI = 0,
f = 1 MHz
15
2
μA
V
μA
65
1.35
VI = 5 V
VR = 50 V
V
50
0.35
0.5
1
1.45
VI = 12 V
IR
V
3
IC = 350 mA
VOH
UNIT
100
50
100
100
25
15
25
mA
μA
pF
6.10 Switching Characteristics: XD/L2002, 2003, 2004
TA = 25°C
PARAMETER
TEST CONDITIONS
XD/L2002, 2003,
2004
MIN
UNIT
TYP
MAX
tPLH
Propagation delay time, low- to high-level output
See Figure 17
0.25
1
μs
tPHL
Propagation delay time, high- to low-level output
See Figure 17
0.25
1
μs
6.11 Switching Characteristics: 2003
TA = 25°C
PARAMETER
TEST CONDITIONS
2003
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
See Figure 17
0.25
1
μs
tPHL
Propagation delay time, high- to low-level output
See Figure 17
0.25
1
μs
6
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
6.12 Switching Characteristics: 2003
TA = –40°C to 105°C
PARAMETER
2003
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
See Figure 17
1
10
μs
tPHL
Propagation delay time, high- to low-level output
See Figure 17
1
10
μs
6.13 Switching Characteristics: 2003, 2004
over recommended operating conditions (unless otherwise noted)
PARAMETER
2003, 2004
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
See Figure 17
1
10
μs
tPHL
Propagation delay time, high- to low-level output
See Figure 17
1
10
μs
6.14 Typical Characteristics
VCE(sat)
VCE(sat) - Collector-Emitter Saturation Voltage - V
VCE(sat)
VCE(sat) - Collector-Emitter Saturation Voltage - V
2.5
TA = 25°C
2
II = 250 µA
II = 350 µA
II = 500 µA
1.5
1
0.5
0
0
100
200
300
400
500
600
700
800
2.5
TA = 25°C
II = 250 µA
2
II = 350 µA
1.5
II = 500 µA
1
0.5
0
0
100
200
300
400
500
600
700
800
IC(tot) - Total Collector Current - mA
IC - Collector Current - mA
Figure 1. Collector-Emitter Saturation Voltage
vs Collector Current (One Darlington)
Figure 2. Collector-Emitter Saturation Voltage
vs Total Collector Current (Two Darlingtons in Parallel)
7
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
Typical Characteristics (continued)
600
500
450
IIC
C - Maximum Collector Current - mA
RL = 10 Ω
TA = 25°C
IC
IC - Collector Current - mA
400
VS = 10 V
350
VS = 8 V
300
250
200
150
100
50
0
500
N=1
400
N=4
N=3
300
N=2
N=6
200 N = 7
N=5
100
TA = 70°C
N = Number of Outputs
Conducting Simultaneously
0
25
0
50
75
100
125
150
200
175
0
10
20
30
40
II - Input Current - µA
50
60
70
80
90 100
Duty Cycle - %
Figure 3. Collector Current vs Input Current
Figure 4. D Package Maximum Collector Current
vs Duty Cycle
600
2000
TJ = -40°C to 105°C
IIC
C - Maximum Collector Current - mA
1800
500
1600
400
Input Current – µA
N=1
N=3
N=2
N=4
300
N=5
N=6
N=7
200
1200
1000
Maximum
800
600
100
0
1400
400
TA = 85°C
N = Number of Outputs
Conducting Simultaneously
0
10
20
30
40
50
60
70
Typical
200
80
0
90 100
2
2.5
Duty Cycle - %
3
3.5
4
Input Voltage – V
4.5
5
Figure 6. Maximum and Typical Input Current
vs Input Voltage
Figure 5. N Package Maximum Collector Current
vs Duty Cycle
500
2.1
V CE = 2 V
TJ = -40°C to 105°C
TJ = -40°C to 105°C
450
400
Output Current – mA
Maximum VCE(sat) Voltage – V
1.9
1.7
1.5
Maximum
1.3
350
300
250
Minimum
200
1.1
150
Typical
0.9
100
200
300
400
100
250
500
350
450
550
650
Input Current – µA
Output Current – mA
Figure 7. Maximum and Typical Saturated VCE
vs Output Current
Figure 8. Minimum Output Current vs Input Current
8
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
7 Parameter Measurement Information
Open
Open
VCE
ICEX
ICEX
Open
VI
Figure 9. ICEX Test Circuit
Open
II(off)
Figure 10. ICEX Test Circuit
Open
VCE
II(on)
IC
Open
VI
Figure 11. II(off) Test Circuit
Figure 12. II Test Circuit
II is fixed for measuring VCE(sat), variable for measuring hFE.
Open
hFE =
II
VCE
Open
IC
II
VCE
VI(on)
IC
Figure 13. hFE, VCE(sat) Test Circuit
VCE
Figure 14. VI(on) Test Circuit
9
IC
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
Parameter Measurement Information (continued)
VR
IR
VF
Open
Open
Figure 15. IR Test Circuit
Figure 16. VF Test Circuit
Figure 17. Propagation Delay-Time Waveforms
200 W
≤10 ns
≤5 ns
90%
1.5 V
Input
VIH
(see Note C)
90%
1.5 V
10%
10%
40 µs
0V
VOH
Output
VOL
VOLTAGE WAVEFORMS
The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
CL includes probe and jig capacitance.
For testing the 2003 device, 2003 device, and 2003 devices, VIH = 3 V; for the XD/L2002 device,
VIH = 13 V; for the 2004 and the 2004 devices, VIH = 8 V.
Figure 18. Latch-Up Test Circuit and Voltage Waveforms
10
IF
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to
integration of 7 Darlington transistors of the device that are capable of sinking up to 500 mA and wide GPIO
range capability.
The 2003 device comprises seven high-voltage, high-current NPN Darlington transistor pairs. All units
feature a common emitter and open collector outputs. To maximize their effectiveness, these units contain
suppression diodes for inductive loads. The 2003 device has a series base resistor to each Darlington pair,
thus allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The 2003
device offers solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and
LEDs. Applications requiring sink currents beyond the capability of a single output may be accommodated by
paralleling the outputs.
This device can operate over a wide temperature range (–40°C to 105°C).
8.2 Functional Block Diagrams
All resistor values shown are nominal. The collector-emitter diode is a parasitic structure and should not be used
to conduct current. If the collectors go below GND, an external Schottky diode should be added to clamp
negative undershoots.
COM
7V
Output C
10.5 NŸ
Input B
7.2 NŸ
E
3 NŸ
Figure 19. XD/L2002 Block Diagram
COM
COM
Output C
RB
2.7 NŸ
Input B
Output C
RB
10.5 NŸ
Input B
7.2 NŸ
3 NŸ
E
7.2 NŸ
3 NŸ
Figure 21. 2004 Block Diagram
Figure 20.2003
Block Diagram
11
E
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
8.3 Feature Description
Each channel of the 2003 device consists of Darlington connected NPN transistors. This connection
creates the effect of a single transistor with a very high-current gain (β2). This can be as high as 10,000 A/A at
certain currents. The very high β allows for high-output current drive with a very low input current, essentially
equating to operation with low GPIO voltages.
The GPIO voltage is converted to base current through the 2.7-kΩ resistor connected between the input and
base of the predriver Darlington NPN. The 7.2-kΩ and 3-kΩ resistors connected between the base and emitter of
each respective NPN act as pulldowns and suppress the amount of leakage that may occur from the input.
The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kick-back diode.
In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diodes are
forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device
pins.
8.4 Device Functional Modes
8.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, 2003 device is able to drive inductive loads and
suppress the kick-back voltage through the internal free-wheeling diodes.
8.4.2 Resistive Load Drive
When driving a resistive load, a pullup resistor is needed in order for 2003 device to sink current and for
there to be a logic high level. The COM pin can be left floating for these applications.
12
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
9 Application and Implementation
9.1 Application Information
Typically, the 2003 device drives a high-voltage or high-current (or both) peripheral from an MCU or logic
device that cannot tolerate these conditions. This design is a common application of 2003 device, driving
inductive loads. This includes motors, solenoids and relays. Figure 22 shows a model for each load type.
9.2 Typical Application
3.3-V Logic
3.3-V Logic
2003
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
VSUP
3.3-V Logic
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
COM
VSUP
Figure 22. 2003 Device as Inductive Load Driver
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
GPIO voltage
3.3 V or 5 V
Coil supply voltage
12 V to 48 V
Number of channels
7
Output current (RCOIL)
20 mA to 300 mA per channel
Duty cycle
100%
13
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
9.2.2 Detailed Design Procedure
When using 2003 device in a coil driving application, determine the following:
• Input voltage range
• Temperature range
• Output and drive current
• Power dissipation
9.2.2.1 Drive Current
The coil voltage (VSUP), coil resistance (RCOIL), and low-level output voltage (VCE(SAT) or VOL) determine the coil
current.
ICOIL = (VSUP – VCE(SAT)) / RCOIL
(1)
9.2.2.2 Low-Level Output Voltage
The low-level output voltage (VOL) is the same as VCE(SAT) and can be determined by, Figure 1, Figure 2, or
Figure 7.
9.2.2.3 Power Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by Figure 4 or Figure 5.
For a more accurate determination of number of coils possible, use the below equation to calculate 2003
device on-chip power dissipation PD:
N
PD = å VOLi ´ ILi
i=1
where
•
•
N is the number of channels active together
VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT)
(2)
To ensure reliability of 2003 device and the system, the on-chip power dissipation must be lower that or
equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation Equation 3.
PD(MAX) =
(T
J(MAX)
- TA )
qJA
where
•
•
•
TJ(max) is the target maximum junction temperature
TA is the operating ambient temperature
RθJA is the package junction to ambient thermal resistance
Limit the die junction temperature of the 2003 device to less than 125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
14
(3)
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
9.2.3 Application Curves
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-0.004
14
12
Output voltage - V
Output voltage - V
The characterization data shown in Figure 23 and Figure 24 were generated using the 2003 device drivingan
OMRON G5NB relay and under the following conditions: VIN = 5 V, VSUP= 12 V, and RCOIL= 2.8 kΩ.
10
8
6
4
2
0
0.004
0.008
Time (s)
0.012
0
-0.004
0.016
D001
Figure 23. Output Response With Activation of Coil
(Turnon)
0
0.004
0.008
Time (s)
0.012
0.016
D001
Figure 24. Output Response With De-activation of Coil
(Turnoff)
15
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
9.3 System Examples
XD/L2002
ULN2002A
VSS
V
16
1
16
2
15
2
15
3
14
3
14
4
4
13
13
5
12
6
11
7
10
8
9
12
6
11
7
10
8
9
Lam
Test
TTL
Output
Figure 25. P-MOS to Load
VDD
V
1
5
P-MOS
Output
2003
VCC
Figure 26. TTL to Load
VCC
V
2004
V
2003
1
16
1
16
2
15
2
15
3
14
3
14
4
13
4
13
5
12
5
12
6
11
6
11
7
10
7
10
8
9
8
9
RP
CMOS
Output
TTL
Output
Figure 27. Buffer for Higher Current Loads
Figure 28. Use of Pullup Resistors to Increase
Drive Current
16
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
17
16
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
18
17
XD2002 DIP16 XD2003 DIP16 XD2004 DIP16
XL2003 SOP16 XL2004 SOP16
19
工商网监
湘ICP备2023018690号
