XL74LS148

XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 74LS147 D Encode 10-Line Decimal to 4-Line BCD D Applications Include: D D − Keyboard Encoding − Range Selection 4 5 6 7 8 C B GND 74LS148 Encode 8 Data Lines to 3-Line Binary (Octal) Applications Include: − n-Bit Encoding − Code Converters and Generators 74LS147 74LS148 (TOP VIEW) (TOP VIEW) 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC NC D 3 2 1 9 A 4 5 6 7 EI A2 A1 GND TYPE TYPICAL DATA DELAY TYPICAL POWER DISSIPATION ’147 10 ns 225 mW ’148 10 ns 190 mW ’LS147 15 ns 60 mW ’LS148 15 ns 60 mW 1 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC E0 GS 3 2 1 0 A0 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 description/ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The 74LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54/74LS load, respectively. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA PDIP − N 0°C to 70°C SOIC − D SOP − NS Tube 74LS148 Tube 74LS148 Tape and reel 74LS148 Tape and reel 74LS148 TOP-SIDE MARKING 74LS148 74LS148 74LS148 FUNCTION TABLE − 74LS147 INPUTS OUTPUTS 1 2 3 4 5 6 7 8 9 D C B A H H H H H H H H H H H H H X X X X X X X X L L H H L X X X X X X X L H L H H H X X X X X X L H H H L L L X X X X X L H H H H L L H X X X X L H H H H H L H L X X X L H H H H H H L H H X X L H H H H H H H H L L X L H H H H H H H H H L H L H H H H H H H H H H H L H = high logic level, L = low logic level, X = irrelevant FUNCTION TABLE − 74LS148 INPUTS OUTPUTS EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO H X X X X X X X X H H H H H L H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L L H L H L X X X X X L H H L H L L H L X X X X L H H H L H H L H L X X X L H H H H H L L L H L X X L H H H H H H L H L H L X L H H H H H H H H L L H L L H H H H H H H H H H L H H = high logic level, L = low logic level, X = irrelevant 2 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 74LS147 logic diagram (positive logic) (11) 1 2 3 4 (12) (9) (13) (1) (7) 5 6 7 8 9 A B (2) (3) (4) (6) C (5) (14) (10) Pin numbers shown are for D, J, N, and W packages. 3 D XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 74LS148 logic diagram (positive logic) 0 (10) (15) 1 2 (14) (11) 4 6 7 EI A0 (13) (1) (7) 5 G5 (12) (9) 3 EO A1 (2) (3) (4) (6) (5) Pin numbers shown are for D, J, N, NS, and W packages. 4 A2 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 schematics of inputs and outputs 74LS148/74LS148 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC
 Ω NOM Req Input Output 0 input (’148): Req = 2 kΩ NOM All other inputs: Req = 4 kΩ NOM ’LS147, ’LS148 TYPICAL OF ALL OUTPUTS EQUIVALENT OF ALL INPUTS VCC VCC 120 Ω NOM Req Input Output 74LS148 inputs 1–7: R eq = 9 kΩ NOM All other inputs: Req = 18 kΩ NOM 5 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI :74LS147,74LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V 74LS147,74LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Inter-emitter voltage: ’148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. For 74LS148 circuits, this rating applies between any two of the eight data lines, 0 through 7. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) 74LS VCC IOH Supply voltage IOL TA Low-level output current MIN NOM 4.5 5 High-level output current Operating free-air temperature MAX MIN NOM 5.5 4.75 5 −800 125 MAX MIN NOM 5.25 4.5 5 −800 16 −55 74LS 74LS 70 MAX MIN NOM 5.5 4.75 5 −400 16 0 74LS 4 −55 125 0 MAX UNIT 5.25 V −400 µA 8 mA 70 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS† PARAMETER VIH VIL High-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL 74LS147 MIN TYP‡ MAX 74LS148 MIN TYP‡ MAX 2 2 Low-level input voltage V 0.8 0.8 V −1.5 −1.5 V VCC = MIN, VCC = MIN, VIL = 0.8 V, II = −12 mA VIH = 2 V, IOH = −800 µA Low-level output voltage VCC = MIN, VIL = 0.8 V, VIH = 2 V, IOL = 16 mA II Input current at maximum input voltage VCC = MIN, VI = 5.5 V 1 High-level input current 0 input IIH VCC = MAX, VI = 2.4 V 40 Low-level input current 0 input IIL VCC = MAX, VI = 0.4 V −1.6 2.4 3.3 2.4 0.2 0.4 3.3 0.2 V 0.4 1 40 Any input except 0 UNIT 80 V mA µA A −1.6 IOS Any input except 0 Short-circuit output current§ ICC Supply current VCC = MAX VCC = MAX (See Note 5) −35 −85 −3.2 −35 −85 Condition 1 50 70 40 60 Condition 2 42 62 35 55 mA mA mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 5: For 74LS147, I CC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For 74LS148 I CC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. 74LS147 switching characteristics, V CC = 5 V, TA = 255C (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any Any tPLH tPHL Any Any WAVEFORM TEST CONDITIONS In-phase output Out-of-phase output 7 CL = 15 pF, RL = 400 Ω MIN TYP MAX 9 14 7 11 13 19 12 19 UNIT ns ns XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 74LS148 switching characteristics, VCC = 5 V, TA = 255C (see Figure 1) PARAMETER† FROM (INPUT) TO (OUTPUT) tPLH tPHL 1–7 A0, A1, or A2 In-phase output tPLH tPHL 1–7 A0, A1, or A2 Out-of-phase output tPLH tPHL 0–7 EO Out-of-phase output tPLH tPHL 0–7 GS In-phase output tPLH tPHL EI A0, A1, or A2 In-phase output tPLH tPHL EI GS In-phase output tPLH tPHL EI EO In-phase output WAVEFORM TEST CONDITIONS MIN CL = 15 pF, RL = 400 Ω TYP MAX 10 15 9 14 13 19 12 19 6 10 14 25 18 30 14 25 10 15 10 15 8 12 10 15 10 15 17 30 UNIT ns ns ns ns ns ns ns † tPLH = propagation delay time, low-to-high-level output. tPHL = propagation delay time, high-to-low-level output. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIH VIL High-level input voltage VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage II Input current at maximum input voltage All other inputs IIH High-level input current All other inputs IIL Low-level input current TEST CONDITIONS† 74LS MIN TYP‡ MAX 2 2 Low-level input voltage VCC = MIN, VCC = MIN, VIL = 0.8 V, II = −18 mA VIH = 2 V, IOH = −400 µA VCC = MIN, VIH = 2 V, VIL = VIL MAX IOL = 4 mA VCC = MAX, VI = 7 V VCC = MAX, VI = 2.7 V VCC = MAX, VI = 0.4 V 2.5 0.25 Supply current 0.8 V −1.5 V 2.7 0.4 3.4 V 0.25 0.4 0.35 0.5 V VCC = MAX −20 VCC = MAX (See Note 6) 0.2 0.2 0.1 0.1 40 40 20 20 −0.8 −0.8 −0.4 −0.4 mA 74LS148 inputs 1–7 ICC V 0.7 IOL = 8 mA 74LS148 inputs 1–7 IOS UNIT −1.5 3.4 74LS148 inputs 1–7 All other inputs Short-circuit output current§ 74LS MIN TYP‡ MAX −100 −20 −100 Condition 1 12 20 12 20 Condition 2 10 17 10 17 µA A mA mA mA † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time. NOTE 6: For 74LS147, I CC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. For 74LS148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC (Condition 2) is measured with all inputs and outputs open. 8 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 74LS147 switching characteristics, VCC = 5 V, TA = 255C (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL Any Any tPLH tPHL Any Any WAVEFORM TEST CONDITIONS MIN In-phase output Out-of-phase output CL = 15 pF, RL = 2 kkΩ TYP MAX 12 18 12 18 21 33 15 23 TYP MAX 14 18 15 25 20 36 16 29 UNIT ns ns 74LS148 switching characteristics, V CC = 5 V, TA = 255C (see Figure 2) PARAMETER† FROM (INPUT) TO (OUTPUT) tPLH tPHL 1–7 A0, A1, or A2 In-phase output tPLH tPHL 1–7 A0, A1, or A2 Out-of-phase output tPLH tPHL 0–7 EO Out-of-phase output tPLH tPHL 0–7 GS In-phase output tPLH tPHL EI A0, A1, or A2 In-phase output tPLH tPHL EI GS In-phase output tPLH tPHL EI EO In-phase output WAVEFORM † tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output 9 TEST CONDITIONS CL = 15 pF, RL = 2 kΩ k MIN 7 18 25 40 35 55 9 21 16 25 12 25 12 17 14 36 12 21 23 35 UNIT ns ns ns ns ns ns ns XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 DEVICES VCC Test Point VCC RL From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse 1.5 V 1 kΩ Test Point S2 LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V S1 (see Note B) CL (see Note A) RL (see Note B) RL From Output Under Test VCC From Output Under Test Test Point 1.5 V 0V tw Low-Level Pulse 1.5 V tsu Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.5 V 0V In-Phase Output (see Note D) tPHL VOH 1.5 V Out-of-Phase Output (see Note D) 0V 1.5 V 1.5 V Waveform 1 (see Notes C and D) tPLZ VOH 1.5 V 1.5 V VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.5 V VOL tPZH tPLH 1.5 V 0V tPZL VOL tPHL 1.5 V 3V Output Control (low-level enabling) 1.5 V tPLH 3V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th VOL + 0.5 V tPHZ VOH 1.5 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 74LS devices. F. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 10 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 PARAMETER MEASUREMENT INFORMATION SERIES 74LS DEVICES VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse 1.3 V 5 kΩ Test Point S2 LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.3 V S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 1.3 V 0V tw Low-Level Pulse 1.3 V tsu Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V Output Control (low-level enabling) 1.3 V 0V tPLH In-Phase Output (see Note D) 1.3 V 0V 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL tPZH tPLH VOH 1.3 V 1.3 V VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 3V 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th VOL + 0.5 V tPHZ VOH 1.3 V VOH − 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 11 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 APPLICATION INFORMATION 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI 74LS148 EO A0 A1 Enable (active low) 74LS148 A2 GS EO A0 A1 A2 GS ’08/’LS08 0 1 2 Priority Flag (active low) 3 Encoded Data (active low) 16-Line Data (active low) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 EI 0 1 2 3 4 5 6 7 EI 74LS148 EO A0 A1 Enable (active low) 74LS148 A2 GS EO A0 A1 A2 GS ’HC00 0 1 2 3 Priority Flag (active high) Encoded Data (active high) Figure 3. Priority Encoder for 16 Bits Because the 74LS147 and 74LS148 devices are combinational logic circuits, wrong addresses can appear during input transients. Moreover, for the 74LS148 devices, a change from high to low at EI can cause a transient low on GS when all inputs are high. This must be considered when strobing the outputs. 12 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 13 12 XL74LS148 SOP16 / XD74LS148 DIP16 / XD74LS147 DIP16 14 12