XL07Z

XD07 DIP-8 / XL07Z SOP-8 FEATURES PIN CONFIGURATION Low VOS: 75 μV maximum Low VOS drift: 1.3 μV/°C maximum Ultrastable vs. time: 1.5 μV per month maximum Low noise: 0.6 μV p-p maximum Wide input voltage range: ±14 V typical Wide supply voltage range: ±3 V to ±18 V 125°C temperature-tested dice VOS TRIM 1 8 07 VOS TRIM –IN 2 7 V+ +IN 3 6 OUT V– 4 5 NC NC = NO CONNECT Figure 1. APPLICATIONS Wireless base station control circuits Optical network control circuits Instrumentation Sensors and controls Thermocouples Resistor thermal detectors (RTDs) Strain bridges Shunt current measurements Precision filters The wide input voltage range of ±13 V minimum combined with a high CMRR of 106 dB (XL07Z) and high input impedance provide high accuracy in the noninverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variations in temperature is excellent. The accuracy and stability of the XD07 , even at high gain, combined with the freedom from external nulling have made the XD07 an industry standard for instrumentation applications. GENERAL DESCRIPTION The XD07 is available in two standard performance gra des. The XL07Z is specified for operation over the 0 °C to 70°C range, and the XD07Z is specified over the −40°C to +85°C temperature range. The XD07 has very low input offset voltage (75 μV maximum for XL07Z) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The XD07also features low input bias current ( ±4 nA for the XL07Z) and high open -loop gain (200 V/mV for the XL07Z). The low offset and high open-loop gain make the XD07 particularly useful for high gain instrumentation applications. The XD07 is available in epoxy 8-lead PDIP and 8-lead narrow SOIC packages. For CERDIP and TO-99 packages and standard microcircuit drawing (SMD) versions, see the XD07 V+ 7 R2B1 R2A1 1 R1A (OPTIONAL NULL) R7 C1 8 R1B Q19 Q10 Q9 NONINVERTING INPUT 3 INVERTING INPUT R3 Q3 Q5 Q6 Q4 Q27 Q21 Q23 Q22 Q24 C3 Q12 C2 R10 Q16 Q26 Q20 Q15 Q2 Q25 Q14 2 Q13 4 V– 1 R2A OUT 6 Q17 R5 Q1 R4 R9 Q11 Q8 Q7 AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE. Figure 2. Simplified Schematic 1 Q18 R6 R8 XD07 DIP-8 / XL07Z SOP-8 SPECIFICATIONS OP07E ELECTRICAL CHARACTERISTICS VS = ±15 V, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS TA = 25°C Input Offset Voltage 1 Long-Term VOS Stability 2 Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Symbol VOS VOS/Time IOS IB en p-p en Input Noise Current Input Noise Current Density In p-p In Input Resistance, Differential Mode 4 Input Resistance, Common Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain RIN RINCM IVR CMRR PSRR AVO 0°C ≤ TA ≤ 70°C Input Offset Voltage1 Voltage Drift Without External Trim4 Voltage Drift with External Trim3 Input Offset Current Input Offset Current Drift Input Bias Current Input Bias Current Drift Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain OUTPUT CHARACTERISTICS TA = 25°C Output Voltage Swing 0°C ≤ TA ≤ 70°C Output Voltage Swing VOS TCVOS TCVOSN IOS TCIOS IB TCIB IVR CMRR PSRR AVO Conditions Min Typ Max Unit 30 0.3 0.5 ±1.2 0.35 10.3 10.0 9.6 14 0.32 0.14 0.12 50 160 ±14 123 5 500 400 75 1.5 3.8 ±4.0 0.6 18.0 13.0 11.0 30 0.80 0.23 0.17 μV μV/Month nA nA μV p-p nV/√Hz nV/√Hz nV/√Hz pA p-p pA/√Hz pA/√Hz pA/√Hz MΩ GΩ V dB μV/V V/mV V/mV 130 1.3 1.3 5.3 35 ±5.5 35 180 45 0.3 0.3 0.9 8 ±1.5 13 ±13.5 123 7 450 0.1 Hz to 10 Hz 3 fO = 10 Hz fO = 100 Hz3 fO = 1 kHz fO = 10 Hz fO = 100 Hz3 fO = 1 kHz 15 VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 ±13 106 200 150 RP = 20 kΩ VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V ±13 103 20 32 μV μV/°C μV/°C nA pA/°C nA pA/°C V dB μV/V V/mV VO RL ≥ 10 kΩ RL ≥ 2 kΩ RL ≥ 1 kΩ ±12.5 ±12.0 ±10.5 ±13.0 ±12.8 ±12.0 V V V VO RL ≥ 2 kΩ ±12 ±12.6 V 2 XD07 DIP-8 / XL07Z SOP-8 Parameter DYNAMIC PERFORMANCE TA = 25°C Slew Rate Closed-Loop Bandwidth Open-Loop Output Resistance Power Consumption Symbol Conditions Min Typ SR BW RO Pd RL ≥ 2 kΩ3 AVOL = 1 5 VO = 0, IO = 0 VS = ±15 V, No load VS = ±3 V, No load RP = 20 kΩ 0.1 0.4 0.3 0.6 60 75 4 ±4 Offset Adjustment Range Max 120 6 Unit V/μs MHz Ω mW mW mV Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is sample tested. 3 Sample tested. 4 Guaranteed by design. 5 Guaranteed but not tested. 1 2 OP07C ELECTRICAL CHARACTERISTICS VS = ±15 V, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS TA = 25°C Input Offset Voltage 1 Long-Term VOS Stability 2 Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Symbol VOS VOS/Time IOS IB en p-p en Input Noise Current Input Noise Current Density In p-p In Input Resistance, Differential Mode 4 Input Resistance, Common Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain RIN RINCM IVR CMRR PSRR AVO −40°C ≤ TA ≤ +85°C Input Offset Voltage1 Voltage Drift Without External Trim4 Voltage Drift with External Trim3 Input Offset Current Input Offset Current Drift Input Bias Current Input Bias Current Drift Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain VOS TCVOS TCVOSN IOS TCIOS IB TCIB IVR CMRR PSRR AVO Conditions Min 0.1 Hz to 10 Hz3 fO = 10 Hz fO = 100 Hz 3 fO = 1 kHz fO = 10 Hz fO = 100 Hz3 fO = 1 kHz 8 VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 ±13 100 120 100 RP = 20 kΩ VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V 3 ±13 97 100 Typ Max Unit 60 0.4 0.8 ±1.8 0.38 10.5 10.2 9.8 15 0.35 0.15 0.13 33 120 ±14 120 7 400 400 150 2.0 6.0 ±7.0 0.65 20.0 13.5 11.5 35 0.90 0.27 0.18 μV μV/Month nA nA μV p-p nV/√Hz nV/√Hz nV/√Hz pA p-p pA/√Hz pA/√Hz pA/√Hz MΩ GΩ V dB μV/V V/mV V/mV 85 0.5 0.4 1.6 12 ±2.2 18 ±13.5 120 10 400 250 1.8 1.6 8.0 50 ±9.0 50 32 51 μV μV/°C μV/°C nA pA/°C nA pA/°C V dB μV/V V/mV XD07 DIP-8 / XL07Z SOP-8 Parameter OUTPUT CHARACTERISTICS TA = 25°C Output Voltage Swing −40°C ≤ TA ≤ +85°C Output Voltage Swing DYNAMIC PERFORMANCE TA = 25°C Slew Rate Closed-Loop Bandwidth Open-Loop Output Resistance Power Consumption Offset Adjustment Range Symbol Conditions Min Typ Max VO RL ≥ 10 kΩ RL ≥ 2 kΩ RL ≥ 1 kΩ ±12.0 ±11.5 ±13.0 ±12.8 ±12.0 V V V VO RL ≥ 2 kΩ ±12 ±12.6 V SR BW RO Pd RL ≥ 2 kΩ3 AVOL = 1 5 VO = 0, IO = 0 VS = ±15 V, No load VS = ±3 V, No load RP = 20 kΩ 0.1 0.4 0.3 0.6 60 80 4 ±4 V/μs MHz Ω mW mW mV 150 8 Unit Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is sample tested. 3 Sample tested. 4 Guaranteed by design. 5 Guaranteed but not tested. 1 2 4 XD07 DIP-8 / XL07Z SOP-8 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage (VS) Input Voltage1 Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range S and P Packages Operating Temperature Range Ratings ±22 V ±22 V ±30 V Indefinite XD07 XL07Z Junction Temperature Lead Temperature, Soldering (60 sec) 0°C to 70°C −40°C to +85°C 150°C 300°C 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −65°C to +125°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 8-Lead PDIP (P-Suffix) 8-Lead SOIC_N (S-Suffix) For supply voltages less than ±22 V, the absolute maximum input voltage is equal to the supply voltage. θJA 103 158 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 5 θJC 43 43 Unit °C/W °C/W XD07 DIP-8 / XL07Z SOP-8 TYPICAL PERFORMANCE CHARACTERISTICS 1000 1.0 MAXIMUM ERROR REFERRED TO INPUT (mV) VS = ±15V 900 OPEN-LOOP GAIN (V/mV) 800 700 600 500 400 300 200 100 0 –75 –50 –25 0 25 50 75 100 VS = ±15V TA = 25°C 0.8 0.6 0.4 XL07Z 0.2 XD07 0 100 125 1k Figure 3. Open-Loop Gain vs. Temperature 1.2 MAXIMUM ERROR REFERRED TO INPUT (mV) VS = ±15V TA = 25°C, TA = 70°C 25 ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µV) 100k Figure 6. Maximum Error vs. Source Resistance 30 20 15 THERMAL SHOCK RESPONSE BAND 10 DEVICE IMMERSED IN 70°C OIL BATH 5 0 –20 0 20 40 60 80 VS = ±15V 0°C ≤ TA ≤ 70°C 1.0 0.8 0.6 0.4 XL07Z 0.2 XD07 0 100 100 Figure 4. Offset Voltage Change due to Thermal Shock 30 NONINVERTING INPUT BIAS CURRENT (nA) VS = ±15V TA = 25°C 20 15 XL07Z XD07 5 0 0 1 2 10k 100k Figure 7. Maximum Error vs. Source Resistance 25 10 1k MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω) TIME (Seconds) ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µV) 10k MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω) TEMPERATURE (°C) 3 4 20 AT |VDIFF| ≤ 1.0V, | IB | ≤ 7nA (OP07C) VS = ±15V TA = 25°C 10 0 –10 –20 –30 –30 5 TIME AFTER SUPPLY TURN-ON (Minutes) –20 –10 0 10 20 DIFFERENTIAL INPUT VALUE (V) Figure 5. Warm-Up Drift Figure 8. Input Bias Current vs. Differential Input Voltage 6 30 XD07 DIP-8 / XL07Z SOP-8 4 1000 INPUT NOISE VOLTAGE (nV/ Hz) INPUT BIAS CURRENT (nA) VS = ±15V 3 XL07Z 2 XD07 1 RS1 = RS2 = 200kΩ THERMAL NOISE SOURCE RESISTORS INCLUDED EXCLUDED 100 RS = 0 10 VS = ±15V TA = 25°C 0 –75 1 –50 –25 0 25 50 75 100 125 1 10 Figure 9. Input Bias Current vs. Temperature 1000 Figure 12. Total Input Noise Voltage vs. Frequency 2.5 10 VS = ±15V TA = 25°C VS = ±15V RMS NOISE (µV) 2.0 1.5 1.0 XL07Z 1 0.5 XD07 0 –100 –75 –50 –25 0 25 50 75 0.1 100 100 1k TEMPERATURE (°C) 10k 100k BANDWIDTH (Hz) Figure 10. Input Offset Current vs. Temperature Figure 13. Input Wideband Noise vs. Bandwidth, 0.1 Hz to Frequency Indicated 130 REFERRED TO INPUT 5mV/CM AT OUTPUT 120 110 XL07Z CMRR (dB) VOLTAGE (200nV/DIV) INPUT OFFSET CURRENT (nA) 100 FREQUENCY (Hz) TEMPERATURE (°C) 100 90 80 70 60 1 10 100 1k FREQUENCY (Hz) TIME (1s/DIV) Figure 14. CMRR vs. Frequency Figure 11. Low Frequency Noise 7 10k 100k XD07 DIP-8 / XL07Z SOP-8 120 100 VS = ±15V TA = 25°C TA = 25°C 110 80 CLOSED-LOOP GAIN (dB) XL07Z PSRR (dB) 100 90 80 70 60 40 20 0 60 50 0.1 1 10 100 1k –20 10 10k 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. PSRR vs. Frequency Figure 18. Closed-Loop Frequency Response for Various Gain Configurations 1000 28 VS = ±15V TA = 25°C TA = 25°C PEAK-TO-PEAK AMPLITUDE (V) 24 OPEN-LOOP GAIN (V/mV) 800 600 400 200 20 16 12 8 4 0 1k 0 0 ±5 ±10 ±15 ±20 10k Figure 16. Open-Loop Gain vs. Power Supply Voltage 120 20 VS = ±15V VIN = ±10mV TA = 25°C 80 15 MAXIMUM OUTPUT (V) OPEN-LOOP GAIN (dB) 1M Figure 19. Maximum Output Swing vs. Frequency VS = ±15V TA = 25°C 100 100k FREQUENCY (Hz) POWER SUPPLY VOLTAGE (V) 60 40 20 0 POSITIVE SWING NEGATIVE SWING 10 5 –20 –40 0.1 1 10 100 1k 10k 100k 1M 0 100 10M 1k 10k LOAD RESISTANCE TO GROUND (Ω) FREQUENCY (Hz) Figure 17. Open-Loop Frequency Response Figure 20. Maximum Output Voltage vs. Load Resistance 8 XD07 DIP-8 / XL07Z SOP-8 30.0 ABSOLUTE VALUE OF OFFSET VOLTAGE (µV) 1000 POWER CONSUMPTION (mW) TA = 25°C 100 10 1 0 10 20 30 40 50 VOS TRIMMED TO < 5µV AT 25°C NULLING POT = 20kΩ 22.5 XL07Z 15.0 XL07Z XD07 7.5 XD07 0 –100 60 –75 –50 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) Figure 21. Power Consumption vs. Power Supply 50 75 100 12 30 25 VIN (PIN 3) = +10mV, VO = –15V VIN (PIN 3) = –10mV, VO = +15V 0.3µV/MONTH TREND LINE 8 0.3µV/MONTH TREND LINE 4 0.2µV/MONTH TREND LINE 0.3µV/MONTH TREND LINE 0 0.2µV/MONTH TREND LINE 0.2µV/MONTH TREND LINE –4 –8 –12 15 –16 0 1 2 3 4 0 TIME FROM OUTPUT BEING SHORTED (Minutes) VS = ±15V RS = 100Ω OP07C 63.75 42.50 OP07E 21.25 –50 –25 0 25 50 75 100 2 3 4 5 6 7 8 9 Figure 25. Offset Voltage Drift vs. Time 85.00 0 –75 1 TIME (Months) Figure 22. Output Short-Circuit Current vs. Time ABSOLUTE VALUE OF OFFSET VOLTAGE (µV) 25 16 VS = ±15V TA = 25°C 20 0 Figure 24. Trimmed Offset Voltage vs. Temperature TOTAL DRIFT WITH TIME (µV) OUTPUT SHORT-CIRCUIT CURRENT (mA) 35 –25 TEMPERATURE (°C) 125 TEMPERATURE (°C) Figure 23. Untrimmed Offset Voltage vs. Temperature 9 10 11 12 XD07 DIP-8 / XL07Z SOP-8 TYPICAL APPLICATIONS RF EIN R1 SUM MODE BIAS R3 3kΩ V+ 2 – 3 4 V– EIN ±10V EO R1 10kΩ FD333 D1 7 2 7 2 – – 3 + V– 4 V– R2 10kΩ EO = –EIN RF –IB RF R1 Figure 26. Typical Offset Voltage Test Circuit 3 FD333 D2 6 XD07 6 XD07 4 R2 100kΩ + 6 + A1 R5 10kΩ V+ – AD7115 OR AD8510 R5 6 10kΩ R4 10kΩ V+ 7 2 7 XL07Z 3 R3 10kΩ V+ EO 0V TO +10V + 4 V– R1 R2 = R3 R4 Figure 29. Absolute Value Circuit RF EIN R1 SUM MODE BIAS R4 10kΩ E1 E2 E3 R1 10kΩ 2 +15V R2 10kΩ 2 3 6 XL07Z R1 6 10kΩ EO 4 V– 4 6 A2 3 + 4 R2 100kΩ + + R5 2.5kΩ – XL07Z – A1 – 3 2 V+ 7 7 XL07Z 7 R3 10kΩ R3 3kΩ V+ V– EO = –EIN RF + IB RF R1 NOTES 1. PINOUT SHOWN FOR P PACKAGE –15V Figure 27. Typical Low Frequency Noise Circuit Figure 30. High Speed, Low VOS Composite Amplifier R4 10kΩ E1 20kΩ V+ E2 1 – 2 – INPUT + 8 7 XD07 3 + 6 E3 R1 10kΩ +15V R2 10kΩ 2 7 – R3 10kΩ XD07 3 OUT EO + R5 2.5kΩ 4 6 4 –15V NOTES 1. PINOUT SHOWN FOR P PACKAGE V– Figure 28. Optional Offset Nulling Circuit Figure 31. Adjustment-Free Precision Summing Amplifier 10 EO XD07 DIP-8 / XL07Z SOP-8 DIP8 11 10 XD07 DIP-8 / XL07Z SOP-8 SOP8 12 10