XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
D
D
D
D
D
D
D
D
D
D
D
D
D
12-Bit-Resolution A/D Converter
10-µs Conversion Time Over Operating
Temperature
11 Analog Input Channels
3 Built-In Self-Test Modes
Inherent Sample-and-Hold Function
Linearity Error . . . ± 1 LSB Max
On-Chip System Clock
End-of-Conversion Output
Unipolar or Bipolar Output Operation
(Signed Binary With Respect to 1/2 the
Applied Voltage Reference)
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
CMOS Technology
DIP/SOP/SSOP
(TOP VIEW)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
description
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
EOC
I/O CLOCK
DATA INPUT
DATA OUT
CS
REF +
REF –
AIN10
AIN9
The 2543 are 12-bit, switched- capacitor,
successive-approximation, analog-todigital converters. Each device, with three control
inputs [chip select (CS), the input-output clock, and
the address input (DATA INPUT)], is designed for
communication with the serial port of a host processor
or peripheral through a serial 3-state output. The
device allows high-speed data transfers from the
host.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The
sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high
to indicate that conversion is complete. The converter incorporated in the device features differential
high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating
temperature range.
1
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
AVAILABLE OPTIONS
PACKAGE
TA
DIP
– 40°C to 85°C
SOP
SSOP
XL2543
XD2543N
XL2543-SS
functional block diagram
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
1
2
3
4
5
6
7
8
9
11
12
REF +
REF –
14
13
12-Bit
Analog-to-Digital
Converter
(Switched Capacitors)
Sample-andHold
Function
14-Channel
Analog
Multiplexer
12
4
Output
Data
Register
Input Address
Register
12
12-to-1 Data
Selector and
Driver
16
DATA
OUT
4
3
Control Logic
and I/O
Counters
Self-Test
Reference
19
DATA
INPUT
I/O CLOCK
CS
17
18
15
2
EOC
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
Terminal Functions
TERMINAL
I/O
DESCRIPTION
1 – 9,
11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should
be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input
voltage into a capacitance of 60 pF.
CS
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup
time.
DATA INPUT
17
I
Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.
The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK.
After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state
and is driven to the logic level corresponding to the MSB/LSB† value of the previous conversion result. The
next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and
the remaining bits are shifted out in order.
EOC
19
O
End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and the data is ready for transfer.
GND
10
I/O CLOCK
18
I
Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of the I/O
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of I/O CLOCK.
4. It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.
REF +
14
I
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The
maximum input voltage range is determined by the difference between the voltage applied to this terminal and
the voltage applied to the REF – terminal.
REF –
13
I
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF –.
NAME
NO.
AIN0 – AIN10
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
VCC
20
Positive supply voltage
† MSB/LSB = Most significant bit / least significant bit
3
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
absolute maximum ratings over operating free-air temperature range (unless otherwise
noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V
Negative reference voltage, Vref – . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.1 V
Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Peak total input current, II (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Operating free-air temperature range, TA: 2543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °C to 70°C
2543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF – and GND wired together (unless otherwise noted).
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
4.5
5
5.5
Positive reference voltage, Vref + (see Note 2)
VCC
0
Negative reference voltage, Vref – (see Note 2)
Differential reference voltage, Vref + – Vref – (see Note 2)
2.5
Analog input voltage (see Note 2)
0
High-level control input voltage, VIH
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
Low-level control input voltage, VIL
Clock frequency at I/O CLOCK
Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4)
Hold time, CS low after last I/O CLOCK↓, th(CS) (see Figure 5)
V
V
V
VCC + 0.1
VCC
2
0
Setup time, address bits at DATA INPUT before I/O CLOCK↑, tsu(A) (see Figure 4)
VCC
UNIT
V
V
V
0.8
V
4.1
MHz
100
ns
0
ns
0
ns
1.425
µs
Pulse duration, I/O CLOCK high, twH(I/O)
120
ns
Pulse duration, I/O CLOCK low, twL(I/O)
120
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5)
Transition time, I/O CLOCK high to low, tt(I/O) (see Note 4 and Figure 6)
Transition time, DATA INPUT and CS, tt(CS)
Operating free-air temperature, TA
ns
1
µs
10
µs
2543
0
70
2543
– 40
85
°C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied
to REF– convert as all zeros (000000000000).
3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control
input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data acquisition applications
where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
4
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
electrical characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2543
TYP†
MAX
VOH
High level output voltage
High-level
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
IOH = –1.6 mA
IOH = –20 µA
VOL
Low level output voltage
Low-level
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
IOL = 1.6 mA
IOL = 20 µA
IOZ
High-impedance
g
off-state output
current
VO = VCC,
VO = 0,
CS at VCC
1
2.5
CS at VCC
1
– 2.5
IIH
IIL
High-level input current
1
2.5
Low-level input current
VI = VCC
VI = 0
1
– 2.5
µA
ICC
Operating supply current
CS at 0 V
1
2.5
mA
ICC(PD)
Power-down current
For all digital inputs,
0 ≤ VI ≤ 0.5 V or VI ≥ VCC – 0.5 V
4
25
µA
Selected channel leakage
current
Maximum static analog
reference current into REF +
Ci
Input
capacitance
Selected channel at VCC,
2.4
UNIT
V
VCC – 0.1
0.4
0.1
Unselected channel at 0 V
–1
Vref – = GND
1
2.5
Analog inputs
30
60
Control inputs
5
15
† All typical values are at VCC = 5 V, TA = 25°C.
5
µA
µA
1
Selected channel at 0 V,
Unselected channel at VCC
Vref + = VCC,
V
µA
µA
pF
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
Linearity error (see Note 5)
See Figure 2
±1
LSB
Differential linearity error
See Figure 2
±1
LSB
EO
Offset error (see Note 6)
See Note 2 and
Figure 2
± 1.5
LSB
EG
Gain error (see Note 6)
See Note 2 and
Figure 2
±1
LSB
ET
Total unadjusted error (see Note 7)
± 1.75
LSB
EL
ED
Self-test output code (see Table 3 and Note 8)
t(conv)
Conversion time
DATA INPUT = 1011
2048
DATA INPUT = 1100
0
DATA INPUT = 1101
4095
See Figures 9 – 14
8
10
10 + total
I/O CLOCK
periods +
td(I/O-EOC)
µs
tc
Total cycle time (access, sample, and conversion)
See Figures 9 – 14
and Note 9
tacq
Channel acquisition time (sample)
See Figures 9 – 14
and Note 9
tv
td(I/O-DATA)
Valid time, DATA OUT remains valid after I/O CLOCK↓
See Figure 6
Delay time, I/O CLOCK↓ to DATA OUT valid
See Figure 6
td(I/O-EOC)
td(EOC-DATA)
Delay time, last I/O CLOCK↓ to EOC↓
See Figure 7
Delay time, EOC↑ to DATA OUT (MSB / LSB)
See Figure 8
100
ns
tPZH, tPZL
tPHZ, tPLZ
Enable time, CS↓ to DATA OUT (MSB / LSB driven)
See Figure 3
0.7
1.3
µs
Disable time, CS↑ to DATA OUT (high impedance)
See Figure 3
70
150
ns
tr(EOC)
tf(EOC)
Rise time, EOC
See Figure 8
15
50
ns
Fall time, EOC
See Figure 7
15
50
ns
tr(bus)
tf(bus)
Rise time, data bus
See Figure 6
15
50
ns
Fall time, data bus
See Figure 6
15
50
ns
5
µs
td(I/O-CS)
Delay time, last I/O CLOCK↓ to CS↓ to abort conversion
(see Note 10)
4
12
10
µs
I/O
CLOCK
periods
ns
1.5
150
ns
2.2
µs
† All typical values are at TA = 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that
applied to REF – convert as all zeros (000000000000).
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.
9. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7).
10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs
of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether
the conversion is aborted or the conversion results are valid.
6
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PARAMETER MEASUREMENT INFORMATION
15 V
50 Ω
C1
10 µF
C2
0.1 µF
C3
470 pF
10 Ω
_
U1
+
VI
C1
10 µF
2543
AIN0 – AIN10
C3
470 pF
C2
0.1 µF
50 Ω
– 15 V
LOCATION
DESCRIPTION
U1
C1
C2
C3
PART NUMBER
OP27
10-µF 35-V tantalum capacitor
0.1-µF ceramic NPO SMD capacitor
470-pF porcelain Hi-Q SMD capacitor
—
—
AVX 12105C104KA105 or equivalent
Johanson 201S420471JG4L or equivalent
Figure 1. Analog Input Buffer to Analog Inputs AIN0 – AIN10
VCC
Test Point
VCC
Test Point
RL = 2.18 kΩ
RL = 2.18 kΩ
EOC
DATA OUT
CL = 50 pF
12 kΩ
12 kΩ
CL = 100 pF
Figure 2. Load Circuits
Data
Valid
2V
CS
tPZH, tPZL
DATA
OUT
2V
0.8 V
DATA INPUT
0.8 V
tPHZ, tPLZ
2.4 V
90%
0.4 V
10%
th(A)
tsu(A)
I/O CLOCK
0.8 V
Figure 4. DATA INPUT and I/O CLOCK
Voltage Waveforms
Figure 3. DATA OUT to Hi-Z Voltage Waveforms
7
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PARAMETER MEASUREMENT INFORMATION
2V
CS
0.8 V
tsu(CS)
I/O CLOCK
th(CS)
Last
Clock
0.8 V
0.8 V
NOTE A: To ensure full conversion accuracy, it is recommended that no input signal change
occurs while a conversion is ongoing.
Figure 5. CS and I/O CLOCK Voltage Waveforms
tt(I/O)
tt(I/O)
I/O CLOCK
2V
2V
0.8 V
0.8 V
0.8 V
I/O CLOCK Period
td(I/O-DATA)
tv
DATA OUT
2.4 V
0.4 V
2.4 V
0.4 V
tr(bus), tf(bus)
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
Last
Clock
0.8 V
td(I/O-EOC)
2.4 V
EOC
0.4 V
tf(EOC)
Figure 7. I/O CLOCK and EOC Voltage Waveforms
tr(EOC)
EOC
2.4 V
0.4 V
td(EOC-DATA)
2.4 V
0.4 V
DATA OUT
Valid MSB
Figure 8. EOC and DATA OUT Voltage Waveforms
8
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
8
11
12
Sample Cycle B
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
1
Hi-Z State
DATA
OUT
A11
A10
A9
A8
A7
A6
A5
A4
A1
A0
Previous Conversion Data
ÎÎÎ
ÎÎ
ÎÎ
Î
Î
Î
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ
MSB
DATA
INPUT
7
B7
B6
B5
B4
MSB
B3
B2
B1
B11
ÎÎ
ÎÎ
ÎÎÎÎ
LSB
C7
B0
LSB
EOC
t(conv)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A11
A10
A9
8
11
A8
A7
A6
A5
A4
A1
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
B7
B6
MSB
B5
12
1
Sample Cycle B
Previous Conversion Data
MSB
DATA
INPUT
7
B4
B3
B2
B1
A0
B11
Low Level
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎ
LSB
C7
B0
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
t(conv)
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
9
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
1
I/O CLOCK
2
3
4
5
Access Cycle B
A7
DATA OUT
A6
A5
7
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
8
Sample Cycle B
A4
A3
A2
A1
Previous Conversion Data
Hi-Z
A0
1
B7
ÎÎÎ
ÎÎ
ÎÎ
Î
Î
Î
ÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
MSB
DATA INPUT
6
B7
B6
B5
B4
MSB
B3
LSB
B2
B1
B0
C7
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t(conv)
A/D Conversion
Interval
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
CS
(see Note A)
1
I/O CLOCK
2
3
4
5
Access Cycle B
DATA OUT
A7
A6
A5
7
8
1
Sample Cycle B
A4
A3
A2
A1
Previous Conversion Data
A0
Low Level
ÎÎÎ
ÎÎ
Î
Î
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
MSB
DATA INPUT
6
B7
MSB
B6
B5
B4
B3
B2
ÎÎ
ÎÎ
ÎÎÎÎ
LSB
B1
B7
C7
B0
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
t(conv)
A/D Conversion
Interval
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
10
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
7
8
15
16
Sample Cycle B
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
1
Hi-Z State
DATA
OUT
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
MSB
B15
ÎÎ
ÎÎÎ
LSB
DATA
INPUT
B7
B6
B5
B3
B4
MSB
B2
B1
B0
C7
LSB
EOC
t(conv)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 13. Timing for 16-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
Access Cycle B
DATA
OUT
A15
A14
A13
7
8
15
1
Sample Cycle B
A12
A11
A10
A9
A8
A1
ÎÎ
Î
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Previous Conversion Data
MSB
16
A0
Low Level
ÎÎÎÎ
Î
ÎÎÎÎÎ
LSB
DATA
INPUT
B7
MSB
B6
B5
B4
B3
B2
B1
B15
B0
C7
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Initialize
t(conv)
A/D Conversion
Interval
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First
11
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PRINCIPLES OF OPERATION
Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA INPUT
and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7 – D4), a 2-bit data length
select (D3 – D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are
applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the
input data register.
During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long depending on
the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last
falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle and 2) the
actual conversion cycle.
I/O cycle
The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending
on the selected output data length.
During the I/O cycle, the following two operations take place simultaneously.
An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is
shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first
eight clocks during 12- or 16-clock I/O transfers.
The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the
first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output
data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the
first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.
conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to
I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O
cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion.
12
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PRINCIPLES OF OPERATION
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data
register is set to all zeroes. The contents of the output data register are random, and the first conversion result
should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O
cycle. The first conversion after the device has returned from the power-down state may not read accurately
due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output
register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N – 1) conversion cycle
The conversion cycle just prior to the current I/O cycle
Next (N + 1) I/O cycle
The I/O period that follows the current conversion cycle
Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even
when this corrupts the output data from the previous conversion. The current conversion is begun
immediately after the twelfth falling edge of the current I/O cycle.
13
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PRINCIPLES OF OPERATION
data input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the data word with the MSB first.
Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data input-register
format).
Table 2. Input-Register Format
INPUT DATA BYTE
ADDRESS BITS
FUNCTION SELECT
Select input channel
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Select test voltage
(Vref + – Vref –)/2
Vref –
Vref +
Software power down
D7
(MSB)
D6
D5
D4
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
0
1
0
1
1
1
1
0
Output data length
8 bits
12 bits
16 bits
Output data format
MSB first
LSB first (LSBF)
L1
L0
LSBF
BIP
D3
D2
D1
D0
(LSB)
0
X†
1
1
0
1
0
1
Unipolar (binary)
0
Bipolar (BIP) 2s complement
1
† X represents a do not care condition.
data input address bits
The four MSBs (D7 – D4) of the data register address one of the 11 input channels, a reference-test voltage,
or the power-down mode. The address bits affect the current conversion, which is the conversion that
immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+ – Vref –.
14
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PRINCIPLES OF OPERATION
analog input, test, and power-down mode
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type
to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on
the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held
on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
Table 3. Analog-Channel-Select Address
VALUE SHIFTED INTO
DATA INPUT
ANALOG INPUT
SELECTED
BINARY
HEX
AIN0
0000
0
AIN1
0001
1
AIN2
0010
2
AIN3
0011
3
AIN4
0100
4
AIN5
0101
5
AIN6
0110
6
AIN7
0111
7
AIN8
1000
8
AIN9
1001
9
AIN10
1010
A
Table 4. Test-Mode-Select Address
INTERNAL
SELF-TEST
VOLTAGE
SELECTED†
VALUE SHIFTED INTO
DATA INPUT
BINARY
HEX
1011
B
Vref + – Vref –
2
UNIPOLAR OUTPUT
RESULT (HEX)‡
800
Vref –
1100
C
000
Vref +
1101
D
FFF
† Vref + is the voltage applied to REF +, and Vref – is the voltage applied to REF –.
‡ The output results shown are the ideal values and may vary with the reference stability
and with internal offsets.
Table 5. Power-Down-Select Address
INPUT COMMAND
Power down
VALUE SHIFTED INTO
DATA INPUT
BINARY
HEX
1110
E
15
RESULT
ICC ≤ 25 µA
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
PRINCIPLES OF OPERATION
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)
voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. When the voltage at the
summing node is greater than the trip point of the threshold detector (approximately 1/2 VCC ), a bit 0 is placed
in the output register and the 4096-weight capacitor is switched to REF–. When the voltage at the summing node
is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capacitor
remains connected to REF + through the remainder of the successive-approximation process. The process is
repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are
determined. With each step of the successive-approximation process, the initial charge is redistributed among
the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
reference voltage inputs
The two reference inputs used with the device are the voltages applied to the REF+ and REF– terminals. These
voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale
reading respectively. These voltages and the analog input should not exceed the positive supply or be lower
than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower
than REF– terminal voltage.
SC
Threshold
Detector
4096
2048
Node 4096
REF –
1024
REF+
REF –
ST
16
REF+
REF –
ST
8
REF+
REF –
ST
4
REF+
REF –
ST
REF+
REF –
ST
2
1
REF+
REF+
REF –
ST
REF –
ST
To Output
Latches
1
REF –
ST
ST
VI
Figure 15. Simplified Model of the Successive-Approximation System
16
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
APPLICATION INFORMATION
4095
111111111111
VFS
See Notes A and B
4094
111111111110
VFSnom
4093
VFT = VFS – 1/2 LSB
2049
100000000001
2048
100000000000
VZT = VZS + 1/2 LSB
Step
Digital Output Code
111111111101
2047
011111111111
VZS
000000000001
1
000000000000
0
0.0012
0.0024
2.4564
2.4576
2.4588
4.9128
4.9134
2
0.0006
000000000010
4.9140
0
4.9152
VI – Analog Input Voltage – V
NOTES: A. This curve is based on the assumption that Vref+ and Vref – have been adjusted so that the voltage at the transition from digital 0
to 1 (VZT) is 0.0006 V and the transition to full scale (VFT) is 4.9134 V. 1 LSB = 1.2 mV.
B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is
the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
2543
1
2
3
4
5
Analog
Inputs
6
7
8
9
11
12
15
AIN0
CS
AIN1
I/O CLOCK
AIN2
DATA INPUT
18
17
Processor
AIN3
AIN4
DATA OUT
AIN5
EOC
16
19
AIN6
AIN7
AIN8
REF+
AIN9
AIN10
REF–
14
5-V DC Regulated
13
GND
10
To Source
Ground
Figure 17. Serial Interface
17
Control
Circuit
XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 V to
VS within 1/2 LSB can be derived as follows:
ǒ
Ǔ
The capacitance charging voltage is given by
V
C
+ VS 1–e–tcńRtCi
Where:
(1)
Rt = Rs + ri
The final voltage to 1/2 LSB is given by
VC (1/2 LSB) = VS – (VS /8192)
(2)
ǒ
Ǔ
Equating equation 1 to equation 2 and solving for time tc gives
V
and
S
*
ǒ
V
Ǔ
ń8192 + VS 1–e–tcńRtCi
S
(3)
tc (1/2 LSB) = Rt × Ci × ln(8192)
(4)
Therefore, with the values given, the time for the analog input signal to settle is
tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(8192)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Source†
2543
Rs
VS
VI
ri
VC
1 kΩ Max
Ci
60 pF Max
VI = Input Voltage at AIN
VS = External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance
Ci = Input Capacitance
VC = Capacitance Charging Voltage
† Driving source requirements:
• Noise and distortion for the source must be equivalent to the
resolution of the converter.
• Rs must be real at the input frequency.
Figure 18. Equivalent Input Circuit Including the Driving Source
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XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
SSOP
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XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
SOP
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XD2543N DIP-20 XL2543 SOP20 XL2543-SS SSOP20
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