XL74HC373

XD74HC373 DIP-20 XL74HC373 SOP-20 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State True Outputs Can D ±6-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Eight High-Current Latches in a Single Drive Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 13 ns D Package Full Parallel Access for Loading 74HC373 (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE description/ordering information These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the 74HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. 1 XD74HC373 DIP-20 XL74HC373 SOP-20 description/ordering information (continued) An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 3 2 1D 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2) 74HC373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 XD74HC373 DIP-20 XL74HC373 SOP-20 recommended operating conditions (see Note 3) 74HC373 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VI VO ∆t/∆v NOM MAX 2 5 6 3.15 V 0.5 1.35 V 1.8 Input voltage 0 Output voltage VCC VCC 0 VCC = 2 V VCC = 4.5 V Input transition rise/fall time V 4.2 VCC = 4.5 V VCC = 6 V Low-level input voltage UNIT 1.5 VCC = 6 V VCC = 2 V VIL MIN V V 1000 500 VCC = 6 V ns 400 TA Operating free-air temperature −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VI = VCC or 0, MIN MAX UNIT 1.9 1.998 1.9 IOH = −20 µA 4.4 4.499 4.4 6V 5.9 5.999 5.9 IOH = −6 mA IOH = −7.8 mA 4.5 V 3.98 4.3 3.84 6V 5.48 5.8 5.34 2V 0.002 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 4.5 V 0.17 0.26 0.33 6V 0.15 0.26 0.33 6V ±0.1 ±100 ±1000 nA 6V ±0.01 ±0.5 ±5 µA 8 80 µA 10 10 pF IOL = 6 mA IOL = 7.8 mA ICC Ci 74HC373 2V VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 TA = 25°C MIN TYP MAX 4.5 V VI = VIH or VIL II IOZ VCC IO = 0 6V 2 V to 6 V 3 3 V V XD74HC373 DIP-20 XL74HC373 SOP-20 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ TA = 25°C MIN MAX 74HC373 MIN 2V 80 100 4.5 V 16 20 6V 14 17 2V 50 63 4.5 V 10 13 6V 9 11 2V 20 24 4.5 V 10 12 6V 10 12 MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) D ten tdis tt OE OE 74HC373 VCC 2V 58 150 190 Q 4.5 V 15 30 38 6V 13 26 32 2V 73 175 220 4.5 V 18 35 44 6V 15 30 38 2V 65 150 190 4.5 V 17 30 38 6V 14 26 32 2V 50 150 190 4.5 V 15 30 38 6V 13 26 32 2V 28 60 75 4.5 V 8 12 15 6V 6 10 13 tpd LE TA = 25°C MIN TYP MAX TO (OUTPUT) Any Q Any Q Any Q Any Q 4 MIN MAX UNIT ns ns ns ns XD74HC373 DIP-20 XL74HC373 SOP-20 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER VCC 2V 82 200 250 D Q 4.5 V 22 40 50 6V 19 34 43 2V 100 225 285 4.5 V 24 45 57 6V 20 38 48 LE tt 74HC373 TO (OUTPUT) tpd ten TA = 25°C TYP MAX FROM (INPUT) OE Any Q Any Q Any Q MIN MIN MAX 2V 90 200 250 4.5 V 23 40 50 6V 19 34 43 2V 45 210 265 4.5 V 17 42 53 6V 13 36 45 UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per latch 5 TEST CONDITIONS TYP UNIT No load 100 pF XD74HC373 DIP-20 XL74HC373 SOP-20 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER tPZH S1 Test Point RL ten RL 1 kΩ tPZL tPHZ tdis S2 tPLZ tpd or tt 1 kΩ Data Input VCC 50% 10% 50% Output Control (Low-Level Enabling) VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Open Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% VCC 50% 50% 0V tPZL VOH Output Waveform 1 (See Note B) 50% 10% V OL tf tPLZ ≈VCC 50% 90% VOH Output Waveform 2 (See Note B) VOL ≈VCC 10% tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH Closed tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Open tsu 0V 50% 50 pF or 150 pF 50% 50% tw Low-Level Pulse S2 50 pF or 150 pF −− Reference Input VCC 50% S1 50 pF LOAD CIRCUIT High-Level Pulse CL VOL tPHZ 50% 90% VOH ≈0 V tr VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 XD74HC373 DIP-20 XL74HC373 SOP-20 DIP 76