XD74LS157

XD74LS157 DIP-16 XL74LS157 SOP-16 XDXL74LS157 is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected data in the true (non-inverted) form. The 74LS157 can also be used to generate any four of the 16 different functions of two variables. The 74LS157 is fabricated with the Schottky barrier diode process for high speed. • • • • • • Schottky Process for High Speed Multifunction Capability Non-Inverting Outputs Input Clamp Diodes Limit High Speed Termination Effects Special Circuitry Ensures Glitch Free Multiplexing ESD > 3500 Volts LOGIC SYMBOL                     NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.                             PIN NAMES LOADING (Note a) HIGH Common Select Input Enable (Active LOW) Input Data Inputs from Source 0 Data Inputs from Source 1 Multiplexer Outputs (Note b) S E I0a – I0d I1a – I1d Za – Zd LOW 1.0 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.5 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC DIAGRAM                             CONNECTION DIAGRAM DIP (TOP VIEW)                        1    XD74LS157 DIP-16 XL74LS157 SOP-16 FUNCTIONAL DESCRIPTION The 74S157 is a Quad 2-Input Multiplexer fabricated with the Schottky barrier diode process for high speed. It selects four bits of data from two sources under the control of a common Select Input (S). The Enable Input (E) is active LOW. When E is HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The 74S157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select Input. The logic equations for the outputs are: Za = E ⋅ (I1a ⋅ S + I0a ⋅ S) Zc = E ⋅ (I1c ⋅ S + I0c ⋅ S) Zb = E ⋅ (I1b ⋅ S + I0b ⋅ S) Zd = E ⋅ (I1d ⋅ S + I0d ⋅ S) A common use of the 74S157 is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select Input. A less obvious use is as a function generator. The 74S157 can generate any four of the 16 dif ferent functions of two variables with one variable common. This is useful for implementing highly irregular logic. TRUTH TABLE ENABLE SELECT INPUT E S I0 I1 Z H L L L L X H H L L X X X L H X L H X X L L H L H INPUTS OUTPUT H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA 2 XD74LS157 DIP-16 XL74LS157 SOP-16 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Typ Max 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Short Circuit Current (Note 1) ICC Power Supply Current V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 2.5 3.5 V 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 40 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V – 0.4 – 0.8 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 16 mA VCC = MAX 0.1 0.2 IOS V 74 I0, I1 E, S Input LOW Current I0, I1 E, S Test Conditions Guaranteed Input HIGH Voltage for All Inputs 54 Input HIGH Current I0, I1 E, S IIL Unit – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ Max Unit Test Conditions tPLH tPHL Propagation Delay Data to Output 9.0 9.0 14 14 ns Figure 2 tPLH tPHL Propagation Delay Enable to Output 13 14 20 21 ns Figure 1 tPLH tPHL Propagation Delay Select to Output 15 18 23 27 ns Figure 2 VCC = 5.0 V CL = 15 pF AC WAVEFORMS             Figure 1         Figure 2 3 XD74LS157 DIP-16 XL74LS157 SOP-16 SOP-16 -A- 16 9 P -B1         8 R X 45° G C -T-     D   M K      " !  F ! J                                                    !    !           ° ° ° °  (  (  (  (             DIP-16 -A16 9 1 8 B F L C S -TK H G     J M D       "   4                                                      !  !   !  !                   °   °   °    °