XL1307

XD1307 DIP-8 XL1307 SOP-8 FEATURES GENERAL DESCRIPTION The XDXL1307 serial rea-l time clock (RTC) is a lowpower, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are 2 transferred serially through an I C, bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12hour format with AM/PM indicator. The XDXL1307 has abuilt-in power-sense circuit that detects power failuresand automatically switches to the backup supply.Timekeeping operation continues while the partoperates from the backup supply.         Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the week, and Year with Leap-Year Compensation Valid Up to 2100 56-Byte, Battery-Backed, General-Purpose RAM with Unlimited Writes 2 I C Serial Interface Programmable Square-Wave Output Signal Automatic Power-Fail Detect and Switch Circuitry Consumes Less than 500nA in Battery-Backup Mode with Oscillator Running Optional Industrial Temperature Range: -40°C to +85°C Available in 8-Pin Plastic DIP or SO TYPICAL OPERATING CIRCUIT VCC VCC RPU RPU VCC TOP VIEW X1 X1 X2 SCL CPU PIN CONFIGURATIONS CRYSTAL VCC SQW/OUT XDXL1307 SDA VBAT Functional Diagrams Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc. 1 X1 VCC X2 VBAT SQW/OUT X2 VBAT SQW/OUT SCL GND SDA GND SDA SO (150 mils) GND RPU = tr/Cb VCC SCL PDIP (300 mils) XD1307 DIP-8 XL1307 SOP-8 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground ................................................................................ -0.5V to +7.0V Operating Temperature Range (Noncondensing) Commercial .......................................................................................................................... 0°C to +70°C Industrial ............................................................................................................................ -40°C to +85°C Storage Temperature Range......................................................................................................... -55°C to +125°C Soldering Temperature (DIP, leads) .................................................................................... +260°C for 10 seconds Soldering Temperature (surface mount)…..……………………….Refer to the JPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.0 5.5 V Supply Voltage VCC 4.5 Logic 1 Input VIH 2.2 VCC + 0.3 V Logic 0 Input VIL -0.3 +0.8 V VBAT 2.0 3 3.5 V TYP MAX UNITS VBAT Battery Voltage DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN Input Leakage (SCL) ILI -1 1 µA I/O Leakage (SDA, SQW/OUT) ILO -1 1 µA Logic 0 Output (IOL = 5mA) VOL 0.4 V ICCA 1.5 mA 200 µA 5 50 nA 1.25 x VBAT 1.284 x VBAT V TYP MAX UNITS Active Supply Current (f SCL = 100kHz) Standby Current VBAT Leakage Current Power-Fail Voltage (VBAT = 3.0V) ICCS (Note 3) IBATLKG 1.216 x VBAT VPF DC ELECTRICAL CHARACTERISTICS (VCC = 0V, VBAT = 3.0V; TA = 0°C to +70°C, TA = -40°C to +85°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN VBAT Current (OSC ON); SQW/OUT OFF IBAT1 300 500 nA VBAT Current (OSC ON); SQW/OUT ON (32kHz) IBAT2 480 800 nA VBAT Data-Retention Current (Oscillator Off) IBATDR 10 100 nA WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data. 2 XD1307 DIP-8 XL1307 SOP-8 AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = 0°C to +70°C, TA = -40°C to +85°C.) PARAMETER SYMBOL SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition f SCL 0 tBUF 4.7 µs 4.0 µs tHD:STA CONDITIONS (Note 4) MIN TYP MAX UNITS 100 kHz LOW Period of SCL Clock tLOW 4.7 µs HIGH Period of SCL Clock tHIGH 4.0 µs Setup Time for a Repeated START Condition tSU:STA 4.7 µs Data Hold Time tHD:DAT 0 µs Data Setup Time tSU:DAT 250 ns Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for STOP Condition (Notes 5, 6) tR 1000 ns tF 300 ns tSU:STO 4.7 µs CAPACITANCE (TA = +25°C) PARAMETER SYMBOL Pin Capacitance (SDA, SCL) CI/O Capacitance Load for Each Bus Line CB Note 1: Note 2: Note 3: Note 4: Note 5: CONDITIONS (Note 7) MIN TYP MAX UNITS 10 pF 400 pF Note 6: All voltages are referenced to ground. Limits at -40°C are guaranteed by design and are not production tested. ICCS specified with VCC = 5.0V and SDA, SCL = 5.0V. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW ) of the SCL signal. Note 7: CB—total capacitance of one bus line in pF. 3 XD1307 DIP-8 XL1307 SOP-8 TIMING DIAGRAM SDA tBUF tLOW tR tHD:STA tF SCL t HD:STA STOP tSU:STA tHIGH START tSU:STO SU:DAT REPEATED START tHD:DAT Figure 1. Block Diagram SQW/OUT X1 CL 1Hz/4.096kHz/8.192kHz/32.768kHz MUX/ BUFFER 1Hz X2 CL Oscillator and divider VCC GND POWER CONTROL CONTROL LOGIC VBAT XDXL1307 SCL SDA SERIAL BUS INTERFACE AND ADDRESS REGISTER RAM (56 X 8) CLOCK, CALENDAR, AND CONTROL REGISTERS USER BUFFER (7 BYTES) 4 N XD1307 DIP-8 XL1307 SOP-8 TYPICAL OPERATING CHARACTERISTICS (VCC = 5.0V, TA = +25°C, unless otherwise noted.) ICCS vs. VCC 120 IBAT vs. VBAT V BAT=3.0V V CC = 0V 400 SQW=32kHz 110 350 100 SUPPLY CURRENT (uA SUPPLY CURRENT (nA 90 300 80 70 250 60 50 SQW off 200 40 30 150 20 10 100 0 1.0 2.0 3.0 VCC (V) 4.0 IBAT vs. Temperature 2.0 5.0 V CC=0V, V BAT=3.0 VBACKUP (V) 3.0 3.5 SQW/OUT vs. Supply Voltage 32768.5 SQW=32kHz 325.0 32768.4 FREQUENCY (Hz) SUPPLY CURRENT (nA 2.5 275.0 225.0 32768.3 32768.2 32768.1 SQW off 32768 2.0 175.0 -40 -20 0 20 40 60 2.5 3.0 3.5 4.0 Supply (V) 80 TEMPERATURE (°C) 5 4.5 5.0 5.5 XD1307 DIP-8 XL1307 SOP-8 PIN DESCRIPTION PIN NAME 1 X1 2 X2 3 VBAT 4 GND FUNCTION Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, X2, is floated if an external oscillator is connected to X1. Note: For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. Backup Supply Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. Diodes in series between the battery and the VBAT pin may prevent proper operation. If a backup supply is not required, VBAT must be grounded. The nominal power-fail trip point (VPF) voltage at which access to the RTC and user RAM is denied is set by the internal circuitry as 1.25 x VBAT nominal. A lithium battery with 48mAh or greater will back up the XDXL1307 for more than 10 years in the absence of power at +25°C. Ground 2 5 SDA 6 SCL 7 SQW/OUT 8 VCC Serial Data Input/Output. SDA is the data input/output for the I C serial interface. The SDA pin is open drain and requires an external pullup resistor. The pullup voltage can be up to 5.5V regardless of the voltage on VCC. 2 Serial Clock Input. SCL is the clock input for the I C interface and is used to synchronize data movement on the serial interface. The pullup voltage can be up to 5.5V regardless of the voltage on VCC. Square Wave/Output Driver. When enabled, the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). The SQW/OUT pin is open drain and requires an external pullup resistor. SQW/OUT operates with either VCC or VBAT applied. The pullup voltage can be up to 5.5V regardless of the voltage on VCC. If not used, this pin can be left floating. Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VTP, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. DETAILED DESCRIPTION The XDXL1307 is a low-power clock/calendar with 56 bytes of battery-backed SRAM. The clock/calendar providesseconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automaticallyadjusted for months with fewer than 31 days, including corrections for leap year.The XDXL1307 operates as a slavedevice on the I2C bus. Access is obtained by implementing a START condition and providing a device identificationcode followed by a register address. Subsequent registers can be accessed sequentially until a STOP condition isexecuted. When VCC falls below 1.25 x VBAT, the device terminates an access in progress and resets the deviceaddress counter. Inputs to the device will not be recognized at this time to prevent erroneous data from beingwritten to the device from an out-of-tolerance system. When VCC falls below VBAT, the device switches into a low-current battery-backup mode. Upon power-up, the device switches from battery to VCC when VCC is greater thanVBAT +0.2V and recognizes inputs when VCC is greater than 1.25 x VBAT. The block diagram in Figure 1 shows themain elements of the serial RTC. 6 XD1307 DIP-8 XL1307 SOP-8 OSCILLATOR CIRCUIT The XDXL1307 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors orcapacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows afunctional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time isusually less than one second. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information. Table 1. Crystal Specifications* PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL MIN TYP 32.768 MAX 45 12.5 UNITS kHz kΩ pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. Figure 2. Recommended Layout for Crystal LOCAL GROUND PLANE (LAYER 2) X1 CRYSTAL X2 GND NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE. RTC AND RAM ADDRESS MAP Table 2 shows the address map for the XDXL1307 RTC and RAM registers. The RTC registers are located in addresslocations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multibyte access,when the address pointer reaches 3Fh, the end of RAM space, it wraps around to location 00h, the beginning ofthe clock space. 7 XD1307 DIP-8 XL1307 SOP-8 CLOCK AND CALENDAR The time and calendar information is obtained by reading the appropriate register bytes. Table 2 shows the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the BCD format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.) Illogical time and date entries result in undefined operation. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. On first application of power to the device the time and date registers are typically reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS). The CH bit in the seconds register will be set to a 1. The clock can be halted whenever the timekeeping functions are not required, which minimizes current (IBATDR). The XDXL1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). The hours value must bere-entered whenever the 12/24-hour mode bit is changed. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the 2 internal registers on any I C START. The time information is read from these secondary registers while the clock continues to run. This eliminates the need to re-read the registers in case the internal registers update during a read. The divider chain is reset whenever the seconds register is written. Write transfers occur on the I2C acknowledge from the XDXL1307. Once the divider chain is reset, to avoid rollover issues, the remaining time anddate registers must be written within one second. Table 2. Timekeeper Registers ADDRESS 00h 01h BIT 7 CH 0 02h 0 03h 04h 0 0 05h 0 06h 07h OUT BIT 6 BIT 5 BIT 4 10 Seconds 10 Minutes 10 12 Hour 10 Hour PM/ 24 AM 0 0 0 0 10 Date 10 0 0 Month 10 Year 0 0 SQWE BIT 3 BIT 2 BIT 1 Seconds Minutes 0 BIT 0 FUNCTION Seconds Minutes RANGE 00–59 00–59 Hours Hours 1–12 +AM/PM 00–23 DAY Date Day Date 01–07 01–31 Month 01–12 Year Control RAM 56 x 8 00–99 — Month 0 0 08h–3Fh 0 = Always reads back as 0. 8 Year RS1 RS0 00h–FFh XD1307 DIP-8 XL1307 SOP-8 CONTROL REGISTER The XDXL1307 control register is used to control the operation of the SQW/OUT pin. BIT 7 OUT BIT 6 0 BIT 5 0 BIT 4 SQWE BIT 3 0 BIT 2 0 BIT 1 RS1 BIT 0 RS0 Bit 7: Output Control (OUT). This bit controls the output level of the SQW/OUT pin when the square-wave output is disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1 and is 0 if OUT = 0. On initial application of power to the device, this bit is typically set to a 0. Bit 4: Square-Wave Enable (SQWE). This bit, when set to logic 1, enables the oscillator output. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. With the square-wave output set to 1Hz, the clock registers update on the falling edge of the square wave. On initial application of power to the device, this bit is typically set to a 0. Bits 1 and 0: Rate Select (RS[1:0]). These bits control the frequency of the square-wave output when the squarewave output has been enabled. The following table lists the square-wave frequencies that can be selected with the RS bits. On initial application of power to the device, these bits are typically set to a 1. RS1 0 0 1 1 X X RS0 0 1 0 1 X X SQW/OUT OUTPUT 1Hz 4.096kHz 8.192kHz 32.768kHz 0 1 9 SQWE 1 1 1 1 0 0 OUT X X X X 0 1 XD1307 DIP-8 XL1307 SOP-8 I2C DATA BUS 2 The XDXL1307 supports the I C protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that arecontrolled by the master are referred to as slaves. The bus must be controlled by a master device that generatesthe serial clock (SCL), controls the bus access, and generates the START and STOP conditions. 2 The XDXL1307 operates as a slave on the I C bus. 2 Figures 3, 4, and 5 detail how data is transferred on the I C bus.   Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. START data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. STOP data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the 2 I C bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The XDXL1307 operates in the standard mode (100kHz) only. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 10 XD1307 DIP-8 XL1307 SOP-8 Figure 3. Data Transfer on I2C Serial Bus SDA MSB R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 1 2 3-7 ACK 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERED STOP CONDITION OR REPEATED START CONDITION Depending upon the state of the R/W bit, two types of data transfer are possible: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first. 11 XD1307 DIP-8 XL1307 SOP-8 The XDXL1307 can operate in the following two modes: 1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit (see Figure 4). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit XDXL1307address, which is 1101000, followed by the direction bit (R/W), which for a write is 0. After receiving anddecoding the slave address byte, the XDXL1307 outputs an acknowledge on SDA. After the XDXL1307 acknowledges the slave address + write bit, the master transmits a word address to the XDXL1307. Thissets the register pointer on the XDXL1307, with the XDXL1307 acknowledging the transfer. The master canthen transmit zero or more bytes of data with the XDXL1307 acknowledging each byte received. Theregister pointer automatically increments after each data byte are written. The master will generate aSTOP condition to terminate the data write. 2. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. The XDXL1307 transmits serial data on SDA while the serial clock is input on SCL. START and STOPconditions are recognized as the beginning and end of a serial transfer (see Figure 5). The slaveaddress byte is the first byte received after the START condition is generated by the master. The slaveaddress byte contains the 7-bit XDXL1307 address, which is 1101000, followed by the direction bit (R/W),which is 1 for a read. After receiving and decoding the slave address the XDXL1307 outputs anacknowledge on SDA. The XDXL1307 then begins to transmit data starting with the register addresspointed to by the register pointer. If the register pointer is not written to before the initiation of a readmode the first address that is read is the last one stored in the register pointer. The register pointerautomatically increments after each byte are read. The XDXL1307 must receive a Not Acknowledge toend a read. Figure 4. Data Write—Slave Receiver Mode S 1101000 0 A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A XXXXXXXX A P Master to slave S - Start A - Acknowledge (ACK) P - Stop DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) Slave to master Figure 5. Data Read—Slave Transmitter Mode S 1101000 1 A XXXXXXXX S - Start A - Acknowledge (ACK) P - Stop A - Not Acknowledge (NACK) A XXXXXXXX Master to slave Slave to master A XXXXXXXX A ... XXXXXXXX A P DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL) 12 XD1307 DIP-8 XL1307 SOP-8 S 1101000 0 A XXXXXXXX XXXXXXXX A XXXXXXXX S - Start Sr - Repeated Start A - Acknowledge (ACK) P - Stop A - Not Acknowledge (NACK) A Sr 1101000 Slave to master 1 A A XXXXXXXX Master to slave Figure 6. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit A ... XXXXXXXX A P DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL) SOP8 13 XD1307 DIP-8 XL1307 SOP-8 DIP8 14