XD74LS95

XD74LS95 DIP-14 The 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register has three mode operation: • Parallel (broadside) load • Shift right (the direction QA toward QD) • Shift left (the direction QD toward QA) Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (QD to input C, etc.) and serial data is entered at input D. The clock input may be applied commonly to clock-1 and clock-2 if both modes can be clocked from the same source. Changes at the mode control inputs are low; however, conditions described in the last three lines of the function table will also ensure that register contents are protected. Pin Arrangement Serial Input 1 14 VCC 13 QA A 2 Serial Input A QA B 3 B QB 12 QB C 4 C QC 11 QC D 5 D QD 10 QD Mode Control 6 Mode CK1 9 GND 7 CK2 8 Clock1 R-Shift Clock2 L-Shift (Load) Inputs (Top view) 1 Outputs XD74LS95 DIP-14 Function Table Inputs Clocks 2(L) 1(R) H X ↓ X ↓ X L H X ↓ X ↓ L L L L L H H L H H Mode control H H H L L L ↑ ↓ ↓ ↑ ↑ Serial X X X X H L X X X X X Outputs Parallel B C X X b c QC* QD* X X X X X X X X X X X X X X X X A X a QB* X X X X X X X X D X d d X X X X X X X X QA QB QC QD QAO a QBn QAO H L QAO QAO QAO QAO QAO QBO b QCn QBO QAn QAn QBO QBO QBO QBO QBO QCO c QDn QCO QBn QBn QCO QCO QCO QCO QCO QDO d d QDO QCn QCn QDO QDO QDO QDO QDO Notes: 1. 2. 3. 4. 5. H; high level, L; low level, X; irrelevant ↑; transition from low to high level ↓; transition from high to low level a to d; the level of steady-state input at inputs A, B, C, or D, respectively. QAO to QDO; the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established. 6. QAn to QDn; the level of QA, QB, QC, or QD, respectively, before the most-recent (↑) transition of the clock. 7. *; Shifting left require external connection of QB to A, QC to B, and QD to C. Serial data is entered at input D. Block Diagram Data Inputs A B C D Mode Control Serial Input Clock1 Right -shift Clock2 Left-shift R R CK CK S QA S QB QA R CK CK S QC QB S QD QC Outputs 2 R QD XD74LS95 DIP-14 Absolute Maximum Ratings Item Symbol VCC VIN PT Tstg Supply voltage Input voltage Power dissipation Storage temperature Ratings 7 7 400 –65 to +150 Unit V V mW °C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Symbol VCC IOH IOL Topr fclock tw (CK) tsu th tenable 1 tenable 2 tinhibit 1 tinhibit 2 Supply voltage Output current Operating temperature Clock frequency Clock pulse width Setup time Hold time Enable time 1 Enable time 2 Inhibit time 1 Inhibit time 2 Min 4.75 — — –20 0 20 20 10 20 20 20 20 Typ 5.00 — — 25 — — — — — — — — Max 5.25 –400 8 75 25 — — — — — — — Unit V µA mA °C MHz ns ns ns ns ns ns ns Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V II — — — — — — — — — — 0.4 0.5 20 –0.4 0.1 µA mA mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC VIK — — 13 — 21 –1.5 mA V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Output voltage VOL Input current Short-circuit output current Supply current** Input clamp voltage IIH IIL V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with all outputs and serial input open; A, B, C, and D inputs grounded; mode control at 4.5 V; and momentary 3 V, then ground, applied both clock inputs. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL min. 25 — — typ. 36 18 21 3 max. — 27 32 Unit MHz ns ns Condition CL = 15 pF, RL = 2 kΩ XD74LS95 DIP-14 Clock Enable / Inhibit Times VIH Serial Input VIL VIH Mode Control Input 1.3V 1.3V VIL t enable 1 t inhibit 1 VIH 1.3V Clock1 Input 1.3V VIL t inhibit 2 t enable 2 VIH Clock2 Input 1.3V 1.3V VIL VOH QA Output VOL Testing Method Test Circuit VCC Output 4.5V RL Load circuit 1 QA Input Input See Testing Table Mode Control P.G. Zout = 50Ω P.G. Zout = 50Ω CK1 CK2 A Output QB Same as Load Circuit 1. Output B QC C Same as Load Circuit 1. Output D QD GND Notes: CL Serial Input 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). 4 Same as Load Circuit 1. XD74LS95 DIP-14 Testing Table Item fmax tPLH tPHL Inputs From input to output CK-1 CK-2 CK-1 → Q CK-2 → Q CK-1 → Q CK-2 → Q IN 4.5 V IN 4.5 V 4.5 V IN 4.5 V IN Mode control 0V 4.5 V 0V 4.5 V Serial Inputs IN 4.5 V IN 4.5 V Outputs A B C D QA QB QC QD 4.5 V IN 4.5 V IN 4.5 V IN 4.5 V IN 4.5 V IN 4.5 V IN 4.5 V IN 4.5 V IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Waveform tTLH Data Input tTHL 90% 10% tw (data) 3V 90% 1.3V 1.3V 1.3V 10% 0V th tsu tsu th 3V Clock1 or 2 Input 1.3V 1.3V 1.3V tw (ck) 0V VOH Outputs QA, QB, QC or QD 1.3V tPHL Note: 1.3V tPLH Input pulse; tTLH, tTHL ≤ 10 ns, Data PRR = 500 kHz, Clock PRR = 1 MHz, 5 VOL XD74LS95 DIP-14 Package Dimensions 6