MKM04EL04TD2-TN
NAND 4G(x8) / LPDDR2 4G(x32)
MKM04EL04TD2-TN
NAND Flash and Mobile Memory
162-Ball MCP Specification
4Gb(512Mb x8) NAND Flash
with 4Gb(128Mb x32) LPDDR2
Revision 1.0
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MKM04EL04TD2-TN
NAND 4G(x8) / LPDDR2 4G(x32)
4Gb(512Mb x8) NAND Flash
Featues
•
Organization
Memory cell array
Register
Page size
Block size
x8
4352 x 128K x 8
4352 x 8
4352 bytes
(256K + 16K) bytes
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
•
Mode control
Serial input/output
Command control
•
Number of valid blocks
Min 2008 blocks
Max 2048 blocks
•
Power supply
VCC = 1.8V (1.7 V ~ 1.95V)
•
Access time
Cell array to register
Serial Read Cycle
25 µs max
25 ns min (CL=30pF)
Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
3.5 ms/block typ.
Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 µA max
•
•
•
8-bits ECC for 512Btyes is required
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NAND 4G(x8) / LPDDR2 4G(x32)
4Gb(128Mb x32) LPDDR2
Feature
Double-data rate architecture; two data transfer per clock cycle
Bidirectional, data strobe (DQS, /DQS) is transmitted/received with data, to be used in capturing data
at the receiver
Eight internal banks for concurrent operation
Data mask (DM) for write data
Programmable Burst Lengths: 4 ,8 or 16
Burst type: Sequential or interleave
Programmable RL (Read latency) & WL (Write latency)
Clock Stop capability during idle period
Auto Precharge for each burst access
Configurable Drive Strength (DS)
Auto Refresh and Self Refresh Modes
Differential clock inputs (CK and /CK)
Differential data strobe (DQS and /DQS)
Commands & addresses entered on both positive & negative CK edge; data and data mask referenced
to both edges of DQS
Optional Partial Array Self Refresh (PASR) and Temperature Compensated Self Refresh (TCSR)
Deep Power Down Mode (DPD)
HSUL_12 compatible inputs (High Speed Un-terminated Logic 1.2V)
VDD2/VDDCA/VDDQ= 1.14~1.30V; VDD1=1.70~1.95
Speed:
8-Banks / 14bits rows / 10bits columns
Every Bank is organized as 16384 rows by 1024 columns by 32bits.
Revision 1.0
667MHz / 800MHz / 1066MHz
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NAND 4G(x8) / LPDDR2 4G(x32)
MCP Signal Assignments
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MCP Ball Descriptions
NAND Flash
Symbol
Type
Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7 (X8) I/O0
~ I/O15 (X16)
Input/output
The I/O pins are used to input command, address and data, and to output data during read
operations. The I/O pins float to high-z when the chip is deselected or when the outputs are
disabled.
COMMAND LATCH ENABLE
CLE
Input
The CLE input controls the activating path for commands sent to the internal command registers.
Commands are latched into the command register through the I/O ports on the rising edge of the
WE# signal with CLE high.
ADDRESS LATCH ENABLE
ALE
Input
The ALE input controls the activating path for addresses sent to the internal address registers.
Addresses are latched into the address register through the I/O ports on the rising edge of WE#
with ALE high.
CHIP ENABLE
CE#
Input
The CE# input is the device selection control. When the device is in the Busy state, CE# high is
ignored, and the device does not return to standby mode in program or erase operation.
Regarding CE# control during read operation, refer to ’Page read’ section of Device operation.
READ ENABLE
RE#
Input
The RE# input is the serial data-out control, and when it is active low, it drives the data onto the
I/O bus. Data is valid tREA after the falling edge of RE# which also increments the internal column
address counter by one.
WRITE ENABLE
WE#
Input
The WE# input controls writes to the I/O ports. Commands, address and data are latched on the
rising edge of the WE# pulse.
WRITE PROTECT
WP#
Input
The WP# pin provides inadvertent write/erase protection during power transitions. The internal
high voltage generator is reset when the WP# pin is active low.
READY/BUSY OUTPUT
The R/B# output indicates the status of the device operation. When low, it indicates that a
R/B#
Input
program, erase or random read operation is in progress and returns to high state upon
completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or when outputs are disabled.
VCC
Revision 1.0
Supply
POWER
VCC is the power supply for device.
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NAND 4G(x8) / LPDDR2 4G(x32)
VSS
Supply
N.C.
-
GROUND
NO CONNECTION
Lead is not internally connected.
LPDDR2
Symbol
Type
Function
Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA input signals are
CK, CK#
Input
sampled on both positive and negative edge of CK. CS_n and CKE inputs are sampled at the
positive edge of CK. AC timings are referenced to clock.
Clock Enable: CKE high activates, and CKE low deactivates internal clock signals, and device input
CKE
Input
buffers and output drivers. Power saving modes are entered and exited through CKE transitions.
CKE is considered part of the command code. CKE
is sampled at the positive Clock edge.
CS_n
Input
Chip Select: CS_n is considered part of the command code. CS_n is sampled at the positive Clock
edge.
Command/Address Inputs: Uni-directional command/address bus inputs. Provide the command
CA0 – CA9
Input
and address inputs according to the command truth table. CA is considered part of the command
code.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
DM0-DM3
Input
edges of DQS. Although DM pins are input-only, the DM loading matched the DQ and DQS (or
/DQS).
DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on DQ8-DQ15, DM2
corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on DQ24-DQ31.
DQ0-DQ31
Input/output
Data Bus: Bi-directional Input / Output data bus.
Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used
for read and
write data) and Differential (DQS and DQS#). It is output with read data and input with write
DQS, DQS#
DQS0-3,DQS0#-3#
data. DQS is edge-aligned to read data, and centered with write data.
Input/output
DQS0 & DQS0# corresponds to the data on DQ0-DQ7,
DQS1 & DQS1# corresponds to the data on DQ8-DQ15,
DQS2 & DQS2# corresponds to the data on DQ16-DQ23,
DQS3 & DQS3# corresponds to the data on DQ24-DQ31.
Reference Pin for Output Drive Strength Calibration. External impedance (240-ohm): this signal is
ZQ
Input
VREFDQ, VREFCA
Supply
Revision 1.0
used to calibrate the device output impedance.
Reference Voltage: VREFDQ is reference for DQ input buffers. VREFCA is reference for Command
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/ Address input buffers.
NO CONNECTION
NC
-
VDDQ
Supply
DQ Power Supply: Isolated on the die for improved noise immunity.
VSSQ
Supply
DQ Ground: Isolated on the die for improved noise immunity.
VDDCA
Supply
Command / Address Power Supply.
VSSCA
Supply
Command / Address Ground: Isolated on the die for improved noise immunity.
VDD1
Supply
Core power supply 1.
VDD2
Supply
Core power supply2.
Vss
Supply
Common Ground.
Revision 1.0
Lead is not internally connected.
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NAND 4G(x8) / LPDDR2 4G(x32)
MCP Functional Overview
Block Diagram
Revision 1.0
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NAND 4G(x8) / LPDDR2 4G(x32)
MCP Package Dimensions
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NAND 4G(x8) / LPDDR2 4G(x32)
4Gbit NAND Flash(512M x 8bit)
Descriptions
The Device is a single 1.8V 4 Gbit (4,563,402,752 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 256) bytes × 64
pages × 2048blocks.
The Device is a serial-type memory device which utilizes the I/O pins for both address
and data input/output as well as for command inputs. The Erase and Program operations
are automatically executed making the device most suitable for applications such as
solid-state file storage, voice recording, image file memory for still cameras and other
systems which require high-density non-volatile memory data storage.
The device has two 4352-bytes static registers which allow program and read data to be
transferred between the register and the memory cell array in 4352-byte increments. The
Erase operation is implemented in a single block unit (256Kbytes + 16Kbytes: 4352bytes ×
64pages).
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NAND 4G(x8) / LPDDR2 4G(x32)
Block Diagram
Functional Block Diagram
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Schematic Cell Layout and Address Assignment
A page consists of 4352bytes in which 4096 bytes are used for main memory storage and 256bytes are
for redundancy or for other uses.
1 page = 4352 bytes
1 block = 4352 bytes X 64 pages = ( 256K + 16K) bytes
Capacity = 4352 bytes X 64 pages X 2048 blocks = 570,425,344 bytes
= 4,563,402,752 bits
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
L
L
L
CA12
CA11
CA10
CA9
CA8
Third cycle
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth cycle
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
L
L
L
L
L
L
L
PA16
First cycle
Second cycle
Fifth cycle
CA0 to CA12 : Column address
PA0 to PA16 : Page address
PA0 to PA5 : NAND address in block
PA6 to PA16 : Block address
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Operation Mode: Logic and Command Tables
Logic Tables
CLE
ALE
CE#
Command Input
H
L
Data Input
L
Address Input
RE#
WP#
L
H
X
L
L
H
H
L
H
L
H
X
Serial Data Output
L
L
L
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X
X
X
X
H
X
X
H
X
X
X
X
X
L
H
H
X
Program / Erase Inhibit
X
X
X
X
X
L
Standby
X
X
H
X
X
0V / VCC
During Read (Busy)
WE#
X
Command Tables
First Cycle
Second Cycle
Serial Data Input
80
－
Read
00
30
Column Address Change in Serial Data Output
05
E0
Read with Data Cache
31
－
Read Start for Last Page in Read Cycle with Data Cache
3F
－
Auto Page Program
80
10
Column Address Change in Serial Data Input
85
－
Auto Program with Data Cache
80
15
80
11
81
15
81
10
Read for Page Copy (2) with Data Out
00
3A
Auto Program with Data Cache during Page Copy (2)
8C
15
Auto Program for last page during Page Copy (2)
8C
10
Auto Block Erase
60
D0
ID Read
90
－
Status Read
70
－
○
Status Read for Multi-Page Program or Multi Block Erase
71
－
○
Reset
FF
－
○
Multi Page Program
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Acceptable while Busy
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NAND 4G(x8) / LPDDR2 4G(x32)
Power On/Off Sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence. The
device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for
protecting against data corruption at power-on/off.
Device Operation
Read
Read mode is set when the 00h and 30h commands are issued to the Command register. Between the
two commands, a start address for the Read mode needs to be issued. After initial power on sequence,
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00h command is latched into the internal command register. Therefore read operation after power on
sequence is executed by the setting of only five address cycles and 30h command. Refer to the figures
below for the sequence and the block diagram.
A data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the address information has been latched). The device
will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready
state. Serial data can be output synchronously with the RE clock from the start address designated in the
address input cycle.
Random Column Address Change in Read Cycle
During the serial data output from the Data Cache, the column address can be changed by inputting a
new column address using the 05h and E0h commands. The data is read out in serial starting at the new
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column address. Random Column Address Change operation can be done multiple times within the same
page.
Read Operation with Read Cache
The device has a Read operation with Data Cache that enables the high speed read operation shown
below. When the block address changes, this sequence has to be started from the beginning. If the 31h
command is issued to the device, the data content of the next page is transferred to the Page Buffer during
serial data out from the Data Cache, and therefore the tR (Data transfer from memory cell to data register)
will be reduced.
1. Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time
period, the device outputs Busy state for tR max.
2. After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache
from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time period
can be detected by Ready/Busy signal.
3. Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be
read out by /RE clock simultaneously.
4. The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the
completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max.
This Busy period depends on the combination of the internal data transfer time from cell to Page buffer
and the serial data out time.
5. Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can
be read out by /RE clock simultaneously
6. The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after
the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1
max.. This Busy period depends on the combination of the internal data transfer time from cell to Page
buffer and the serial data out time.
7. Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data
from the memory cell to Page Buffer, the device can accept new command input immediately after the
completion of serial data out.
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Multi Page Read Operation
(1) Multi Page Read without Data Cache
The sequence of command and address input is shown below. Same page address (PA0 to PA5) within
each district has to be selected.
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The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the 2 Districts address information has been latched).
The device will be in the Busy state during this transfer period. After the transfer period, the device returns
to Ready state. Serial data can be output synchronously with the RE clock from the start address
designated in the address input cycle.
(2) Multi Page Read with Data Cache
When the block address changes (increments) this sequenced has to be started from the beginning.
The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each
district has to be selected.
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Internal addressing in relation with the Districts: to use Multi Page Read operation, the internal
addressing should be considered in relation with the District.
• The device consists from 2 Districts.
• Each District consists from 1024 erase blocks.
• The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
Address input restriction for the Multi Page Read operation: There are following restrictions in using
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Multi Page Read, maximum one block should be selected from each District. Same page address (PA0 to
PA5) within two districts has to be selected. For example,
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)There is no order limitation of the District for the address input. For example, following
operation is accepted,
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a 10h Program
command after the address and data have been input. The sequence of command, address and data input
is shown below.
The data is transferred (programmed) from the Data Cache via the Page Buffer to the selected page
on the rising edge of WE following input of the 10h command. After programming, the programmed data is
transferred back to the Page Buffer to be automatically verified by the device. If the programming does not
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NAND 4G(x8) / LPDDR2 4G(x32)
succeed, the Program/Verify operation is repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto
Page Program operation. Two address input cycles after the 85h command are recognized as a new column
address for the data input. After the new data is input to the new column address, the 10h command
initiates the actual data program into the selected page automatically. The Random Column Address
Change operation can be repeated multiple times within the same page.
Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared
to Auto Page Program. The sequence of command, address and data input is shown below. Although two
planes are programmed simultaneously, pass/fail is not available for each page by 70h command when the
program operation completes. Status bit of I/O 1 is set to 1 when any of the pages fails. Limitation in
addressing with Multi Page Program is shown below.
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Auto Page Program Operation with Data Cache
The device has an Auto Page Program with Data Cache operation enabling the high speed program
operation shown below. When the block address changes this sequenced has to be started from the
beginning. Issuing the 15h command to the device after serial data input initiates the program operation
with Data Cache.
1. Data for Page N is input to Data Cache.
2. Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs
Busy State (tDCBSYW2).
3. Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache.
4. By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the
programming of page N is completed. The device output busy state from the 15h command until the
Data Cache becomes empty. The duration of this period depends on timing between the internal
programming of page N and serial data input for Page N + 1 (tDCBSYW2).
5. Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed.
6. The programming with Data Cache is terminated by the 10h command. When the device becomes Ready,
it shows that the internal programming of the Page N + P is completed.
Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation
can be detected by the Status Read operation.
I/O1 : Pass/fail of the current page program operation.
I/O2 : Pass/fail of the previous page program operation.
The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.
Status on I/O1: Page Buffer Ready/Busy is Ready State. The Page Buffer Ready/Busy is output on I/O6
by Status Read operation or RY / BY pin after the 10h command.
Status on I/O2: Data Cache Read/Busy is Ready State. The Data Cache Ready/Busy is output on I/O7 by
Status Read operation or RY / BY pin after the 15h command.
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Multi Page Program with Data Cache
The device has a Multi-Page Program with Data Cache operation, which enables even higher speed
program operation compared to Auto Page Program with Data Cache as shown below. When the block
address changes (increments) this sequenced has to be started from the beginning.
The data is transferred (programmed) from the page buffer to the selected page on the rising edge of
WE# following input of the 15h or 10h command. After programming, the programmed data is transferred
back to the register to be automatically verified by the device. If the programming does not succeed, the
Program/Verify operation is repeated by the device until success is achieved or until the maximum loop
number set in the device is reached.
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Starting the above operation from 1st page of the selected erase blocks, and then repeating the
operation total 64 times with incrementing the page address in the blocks, and then input the last page
data of the blocks, 10h command executes final programming. Make sure to terminate with 81h-10hcommand sequence.
After the 15h or 10h command, the results of the above operation is shown through the 71h Status
Read command.
The 71h command Status description is as below.
Status
Revision 1.0
Output
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Fail: 1
IO0
Chip Status1 : Pass/Fail
Pass: 0
IO1
District 0 Chip Status1 : Pass/Fail
Pass: 0
Fail: 1
IO2
District 1 Chip Status1 : Pass/Fail
Pass: 0
Fail: 1
IO3
District 0 Chip Status2 : Pass/Fail
Pass: 0
Fail: 1
IO4
District 1 Chip Status2 : Pass/Fail
Pass: 0
Fail: 1
IO5
Ready/Busy
Ready:1
Busy: 0
IO6
Data Cache Ready/Busy
Ready:1
Busy: 0
IO7
Write Protect
Protect: 0
Not Protect: 1
Page Copy (2)
By using Page Copy (2), data in a page can be copied to another page after the data has been read out.
When the block address changes (increments) this sequenced has to be started from the beginning. Page
Copy (2) operation is as following.
1. Data for Page N is transferred to the Data Cache.
2. Data for Page N is read out.
3. Copy Page address M is input and if the data needs to be changed, changed data is input.
4. Data Cache for Page M is transferred to the Page Buffer.
5. After the Ready state, Data for Page N + P1 is output from the Data Cache while the data of Page M is
being programmed.
6. Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.
7. After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page
Buffer.
8. By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is
transferred to the Data cache.
9. The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the
Data Cache.
10. Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.
11. By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.
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Multi Page Copy (2)
By using Multi Page Copy (2), data in two pages can be copied to other pages after the data has been
read out. When each block address changes (increments) this sequence has to be started from the
beginning. Same page address (PA0 to PA5) within two districts has to be selected.
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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command D0h
which follows the Erase Setup command 60h. This two-cycle process for Erase operations acts as an extra
layer of protection from accidental erasure of data due to external noise. The device automatically
executes the Erase and Verify operations.
Multi Block Erase
The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below
diagram. The device automatically executes the Erase and Verify operations and the result can be
monitored by checking the status by 71h status read command.
ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and
features of the device. The ID codes can be read out under the following timing conditions:
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Code Table
Description
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 Hex Data
1st Data Maker Code
1
0
0
1
1
0
0
0
98h
2nd Data Device Code
1
0
1
0
1
1
0
0
ACh
3rd Data Chip Number, Cell Type
1
0
0
1
0
0
0
0
90h
4th Data Page Size, Block Size, I/O Width
0
0
1
0
0
1
1
0
26h
5th Data Plane Number
0
1
1
1
0
1
1
0
76h
3rd Table
Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
Internal Chip Number
Cell Type
1
2
4
8
0
0
1
1
2 level cell
0
0
4 level cell
0
1
8 level cell
1
0
16 level cell
1
1
Reserved
1
0
0
0
1
0
1
1
4th Table
Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
Page Size
(without redundant area)
Block Size
(without redundant area)
I/O Width
1KB
2KB
4KB
8KB
0
0
1
1
64KB
0
0
128KB
0
1
256KB
1
0
512KB
1
1
x8
0
x16
1
Reserved
Revision 1.0
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29
0
0
1
0
1
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NAND 4G(x8) / LPDDR2 4G(x32)
5th Table
Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
Plane Number
1Plane
0
0
2Plane
4Plane
8Plane
0
1
1
1
0
1
Reserved
0
1
1
1
1
0
Status Read
The device automatically implements the execution and verification of the Program and Erase
operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine
the result of a Program or Erase operation, and determine whether the device is in Protect mode. The
device status is output via the I/O port using RE after a 70h command input. The Status Read can also be
used during a Read operation to find out the Ready/Busy status.
Definition
Page Program
Block Erase
Cache Program
Read
Cache Read
IO0
Chip Status1
Pass: 0 Fail: 1
Pass/Fail
Pass/Fail
Invalid
IO1
Chip Status 2
Pass: 0 Fail: 1
Invalid
Pass/Fail
Invalid
IO2
Not Used
0
0
0
IO3
Not Used
0
0
0
IO4
Not Used
0
0
0
IO5
Page Buffer Ready/Busy
Ready: 1 Busy: 0
Ready/Busy
Ready/Busy
Ready/Busy
IO6
Data Cache Ready/Busy
Ready: 1 Busy: 0
Ready/Busy
Ready/Busy
Ready/Busy
IO7
Write Protect
Not Protected :1 Protected: 0
Write Protect
Write Protect
Write Protect
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Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the
internally generated voltage is discharged to 0 volt and the device enters the Wait state. Reset during a
Cache Program/Page Copy may not just stop the most recent page program but it may also stop the
previous program to a page depending on when the FF reset is input. The response to a FFh Reset
command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
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When a Reset (FFh) command is input during erasing
When a Reset (FFh) command is input during Read Operation
When a Reset (FFh) command is input during Ready
When a Status Read command (70h) is input after a Reset
When two or more Reset commands are input in succession
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Absolute Maximum Ratings
Parameter
Symbol
Rating
Vcc
-0.6 to +2.5
VIN
-0.6 to +2.5
VI/O
-0.6 to Vcc+0.3( tCK
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Notes: Burst read, RL=3, BL=8, tDQSCK < tCK
tDQSCKDL Timing
Notes:
1. tDQSCKDL=tDQSCKn – tDQSCKm
2. tDQSCKDLmax is defined as the maximum of ABS(tDQSCKn – tDQSCKm) for any {tDQSCKn - tDQSCKm} pair within any 32ms
rolling windows.
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tDQSCKDM Timing
Notes:
1. tDQSCKDM = tDQSCKn - tDQSCKm
2. tDQSCKDMmax is defined as the maximum of ABS(tDQSCKn – tDQSCKm) for any {tDQSCKn - tDQSCKm} pair within any 1.6us
rolling windows.
tDQSCKDS Timing
Notes:
1. tDQSCKDS = tDQSCKn - tDQSCKm
2. tDQSCKDSmax is defined as the maximum of ABS(tDQSCKn – tDQSCKm) for any {tDQSCKn - tDQSCKm} pair for reads within a
consecutive burst within any 160s rolling window.
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The minimum time from the burst READ command to the burst WRITE command is defined by the
read latency (RL) and the burst length (BL). Minimum READ-to-WRITE latency is RL + RU(tDQSCK(MAX)/tCK)
+ BL/2 + 1 - WL clock cycles. Note that if a READ burst is truncated with a burst TERMINATE (BST) command,
the effective burst length of the truncated READ burst should be used as BL to calculate the minimum
READ-to-WRITE delay.
Notes: Burst read followed by burst write, RL=3, WL=1, BL=4
Notes: Seamless burst read: RL=3, BL=4, tCCD=2
The minimum time from the burst READ command to the burst WRITE command is defined by the
read latency (RL) and the burst length (BL). Minimum READ-to-WRITE latency is RL + RU(tDQSCK(MAX)/tCK)
+ BL/2 + 1 - WL clock cycles. Note that if a READ burst is truncated with a burst TERMINATE (BST) command,
the effective burst length of the truncated READ burst should be used as BL to calculate the minimum
READ-to-WRITE delay. The seamless burst READ operation is supported by enabling a READ command at
every other clock cycle for BL = 4 operation, every fourth clock cycle for BL = 8 operation, and every eighth
clock cycle for BL=16 operation. This operation is supported as long as the banks are activated, whether the
accesses read the same or different banks.
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Reads interrupted by a read
For LPDDR2-S4 devices, burst read can be interrupted by another read on even clock cycles after the
Read command, provided that tCCD is met. For LPDDR2-S2 devices, burst reads may be interrupted by
other reads on any subsequent clock, provided that tCCD is met.
Notes: Read can only be interrupted by other reads or the BST command.
Burst Write
The burst WRITE command is initiated with /CS LOW, CA0 HIGH, CA1 LOW, and CA2 LOW at the rising
edge of the clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine the starting
column address for the burst. Write latency (WL) is defined from the rising edge of the clock on which the
WRITE command is issued to the rising edge of the clock from which the tDQSS delay is measured. The first
valid data must be driven WL × tCK + tDQSS from the rising edge of the clock from which the WRITE
command is issued. The data strobe signal (DQS) must be driven LOW tWPRE prior to data input. The burst
cycle data bits must be applied to the DQ pins tDS prior to the associated edge of the DQS and held valid
until tDH after that edge. Burst data is sampled on successive edges of the DQS until the 4-, 8-, or 16-bit
burst length is completed. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE
command to the same bank can be issued. Pin input timings are measured relative to the cross-point of
DQS and its complement, /DQS.
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Notes:
1. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 +
BL/2 + RU (tWTR / tCK) ].
2. tWTR starts at the rising edge of the clock after the last valid input datum.
3. If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write burst
should be used as “BL” to calculate the minimum write to read delay.
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Notes: The seamless burst write operation is supported by enabling a write command every other clock for BL=4 operation,
every four clocks for BL=8 operation, or every eight clocks for BL=16 operation. This operation is allowed regardless of same or
different banks as long as the banks are activated.
Writes interrupted by a write
For LPDDR2-S4 devices, burst write can only be interrupted by another write on even clock cycles after
the Write command, provided that tCCD(min) is met. For LPDDR2-S2 devices, burst writes may be
interrupted on any subsequent clock, provided that tCCD(min) is met.
Notes:
1. WRITEs can only be interrupted by other WRITEs or the BST command.
2. The effective burst length of the first WRITE equals two times the number of clock cycles between the first WRITE and the
interrupting WRITE.
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Burst Terminate (BST)
The BST command is initiated with /CS LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 LOW at the
rising edge of the clock. A BST command can only be issued to terminate an active READ or WRITE burst.
Therefore, a BST command can only be issued up to and including BL/2 - 1 clock cycles after a READ or
WRITE command. The effective burst length of a READ or WRITE command truncated by a BST command is
as follows:
1. Effective burst length = 2 × (number of clock cycles from the READ or WRITE command to the BST
command).
2. If a READ or WRITE burst is truncated with a BST command, to calculate the minimum READ-to-WRITE
or WRITE-to-READ delay, the effective burst length of the truncated burst should be used as the value
for BL.
3. The BST command only affects the most recent READ or WRITE command. The BST command truncates
an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock where the BST
command is issued. The BST command truncates an on-going write burst WL × tCK + tDQSS after the
rising edge of the clock where the BST command is issued.
4. For LPDDR2-S4 devices, the 4-bit prefetch architecture enables BST command assertion on even clock
cycles following a WRITE or READ command. The effective burst length of a READ or WRITE command
truncated by a BST command is thus an integer multiple of 4.
5. For LPDDR2-S2 devices, the 2-bit prefetch architecture enables BST command assertion in any cycle
after a WRITE or READ command.
Notes:
1. The BST command truncates an ongoing write burst WL * tCK + tDQSS after the rising edge of the clock where the Burst
Terminate command is issued.
2. For LPDDR2-S4 devices, BST can only be issued an even number of clock cycles after the Write command.
3. Additional BST commands are not allowed after T4, and may not be issued until after the next Read or Write command.
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Notes:
1. The BST command truncates an ongoing read burst RL * tCK + tDQSCK + tDQSQ after the rising edge of the clock where the
Burst Terminate command is issued.
2. For LPDDR2-S4 devices, BST can only be issued an even number of clock cycles after the Read command.
3. Additional BST commands are not allowed after T4, and may not be issued until after the next Read or Write command.
Write Data Mask
One write data mask (DM) pin for each data byte (DQ) will be supported on LPDDR2 devices,
consistent with the implementation on LPDDR SDRAMs. Each data mask (DM) may mask its respective data
byte (DQ) for any given cycle of the burst. Data mask has identical timings on write operations as the data
bits, though used as input only, is internally loaded identically to data bits to insure matched system timing.
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Precharge
The Precharge command is used to precharge or close a bank that has been activated. The Precharge
command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising
edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks
simultaneously. For 4-bank devices, the AB flag, and the bank address bits, BA0 and BA1, are used to
determine which bank(s) to precharge. For 8-bank devices, the AB flag, and the bank address bits, BA0,
BA1, and BA2, are used to determine which bank(s) to precharge. The bank(s) will be available for a
subsequent row access tRPab after an All-Bank Precharge command is issued and tRPpb after a Single-Bank
Precharge command is issued. In order to ensure that 8-bank devices do not exceed the instantaneous
current supplying capability of 4-bank devices, the Row Precharge time (tRP) for an All-Bank Precharge for
8-bank devices (tRPab) will be longer than the Row Precharge time for a Single-Bank Precharge (tRPpb). For
4-bank devices, the Row Precharge time (tRP) for an All-Bank Precharge (tRPab) is equal to the Row
Precharge time for a Single-Bank Precharge (tRPpb).
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AB (CA4R)
BA2(CA9R)
BA1(CA8R)
BA0(CA7R)
Precharged Bank(s)
8-bank
0
0
0
0
Bank 0 only
0
0
0
1
Bank 1 only
0
0
1
0
Bank 2 only
0
0
1
1
Bank 3 only
0
1
0
0
Bank 4 only
0
1
0
1
Bank 5 only
0
1
1
0
Bank 6 only
0
1
1
1
Bank 7 only
1
don't care
don't care
don't care
All Banks
Burst Read operation followed by Precharge
For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a
Read command. A new bank active (command) may be issued to the same bank after the Row Precharge
time (tRP). A precharge command can not be issued until after tRAS is satisfied. For LPDDR2-S4 devices, the
minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising cloak edge
that initiates the last 4-bit precharge of a Read command. For LPDDR2-S2 devices, the minimum Read to
Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the
last 2-bit prefetch of a Read command. This time is called tRTP (Read to Precharge).
For LPDDR2-S2 devices, tRTP begins BL/2 – 1 clock after the Read command. For LPDDR2-S4 devices,
tRTP begins BL/2 – 2 clock cycles after the Read command. If the burst is truncated by a BST command, the
effective “BL” ahsll be used to calculate when tRTP begins.
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Burst Write operation followed by Precharge
For write cycles, a delay must be satisfied from the time of the last valid burst input data until the
Precharge command may be issued. This delay is known as the write recovery time (tWR) referenced from
the completion of the burst write to the Precharge command. No Precharge command to the same bank
should be issued prior to the tWR delay. LPDDR2-S2 devices write data to the array in prefetch pairs
(prefetch = 2) and LPDDR2-S4 devices write data to the array in prefetch quadruples (prefetch = 4). The
beginning of an internal write operation may only begin after a prefetch group has been completely.
Therefore, the write recovery time (tWR) starts different boundaries for LPDDR2-S2 and LPDDR2-S4
devices.
For LPDDR2-S2 devices, minimum Write to Precharge command spacing to the same bank is WL +
RU(BL/2) + 1 + RU(tWR/tCK) clock cycles. For LPDDR2-S4 devices, minimum Write to Precharge command
spacing to the same bank is WL + BL/2 + 1+ RU (tWR/tCK) clock cycles. For an untruncated burst, BL is the
value from the Mode Register. For a truncated burst, BL is the effective burst length.
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Auto Precharge
Before a new row in an active bank can be opened, the active bank must be precharged using either
the Precharge command or the auto-precharge function. When a Read or a Write command is given to the
LPDDR2 SDRAM, the AP bit (CA0f) may be set to allow the active bank to automatically begin precharge at
the earliest possible moment during the burst read or write cycle. If AP is LOW when the Read or Write
command is issued, the normal Read or Write burst operation is executed and the bank remains active at
the completion of the burst. If AP is HIGH when the Read or Write command is issued, then the
auto-precharge function is engaged. This feature allows the precharge operation to be partially or
completely hidden during burst read cycles (dependent upon Read or Write latency) thus improving system
performance for random data access.
Burst Read with Auto-Precharge
If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is
engaged. LPDDR2-S2 devices start an Auto-Precharge operation on the rising edge of the clock BL/2 – 1 +
RU(tRTP/tCK) clock cycles later than the Read with AP command. LPDDR2-S4 devices start an
Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 – 2 + RU(tRTP/tCK) clock cycles later
than the Read with AP command, whichever is greater. A new bank Activate command may be issued to
the same bank if both of the following two conditions are satisfied simultaneously:
1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto-precharge begins.
2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst Write with Auto-Precharge
If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is
engaged. The LPDDR2 SDRAM starts an Auto-precharge operation on the rising edge which is tWR cycles
after the completion of the burst write. A new bank Activate command may be issued to the same bank if
both of the following two conditions are satisfied:
1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto-precharge begins.
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2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Precharge & Auto Precharge clarification
From Command
Read
BST (for Reads)
Read w/AP
Write
BST (for Writes)
To Command
Minimum Delay between "From Command" to "To Command"
Precharge (to same Bank as Read)
BL/2 + max(2, RU(tRTP/tCK)) - 2
clks
1
Precharge All
BL/2 + max(2, RU(tRTP/tCK)) - 2
clks
1
Precharge (to same Bank as Read)
1
clks
1
Precharge All
1
clks
1
Precharge (to same Bank as Read w/AP)
BL/2 + max(2, RU(tRTP/tCK)) - 2
clks
1,2
Precharge All
BL/2 + max(2, RU(tRTP/tCK)) - 2
clks
1
Activate (to same Bank as Read w/AP)
BL/2 + max(2, RU( RTP/ CK)) - 2 + RU(tRPpb/tCK)
clks
1
Write or Write w/AP (same bank)
illegal
clks
3
Write or Write w/AP (different bank)
RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1
clks
3
Read or Read w/AP (same bank)
illegal
clks
3
Read or Read w/AP (different bank)
BL/2
clks
3
Precharge (to same Bank as Write)
WL + BL/2 + RU(tWR/tCK) + 1
clks
1
Precharge All
WL + BL/2 + RU(tWR/tCK) + 1
clks
1
Precharge (to same Bank as Write)
WL + RU(tWR/tCK) + 1
clks
1
Precharge All
WL + RU(tWR/tCK) + 1
clks
1
Precharge (to same Bank as Write w/AP)
WL + BL/2 + RU(tWR/tCK) + 1
clks
1
Precharge All
WL + BL/2 + RU(tWR/tCK) + 1
clks
1
Activate (to same Bank as Write w/AP)
WL + BL/2 + RU(tWR/tCK) + 1 + RU(tRP /tCK)
clks
1
Write w/AP
Precharge
Precharge All
Unit Notes
pb
Write or Write w/AP (same bank)
illegal
clks
3
Write or Write w/AP (different bank)
BL/2
clks
3
Read or Read w/AP (same bank)
illegal
clks
3
Read or Read w/AP (different bank)
WL + BL/2 + RU(tWTR/tCK) + 1
clks
3
Precharge (to same Bank as Precharge)
1
clks
1
Precharge All
1
clks
1
Precharge
Precharge All
1
1
clks
clks
1
1
Notes:
1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or
precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command
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issued to that bank.
2. Any command issued during the minimum delay time as specified above table is illegal.
3. After read with AP, seamless read operations to different banks are supported. After write with AP, seamless write operations
to different banks are supported. Read w/AP and Write a/AP may not be interrupted or truncated.
Refresh Command
The Refresh Command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the
rising edge of clock. Per Bank Refresh is initiated by having CA3 LOW at the rising edge of the clock and All
Bank Refresh is initiated by having CA3 HIGH at the rising edge of clock. Per Bank Refresh is only allowed in
devices with 8 banks.
A Per Bank Refresh Command, REFpb performs a refresh operation to the bank which is scheduled by
the bank counter in the memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential
round-robin: “0-1-2-3-4-5-6-7-0-1-…”. The bank count is synchronized between the controller and the
SDRAM upon issuing a RESET command or at every exit from self refresh, by resetting bank count to zero.
The bank addressing for the Per Bank Refresh count is the same as established in the single-bank Precharge
command.
A bank must be idle before it can be refreshed. It is the responsibility of the controller to track the
bank being refreshed by the Per Bank Refresh command. The REFpb command may not be issued to the
memory until the following conditions are met:
1. tRFCab has been satisfied after the prior REFab command.
2. tRFCpb has been satisfied after the prior REFpb command.
3. tRP has been satisfied after the prior Precharge command to that given bank.
tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a
row in a different bank than affected by the REFpb command. The target bank is inaccessible during the Per
Bank Refresh cycle (tRFCpb), however other banks within the device are accessible and may be addressed
during the Per Bank Refresh cycle. During the REFpb operation, any of the banks other than the one being
refreshed can be maintained in active state or accessed by a read or a write command.
When the Per Bank Refresh cycle has completed, the affected bank will be in the idle state. As shown
in the table, after issuing REFpb:
1. tRFCpb must be satisfied before issuing a REFab command.
2. tRFCpb must be satisfied before issuing an ACTIVE command to a same bank.
3. tRRD must be satisfied before issuing an ACTIVE command to a different bank.
4. tRFCpb must be satisfied before issuing another REFpb command.
An all Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be
in idle state when REFab is issued (for instance, by Precharge All Bank command). REFab also synchronizes
the bank count between the controller and the SDRAM to zero. As shown in the table, the REFab command
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may not be issued to the memory until the following conditions have been met:
1. tRFCab has been satisfied after the prior REFab command.
2. tRFCpb has been satisfied after the prior REFpb command.
3. tRP has been satisfied after the prior Precharge commands.
When the All Bank Refresh cycle has completed, all banks will be in the idle state. As shown in the
table, after issuing REFab:
1. the tRFCab latency must be satisfied before issuing an ACTIVATE command.
2. the tRFCab latency must be satisfied before issuing a REFab or REFpb command.
Symbol
minimum delay from
tRFCab
REFab
tRFCab
REFpb
REFpb
tRRD
Activate
to
REFab
Activate cmd to any bank .
REFpb
REFab
Activate cmd to same bank as REFpb
REFpb
Activate cmd to different bank than REFpb
REFpb affecting an idle bank (different bank than Activate)
Activate cmd to different bank than prior Activate
Notes
1
Notes:
1. A bank must be in the idle state before it is refreshed. Therefore, after Activate, REFab is not allowed and REFpb is allowed
only if it affects a bank which is in the idle state.
Refresh Requirements
1. Minimum number of Refresh commands: LPDDR2 requires a minimum number, R, of REFRESH (REFab)
commands within any rolling refresh window (tREFW = 32 ms @ MR4[2:0] = 011 or TC ≤ 85°C). For actual
values per density, and the resulting average refresh interval (tREFI). For devices supporting per-bank
REFRESH, a REFab command can be replaced by a full cycle of eight REFpb commands.
2. Burst Refresh limitation: To limit maximum current consumption, a maximum of REFab commands may
be issued in any rolling tREFBW (tREFBW = 4 x 8 x tRFCab). This condition does not apply if REFpb
commands are used.
3. Refresh Requirements and Self-Refresh: If any time within a refresh window is spent in Self-Refresh
Mode, the number of required Refresh commands in this particular window is reduced to:
R* = R - RU{tSRF / tREFI} = R - RU{R * tSRF / tREFW}; where RU stands for the round-up function
4. Minimum number of Refresh commands: LPDDR2 requires a minimum number, R, of REFRESH (REFab)
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NAND 4G(x8) / LPDDR2 4G(x32)
Notes:
1. Time in self refresh mode is fully enclosed in the refresh window (tREF).
2. At self-refresh entry.
3. At self-refresh exit.
4. Several intervals in self refresh during one tREFW interval. In this example, tSRF = tSRF1 + tSRF2.
Notes: All bank refresh operation
Revision 1.0
82
APR 2017
MKM04EL04TD2-TN
NAND 4G(x8) / LPDDR2 4G(x32)
Notes:
1. In the beginning of this example, the REFpb bank is pointing to Bank0.
2. Operations to other banks than the bank being refreshed are allowed during the tREFpb period.
LPDDR2-S4 devices allow significant flexibility in scheduling REFRESH commands, as long as the
boundary conditions above are met. In the most straight forward case a REFRESH command should be
scheduled every tREFI. In this case Self-Refresh may be entered at any time.
The users may choose to deviate from this regular refresh pattern e.g., to enable a period where no
refreshes are required. In the extreme the user may choose to issue a refresh burst of 4096 REFRESH
commands with the maximum allowable rate (limited by tREFBW) followed by a long time without any
REFRESH commands, until the refresh window is complete, then repeating this sequence. The achieveable
time without REFRESH commands is given by tREFW - (R / 8) * tREFBW = tREFW - R * 4 * tRFCab. Tj
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