eMMC 8GB
MKEV008GCB-SS510
Specification
V1.0
Aug 13th, 2019
MKEV008GCB-SS510
Contents
1.
Foreword ......................................................................................................... 6
2.
Revision History ................................................................................................ 7
3.
Statement of Scope ........................................................................................... 8
4.
General Description ........................................................................................... 9
4.1.
Product list ............................................................................................. 9
4.2.
Feature .................................................................................................. 9
5.
eMMC Function Block Diagram .......................................................................... 11
6.
Pin Description ............................................................................................... 12
7.
8.
6.1.
eMMC 153 Ball Pin Assignment ................................................................ 12
6.2.
eMMC Pin Description ............................................................................. 13
Electrical Characteristics .................................................................................. 14
7.1.
General operating conditions ................................................................... 14
7.2.
Device Power Diagram............................................................................ 14
7.3.
Power supply voltage ............................................................................. 15
7.4.
Bus Signal Line Loading .......................................................................... 15
7.5.
Bus Signal Level .................................................................................... 16
7.6.
Bus Timing for eMMC in backward-compatible device and high speed mode ... 17
7.7.
Bus Timing for eMMC in DDR Mode........................................................... 19
7.8.
Bus Timing for eMMC in HS200 Mode........................................................ 21
7.9.
Bus Timing for eMMC in HS400 Mode........................................................ 22
eMMC Register Description ............................................................................... 25
8.1.
Operation Conditions Register (OCR) Register ............................................ 25
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MKEV008GCB-SS510
9.
8.2.
SD Card Identification Register (CID) ....................................................... 26
8.3.
Driver Stage Register (DSR) .................................................................... 26
8.4.
Relative Card Address Register (RCA) ....................................................... 26
8.5.
Card Specific Data Register (CSD) ............................................................ 26
8.6.
Extended CSD register ........................................................................... 28
Production Specifications.................................................................................. 39
9.1.
Performance ......................................................................................... 39
9.2.
Power Consumption ............................................................................... 39
9.3.
Endurance Test...................................................................................... 40
9.3.1 Bit Test………………………………………………………………………………………………………..40
9.3.2 Junior Test……………………………………………………………………………………………………40
10. Package Dimension ......................................................................................... 41
11. MKEV008GCB-SS510 Compatibility List .............................................................. 42
12. MKEV008GCB-SS510 Partition Configuration………………………………………………………………..44
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MKEV008GCB-SS510
List of Figures
FIGURE 5-1 EMMC FUNCTION BLOCK DIAGRAM ......................................................... 11
FIGURE 6-1 EMMC 153 BALL PIN ASSIGNMENT (TOP VIEW) ........................................ 12
FIGURE 7-1 DEVICE POWER DIAGRAM ..................................................................... 14
FIGURE 7-2 BUS SIGNAL LEVEL .............................................................................. 16
FIGURE 7-3 TIMING DIAGRAM DATA INPUT/OUTPUT REFERENCED TO CLOCK (EMMC IN
BACKWARD-COMPATIBLE DEVICE AND HIGH SPEED) ......................................... 17
FIGURE 7-4 TIMING DIAGRAM DATA INPUT/OUTPUT REFERENCED TO
CLOCK (DDR MODE)…………………………………………….………………………………………………………….19
FIGURE 7-5 TIMING DIAGRAM DATA INPUT REFERENCED TO CLOCK (HS200 MODE) .... 21
FIGURE 7-6 TIMING DIAGRAM DATA OUTPUT REFERENCED TO CLOCK (HS200 MODE) . 21
FIGURE 7-7 TIMING DIAGRAM DATA INPUT REFERENCED TO CLOCK (HS400 MODE) .... 22
FIGURE 7-8 TIMING DIAGRAM DATA OUTPUT REFERENCED TO CLOCK (HS400 MODE) . 23
FIGURE 10-1 PACKAGE OUTLINE DIMENSION DRAWING............................................. 41
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MKEV008GCB-SS510
List of Table
TABLE 4-1 EMMC PRODUCT LIST ............................................................................... 9
TABLE 6-1 EMMC PIN DESCRIPTION ........................................................................ 13
TABLE 7-1 GENERAL OPERATING CONDITIONS ......................................................... 14
TABLE 7-2 POWER SUPPLY VOLTAGE ........................................................................ 15
TABLE 7-3 BUS SIGNAL LINE LOADING ................................................................... 15
TABLE 7-4 BUS SIGNAL LINE LOADING FOR HS400 .................................................. 16
TABLE 7-5 BUS SIGNAL LEVEL ................................................................................ 17
TABLE 7-6 BACKWARD-COMPATIBLE DEVICE MODE TIMING FOR EMMC....................... 18
TABLE 7-7 HIGH SPEED MODE TIMING FOR EMMC .................................................... 18
TABLE 7-8 DDR MODE TIMING FOR EMMC ................................................................ 20
TABLE 7-9 HS200 MODE TIMING FOR EMMC ............................................................ 22
TABLE 7-10 HS400 MODE TIMING FOR EMMC ........................................................... 23
TABLE 8-1 EMMC REGISTER TABLE .......................................................................... 25
TABLE 8-2 OCR TABLE ........................................................................................... 25
TABLE 8-3 CID TABLE ............................................................................................ 26
TABLE 8-4 CSD TABLE ........................................................................................... 27
TABLE 8-5 EXTEND CSD TABLE ............................................................................... 28
TABLE 9-1 MKEV008GCB-SS510 PERFORMANCE ....................................................... 39
TABLE 9-2 MKEV008GCB-SS510 OPERATING CURRENT.............................................. 39
TABLE 9-3 MKEV008GCB-SS510 STANDBY/SLEEP CURRENT ....................................... 39
TABLE 9-4 MKEV008GCB-SS510 BIT TEST ............................................................... 40
TABLE 9-5 MKEV008GCB-SS510 JUNIOR TEST .......................................................... 40
TABLE 11-1 MKEV008GCB-SS510 COMPATIBILITY LIST………………………………………………….……42
TABLE 12-1 MKEV008GCB-SS510 PARTITION CONFIGURARION TABLE……………………....…..47
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MKEV008GCB-SS510
1.
Foreword
This document has been produced by MKEV008GCB-SS510, should the company modifies
the contents of this specification, it will be re-released with an identifying change of release
date and an increase in revision number as follows:
Revision mn.xy, where:
mn the first two digit are incremented for major changes of substance, e.g., functional
changes.
xy the second two digits are incremented when minor changes have been incorporated
into the specification, i.e., enhancements, corrections, updates, etc.
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MKEV008GCB-SS510
2. Revision History
Revision
Date
1.0
2019/8/13
Modified By
Ian Lin
Description
Initial release
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MKEV008GCB-SS510
3. Statement of Scope
This Datasheet document is described the eMMC MKEV008GCB-SS510 of methods and
abstractions of reliability. The contents include the concept and measurement methodologies.
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MKEV008GCB-SS510
4. General Description
MKEV008GCB-SS510 is the eMMC Technology of product, which is an embedded non-volatile
memory system package into BGA. It has high performance, low power consumption features and
supports eMMC4.5, eMMC5.01 and eMMC5.1 specifications.
4.1 Product list
Capacities
Part Number
Flash Type
Package Size (mm)
8GB
MKEV008GCB-SS510
64Gb MLCx1
11.5x13x1.0
Package
Type
153FBGA
Table 5.1 eMMC product list
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4.2
Feature
HS200 Bus Speed Mode
The HS200 mode has the following features
-
SDR Data sampling method
-
CLK frequency up to 200 MHz Data rate – up to 200 MB/s
-
4 or 8-bits bus width supported
-
Signaling levels of 1.8 V
-
Tuning concept for Read Operations
Device type values (EXT_CSD Register : DEVICE_TYPE [196])
Bit
Device Type
Supportability
7
HS400 Dual Data Rate e•MMC @ 200 MHz - 1.2V I/O
Not support
6
HS400 Dual Data Rate e•MMC @ 200 MHz - 1.8V I/O
Not support
5
HS200 Single Data Rate e•MMC @ 200 MHz - 1.2V I/O
Not support
4
HS200 Single Data Rate e•MMC @ 200 MHz - 1.8V I/O
Support
3
High-Speed Dual Data Rate e•MMC @ 52MHz - 1.2V I/O
2
High-Speed Dual Data Rate e•MMC @ 52MHz - 1.8V or 3V
I/O
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Not support
Support
MKEV008GCB-SS510
1
High-Speed e•MMC @ 52MHz - at rated device voltage(s)
Support
0
High-Speed e•MMC @ 26MHz - at rated device voltage(s)
Support
Note：It is being discussed in JEDEC and is not confirmed yet. It can be modified according to JEDEC standard in
the future.
Extended CSD revisions (EXT_CSD Register : EXT_CSD_REV [192])
Value
255–9
Timing Interface
EXT_CSD Register Value
Reserved
-
8
Revision 1.8 (for MMC v5.1)
-
7
Revision 1.7 (for MMC V5.0)
0x07h
6
Revision 1.6 (for MMC V4.5, V4.51)
-
5
Revision 1.5 (for MMC V4.41)
-
4
Revision 1.4 (Obsolete)
-
3
Revision 1.3 (for MMC V4.3)
-
2
Revision 1.2 (for MMC V4.2)
-
1
Revision 1.1 (for MMC V4.1)
-
0
Revision 1.0 (for MMC V4.0)
-
Note：Current e•MMC standard defined by JEDEC supports up to 0x07 for EXT_CSD_REV value.
High Speed timing values (EXT_CSD Register: HS_TIMING [185])
Value
Timing Interface
Supportability
0x0
Selecting backwards compatibility interface timing
Support
0x1
High Speed
Support
0x2
HS200
Support
0x3
HS400
Not Support
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MKEV008GCB-SS510
6. Pin Description
6.1
eMMC 153 Ball Pin Assignment
Figure 6-1 eMMC 153 ball pin assignment (Top view)
Ball No.
Name
Ball No.
Name
Ball No.
Name
Ball No.
Name
A3
DAT0
C2
VDDi
J5
VSS
N4
VCCQ
A4
DAT1
C4
VSSQ
J10
VCC
N5
VSSQ
A5
DAT2
C6
VCCQ
K5
RST_n
P3
VCCQ
A6
VSS
E6
VCC
K8
VSS
P4
VSSQ
B2
DAT3
E7
VSS
K9
VCC
P5
VCCQ
B3
DAT4
F5
VCC
M4
VCCQ
P6
VSSQ
B4
DAT5
G5
VSS
M5
CMD
--
--
B5
DAT6
H5
DS
M6
CLK
--
--
B6
DAT7
H10
VSS
N2
VSSQ
--
--
Note：
NC: No Connect, can be connected to ground or left floating.
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MKEV008GCB-SS510
RFU: Reserved for Future Use, should be left floating for future use.
VSF: Vendor Specific Function, shall be left floating.
6.2 eMMC Pin Description
Signal
Ball No.
CLOCK (CLK)
M6
Description
Each cycle of the clock directs a transfer on the command line
and on the data lines.
This signal is a bidirectional command channel used for device
COMMAND
(CMD)
initialization and command transfer.
M5
The CMD Signal has 2 operation modes: open drain for
initialization, and push-pull for fast command transfer.
DATA (DAT0-DAT7)
A3~A5
These are bidirectional data channels. The DAT signals operate in
B2~B6
push-pull mode.
RST_n
K5
Hardware Reset Input
DS
H5
Data Strobe: Return Clock signal used in HS400 mode
Power supply for MMC interface and Controller, have two power
VCCQ
C6,M4,N4,P3,P5
mode:
High power mode:2.7V~3.6V; Lower power mode:1.7V~1.95V
VCC
E6,F5,J10,K9
VDDi
C2
VSS,VSSQ
Power supply for NAND flash memory, its power voltage range is:
2.7V~3.6V
VDDi is internal power mode.
Connect 0.1uF or 2.2uF capacitor from VDDi to ground
A6, E7, G5, H10, J5,
J8,C4,N2,P4,P6
Ground lines
Note：All other pins are not connected [NC] and can be connected to GND or left floating.
Table 6-1 eMMC Pin Description
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MKEV008GCB-SS510
7. DC Electrical Characteristics
7.1 General operating conditions
8
Parameter
Peak voltage on all lines
Symbol
Min
Max
Unit
Remarks
--
-0.5
VCCQ+0.5
V
--
--
-100
100
uA
--
--
-2
2
uA
--
--
-100
100
uA
--
--
-2
2
uA
--
All Inputs
Input Leakage Current (before initialization
sequence and/or the internal pull up resistors
connected)
Input Leakage Current (after initialization
sequence and the internal pull up resistors
disconnected)
All Outputs
Output Leakage Current (before initialization
sequence)
Output Leakage Current (after initialization
sequence)
Note：Initialization sequence is defined in Power-Up chapter of JEDEC/MMCA Standard.
Table 7-1 General Operating Conditions
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MKEV008GCB-SS510
7.2
Operating Current (RMS)
Active Power Consumption during operation
Capacity
NAND Type
8 GB
64Gb x 1
Icc
Iccq
（Max）
（Max）
Read
50
150
mA
Write
50
100
mA
Operation
Unit
Note:
-
Power measurement conditions: Bus configuration =x8 @200MHz DDR
-
Max RMS current is the average RMS current consumption over a period of 100ms.
-
Temperature: 25℃
-
VCC=3.3V, VCCQ=1.8V
-
Not 100% tested
Figure 7-2 Operating Current
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7.3 Power supply voltage
Parameter
Supply voltage1
Symbol
Test
Conditions
VCC
--
VCCQ
--
Min
Max
Unit
2.7
3.6
V
1.7
1.95
V
2.7
3.6
V
（NAND/Core）
Supply voltage 2
（CTRL/IO）
Table 7-2 Power Supply Voltage
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MKEV008GCB-SS510
7.4
Standby Power Consumption
Standby Power Consumption in auto power saving mode and standby state
Capacity
8 GB
NAND
Type
64Gb x 1
State
Icc
Iccq
Unit
25℃
85℃
25℃
85℃
50
150
150
600
uA
50
150
150
600
uA
Standby
Note:
-
Power measurement conditions: Bus configuration =x8, No CLK
-
VCC=3.3V, VCCQ=1.8V
-
Not 100% tested
7.5
Sleep Power Consumption
Sleep Power Consumption in Sleep State
Capacity
8 GB
NAND
Type
64Gb x 1
State
Sleep
Icc
Iccq
Unit
25℃
85℃
25℃
85℃
0
0
150
600
uA
0
0
150
600
uA
Note:
-
Power measurement conditions: Bus configuration = x8, No CLK
-
Enter sleep state by CMD5, VCC power is switched off, VCCQ=1.8V
-
Not 100% tested
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MKEV008GCB-SS510
7.6
Bus Signal Line Loading
The total capacitance CL of each line of the e•MMC bus is the sum of the bus master capacitance
CHOST, the bus capacitance CBUS itself and the capacitance CDEVICE of the e•MMC connected to this
line:
CL = CHOST + CBUS + CDEVICE
The sum of the host and bus capacitances should be under 20pF.
Bus Signal Line Load
Parameter
Symb
ol
Min
Typ.
Max
Unit
Remark
Pull-up resistance for CMD
RCMD
4.7
--
100
kΩ
to prevent bus floating
Pull-up resistance for DAT0–7
RDAT
10
--
100
kΩ
to prevent bus floating
Rint
10
--
150
kΩ
Bus signal line capacitance
CL
--
--
30
pF
Single Device
Single Device capacitance
CDEVICE
--
--
12
pF
Single Device capacitance
--
--
--
16
nH
fPP ≤ 52 MHz
Internal pull up resistance
DAT1–DAT7
Maximum signal line
inductance
Table 7-6 Bus Signal Line Loading
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to prevent unconnected lines
floating
MKEV008GCB-SS510
8. eMMC Register Description
Software designers should refer to the particular implementation to do the programming. This
section introduces the registers in eMMC and the values that are used in MKEV008GCB-SS510.
The following table is the register list of current specification. The detail functionality is not
described here; please reference to latest eMMC specifications.
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8.1 Operation Conditions Register (OCR) Register
The 32-bit operation conditions register (OCR) stores the VDD voltage profile of the Device and
the access mode indication. In addition, this register includes a status information bit. This status
bit is set if the Device power up procedure has been finished. The OCR register shall be implemented
by all Devices.
OCR bit
VCCQ voltage window
e•MMC
[6:0]
Reserved
000 0000b
[7]
1.7–1.95
1b
[14:8]
2.0–2.6
000 0000b
[23:15]
2.7–3.6
1 1111 1111b
[28:24]
Reserved
000 0000b
[30:29]
Access Mode
[31]
00b (byte mode)
10b (sector mode)
Card power up status bit (busy)*
Note*：This bit is set to LOW if the e•MMC has not finished the power up routine. The supported voltage range is
coded as shown in table.
Table 8-1 OCR Table
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MKEV008GCB-SS510
8.2 SD Card Identification Register (CID)
The Device IDentification (CID) register is 128 bits wide. It contains the Device identification
information used during the Device identification phase (e•MMC protocol). Every individual flash or
I/O Device shall have a unique identification number. Every type of e•MMC Device shall have a
unique identification number. Table 75 lists these identifiers. The structure of the CID register is
defined in this section.
Name
Field
Width
CID-slice
CID Value
Manufacturer ID
MID
8
[127:120]
EAh
Reserved
-
6
[119:114]
0h
Card/BGA
CBX
2
[113:112]
01h
OEM/Application ID
OID
8
[111:104]
0Eh
Product name
PNM
48
[103:56]
Product revision
PRV
8
[55:48]
10h
Product serial number
PSN
32
[47:16]
Serial number
Manufacturing date
MDT
8
[15:8]
Manufacturing date
CRC7 checksum
CRC
7
[7:1]
CRC7
Not used, always ‘1’
-
1
[0:0]
1h
53 50 65 4D 4D 43
(SPeMMC)
Table 8-3 CID Table
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8.3 Driver Stage Register (DSR)
The 16-bit driver stage register (DSR) is optionally used to improve the bus performance for
extended operating conditions. The CSD register carries the information about the DSR register
usage. The default value of the DSR register is 0x404.
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8.4
Relative Card Address Register (RCA)
The writable 16-bit relative Device address (RCA) register carries the Device address assigned
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MKEV008GCB-SS510
by the host during the Device identification. This address is used for the addressed host-Device
communication after the Device identification procedure. The default value of the RCA register is
0x0001. The value 0x0000 is reserved to set all Devices into the Stand-by State with CMD7.
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8.5
Card Specific Data Register (CSD)
The Card-Specific Data register provides information on how to access the e•MMC contents.
The CSD defines the data format, error correction type, maximum data access time, data transfer
speed, whether the DSR register can be used etc. The programmable part of the register (entries
marked by W or E, see below) can be changed by CMD27. The type of the entries in the table below
is coded as follows:
9
R:
Read only
10
W:
One time programmable and not readable.
11
R/W:
One time programmable and readable.
12
W/E:
Multiple writable with value kept after power failure, H/W reset assertion and any
CMD0 reset and not readable.
13
R/W/E:
Multiple writable with value kept after power failure, H/W reset assertion and any
CMD0 reset and readable.
14
R/W/C_P:
Writable after value cleared by power failure and HW/ rest assertion (the value
not cleared by CMD0 reset) and readable.
15
R/W/E_P:
Multiple writable with value reset after power failure, H/W reset assertion and any
CMD0 reset and readable.
16
W/E/_P:
Multiple writable with value reset after power failure, H/W reset assertion and any
CMD0 reset and not readable.
Name
Field
Width
Cell
CSD-
Type
slice
Value
CSD structure
CSD_STRUCTURE
2
R
[127:126]
3h
System specification version
SPEC_VERS
4
R
[125:122]
4h
Reserved
-
2
R
[121:120]
0h
Data read access-time 1
TAAC
8
R
[119:112]
7Fh
NSAC
8
R
[111:104]
8h
Max. bus clock frequency
TRAN_SPEED
8
R
[103:96]
32h
Card command classes
CCC
12
R
[95:84]
5F5h
Data read access-time 2 in CLK
cycles (NSAC*100)
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MKEV008GCB-SS510
Max. read data block length
READ_BL_LEN
4
R
[83:80]
9h
Partial blocks for read allowed
READ_BL_PARTIAL
1
R
[79:79]
0h
Write block misalignment
WRITE_BLK_MISALIGN
1
R
[78:78]
0h
Read block misalignment
READ_BLK_MISALIGN
1
R
[77:77]
0h
DSR implemented
DSR_IMP
1
R
[76:76]
0h
Reserved
-
2
R
[75:74]
0h
Device size
C_SIZE
12
R
[73:62]
FFFh
Max. read current @ VDD min
VDD_R_CURR_MIN
3
R
[61:59]
6h
Max. read current @ VDD max
VDD_R_CURR_MAX
3
R
[58:56]
6h
Max. write current @ VDD min
VDD_W_CURR_MIN
3
R
[55:53]
6h
Max. write current @ VDD max
VDD_W_CURR_MAX
3
R
[52:50]
6h
Device size multiplier
C_SIZE_MULT
3
R
[49:47]
7h
Erase group size
ERASE_GRP_SIZE
5
R
[46:42]
1Fh
Erase group size multiplier
ERASE_GRP_MULT
5
R
[41:37]
1Fh
Write protect group size
WP_GRP_SIZE
5
R
[36:32]
Fh
Write protect group enable
WP_GRP_MULT
1
R
[31:31]
1h
Manufacturer default
ECC DEFAULT_ECC
2
R
[30:29]
0h
Write speed factor
R2W_FACTOR
3
R
[28:26]
5h
Max. write data block length
WRITE_BL_LEN
4
R
[25:22]
9h
Partial blocks for write allowed
WRITE_BL_PARTIAL
1
R
[21:21]
0h
Reserved
-
4
R
[20:17]
0h
Content protection application
CONTENT_PROT_APP
1
R
[16:16]
0h
File format group
FILE_FORMAT_GRP
1
R/W
[15:15]
0h
Copy flag(OTP)
COPY
1
R/W
[14:14]
0h
Permanent write protection
PERM_WRITE_PROTECT
1
R/W
[13:13]
0h
Temporary write protection
TMP_WRITE_PROTECT
1
R/W/E
[12:12]
0h
File format
FILE_FORMAT
2
R/W
[11:10]
0h
CRC
CRC
7
R/W/E
[7:1]
0h
Not used, always ‘1’
-
1
-
[0:0]
1h
Table 8-4 CSD Table
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MKEV008GCB-SS510
8.6Extended CSD register
17
The Extended CSD register defines the e•MMC properties and selected modes. It is 512 bytes
long.
18
19
The most significant 320 bytes are the Properties segment, which defines the e•MMC
capabilities and cannot be modified by the host. The lower 192 bytes are the Modes segment,
which defines the configuration the e•MMC is working in. These modes can be changed by the
host by means of the SWITCH command.
20
R:
Read only
21
W:
One time programmable and not readable.
22
R/W:
One time programmable and readable.
23
W/E:
Multiple writable with value kept after power failure, H/W reset assertion and any
CMD0 reset and not readable.
24
R/W/E:
Multiple writable with value kept after power failure, H/W reset assertion and any
CMD0 reset and readable.
25
R/W/C_P:
Writable after value cleared by power failure and HW/ rest assertion (the value
not cleared by CMD0 reset) and readable.
26
R/W/E_P:
Multiple writable with value reset after power failure, H/W reset assertion and any
CMD0 reset and readable.
27
W/E/_P:
Multiple writable with value reset after power failure, H/W reset assertion and any
CMD0 reset and not readable.
Size
Name
Field
(Byte
s)
Cell
CSD-
Type
slice
Value
Properties Segment
Reserved
[511:506
6
TBD
EXT_SECURITY_ERR
1
R
[505]
0h
Supported Command Sets
S_CMD_SET
1
R
[504]
1h
HPI features
HPI_FEATURES
1
R
[503]
1h
Extended Security Commands
Error
-
21 / 44
]
0h
MKEV008GCB-SS510
Background operations support
BKOPS_SUPPORT
1
R
[502]
1h
Max packed read commands
MAX_PACKED_READS
1
R
[501]
Ah
Max packed write commands
MAX_PACKED_WRITES
1
R
[500]
Ah
Data Tag Support
DATA_TAG_SUPPORT
1
R
[499]
1h
Tag Unit Size
TAG_UNIT_SIZE
1
R
[498]
5h
Tag Resources Size
TAG_RES_SIZE
1
R
[497]
1h
CONTEXT_CAPABILITIES
1
R
[496]
5h
LARGE_UNIT_SIZE_M1
1
R
[495]
7h
EXT_SUPPORT
1
R
[494]
3h
Supported modes
SUPPORTED_MODES
1
R
[493]
1h
FFU features
FFU_FEATURES
1
R
[492]
1h
1
R
[491]
40h
Context
management
capabilities
Large Unit size
Extended
partitions
attribute
support
OPERATION_CODE_TIME
Operation codes timeout
OUT
FFU Argument
FFU_ARG
4
R
Barrier support
BARRIER_SUPPORT
1
R
177
TBD
Reserved
-
[490:487
]
[486]
[485:309
]
0h
0h
All ”0”
CMD Queuing Support
CMDQ_SUPPORT
1
R
[308]
1h
CMD Queuing Depth
CMDQ_DEPTH
1
R
[307]
1Fh
1
TBD
[306]
0h
32
R
1
R
[269]
All “0”
1
R
[268]
0h
Cell
CSD-
Type
slice
Reserved
Vendor
proprietary
health
VENDOR_PROPRIETARY_
report
HEALTH_REPORT
Device life time estimation type
DEVICE_LIFE_TIME_EST
B
_TYP_B
Device life time estimation type
DEVICE_LIFE_TIME_EST
A
_TYP_A
Size
Name
Field
(Byte
s)
[301:270
]
0h
Value
Pre EOL information
PRE_EOL_INFO
1
R
[267]
0h
Optimal read size
OPTIMAL_READ_SIZE
1
R
[266]
0h
Optimal write size
OPTIMAL_WRITE_SIZE
1
R
[265]
0h
22 / 44
MKEV008GCB-SS510
OPTIMAL_TRIM_UNIT_SI
Optimal trim unit size
ZE
1
R
[264]
[263:262
0h
Device version
DEVICE_VERSION
2
R
Firmware version
FIRMWARE_VERSION
8
R
PWR_CL_DDR_200_360
1
R
Cache size
CACHE_SIZE
4
R
Generic CMD6 timeout
GENERIC_CMD6_TIME
1
R
[248]
0h
POWER_OFF_LONG_TIME
1
R
[247]
10h
Background operations status
BKOPS_STATUS
1
R
[246]
2h
Number
CORRECTLY_PRG_SECTO
4
R
INI_TIMEOUT_AP
1
R
[241]
0h
CACHE_FLUSH_POLICY
1
R
[240]
0h
PWR_CL_DDR_52_360
1
R
[239]
0h
PWR_CL_DDR_52_195
1
R
[238]
0h
PWR_CL_200_195
1
R
[237]
0h
PWR_CL_200_130
1
R
[236]
0h
MIN_PERF_DDR_W_8_52
1
R
[235]
0h
MIN_PERF_DDR_R_8_52
1
R
[234]
0h
2
TBD
[233]
0h
Power class for 200MHz, DDR at
VCC= 3.6V
Power
off
notification(long)
timeout
of
correctly
programmed sectors
1st
initialization
time
RS_NUM
after
partitioning
Cache Flushing Policy
Power class for 52MHz, DDR at
VCC = 3.6V
Power class for 52MHz, DDR at
VCC = 1.95V
Power class for 200MHz at VCCQ
=1.95V, VCC = 3.6V
Power class for 200MHz, at
VCCQ=1.3V, VCC = 3.6V
Minimum Write Performance for
8bit at 52MHz in DDR mode
Minimum Read Performance for
8bit at 52MHz in DDR mode
Reserved
]
[261:254
]
[253]
[252:249
]
[245:242
]
0h
0h
0h
0h
0h
TRIM Multiplier
TRIM_MULT
1
R
[232]
10h
Secure Feature support
SEC_FEATURE_SUPPORT
1
R
[231]
55h
Secure Erase Multiplier
SEC_ERASE_MULT
1
R
[230]
1Bh
23 / 44
MKEV008GCB-SS510
Secure TRIM Multiplier
SEC_TRIM_MULT
1
R
[229]
11h
Boot information
BOOT_INFO
1
R
[228]
7h
1
TBD
[227]
0h
Reserved
Boot partition size
BOOT_SIZE_MULT
1
R
[226]
20h
Access size
ACC_SIZE
1
R
[225]
6h
High-capacity erase unit size
HC_ERASE_GRP_SIZE
1
R
[224]
1h
High-capacity erase timeout
ERASE_TIMEOUT_MULT
1
R
[223]
10h
Reliable write sector count
REL_WR_SEC_C
1
R
[222]
1h
HC_WP_GRP_SIZE
1
R
[221]
10h
Sleep current [VCC]
S_C_VCC
1
R
[220]
Dh
Sleep current [VCCQ]
S_C_VCCQ
1
R
[219]
Dh
1
R
[218]
6h
1
R
[217]
17h
Cell
CSD-
Type
slice
1
R
[216]
SEC_COUNT
4
R
SECURE_WP_INFO
1
R
[211]
0h
MIN_PERF_W_8_52
1
R
[210]
0h
MIN_PERF_R_8_52
1
R
[209]
0h
1
R
[208]
0h
MIN_PERF_R_8_26_4_52
1
R
[207]
0h
MIN_PERF_W_4_26
1
R
[206]
0h
MIN_PERF_R_4_26
1
R
[205]
0h
High-capacity
write
protect
group size
Production
state
awareness
PRODUCTION_STATE_A
timeout
WARENESS_TIMEOUT
Sleep/awake timeout
S_A_TIMEOUT
Size
Name
Field
(Byte
s)
Sleep Notification Timout1
Sector Count
Secure
Write
Protect
Information
Minimum Write Performance for
8bit at 52MHz
Minimum Read Performance for
8bit at 52MHz
SLEEP_NOTIFICATION_TI
ME
Minimum Write Performance for
MIN_PERF_W_8_26_4_5
8bit at 26MHz, for 4bit at 52MHz
2
Minimum Read Performance for
8bit at 26MHz, for 4bit at 52MHz
Minimum Write Performance for
4bit at 26MHz
Minimum Read Performance for
24 / 44
[215:212
]
Value
0h
E6A340h
MKEV008GCB-SS510
4bit at 26MHz
Reserved
Power class for 26MHz at 3.6 V
1R
Power class for 52MHz at 3.6 V
1R
Power class for 26MHz at 1.95 V
1R
Power class for 52MHz at 1.95 V
1R
Partition switching timing
Out-of-interrupt busy timing
1
TBD
[204]
0h
PWR_CL_26_360
1
R
[203]
0h
PWR_CL_52_360
1
R
[202]
0h
PWR_CL_26_195
1
R
[201]
0h
PWR_CL_52_195
1
R
[200]
0h
1
R
[199]
FFh
1
R
[198]
64h
PARTITION_SWITCH_TIM
E
OUT_OF_INTERRUPT_TI
ME
I/O Driver Strength
DRIVER_STRENGTH
1
R
[197]
0h
Device type
DEVICE_TYPE
1
R
[196]
17h
1
TBD
[195]
0h
1
R
[194]
2h
1
TBD
[193]
0h
EXT_CSD_REV
1
R
[192]
7h
CMD_SET
1
R/W/E_P
[191]
0h
1
TBD
[190]
0h
R
[189]
0h
TBD
[188]
0h
R/W/E_P
[187]
0h
1
TBD
[186]
0h
1
R/W/E_P
[185]
2h
1
TBD
[184]
0h
1
W/E_P
[183]
2h
1
TBD
[182]
0h
[181]
0h
[180]
0h
[179]
0h
Reserved
CSD Structure Version
CSD_STRUCTURE
Reserved
Extended CSD Revision
Modes Segment
Command Set
Reserved
Command set revision
CMD_SET_REV
Reserved
Power class
1
POWER_CLASS
Reserved
High Speed Interface Timing
HS_TIMING
Reserved
Bus Width Mode
BUS_WIDTH
Reserved
Erased memory range
ERASE_MEM_CONT
Reserved
Partition Configuration
1
1
PARTITION_CONFIG
1
25 / 44
TBD
R/W/E &
R/W/E_P
MKEV008GCB-SS510
R/W
Boot Config protection
BOOT_CONFIG_PROT
1
&R/W/C_
[178]
0h
P
Size
Cell
CSD-
Type
slice
1
R/W/E
[177]
0h
1
TBD
[176]
0h
ERASE_GROUP_DEF
1
R/W/E
[175]
0h
BOOT_WP_STATUS
1
R
[174]
0h
[173]
0h
[172]
0h
[171]
0h
Name
Field
(Byte
s)
Boot bus Conditions
BOOT_BUS_CONDITIONS
Reserved
High-density
erase
group
definition
Boot
write
protection
status
registers
Value
R/W
Boot area write protect register
BOOT_WP
1
&R/W/C_
P
Reserved
1
TBD
R/W,R/W/
User area write protect register
USER_WP
1
C_P
&R/W/E_
P
Reserved
1
TBD
[170]
0h
FW configuration
FW_CONFIG
1
R/W
[169]
0h
RPMB Size
RPMB_SIZE_MULT
1
R
[168]
20h
Write reliability setting register
WR_REL_SET
1
R/W
[167]
1Fh
WR_REL_PARAM
1
R
[166]
14h
SANITIZE_START
1
W/E_P
[165]
0h
BKOPS_START
1
W/E_P
[164]
0h
BKOPS_EN
1
[163]
0h
H/W reset function
RST_n_FUNCTION
1
R/W
[162]
0h
HPI management
HPI_MGMT
1
R/W/E_P
[161]
0h
Partitioning Support
PARTITIONING_SUPPORT
1
R
[160]
7h
Max Enhanced Area Size
MAX_ENH_SIZE_MULT
3
R
[159:157
133h
Write
reliability
parameter
register
Start Sanitize operation
Manually
start
background
operations
Enable background operations
handshake
26 / 44
R/W &
R/W/E
MKEV008GCB-SS510
]
Partitions attribute
PARTITIONS_ATTRIBUTE
PARTITION_SETTING_CO
Partitioning Setting
MPLETED
1
R/W
[156]
0h
1
R/W
[155]
0h
12
R/W
[154:143
General Purpose Partition Size
GP_SIZE_MULT
Enhanced User Data Area Size
ENH_SIZE_MULT
3
R/W
ENH_START_ADDR
4
R/W
1
TBD
[135]
0h
1
R/W
[134]
0h
1
R/W/E
[133]
0h
TCASE_SUPPORT
1
W/E_P
[132]
0h
Periodic Wake-up
PERIODIC_WAKEUP
1
R/W/E
[131]
0h
Program CID/CSD in DDR mode
PROGRAM_CID_CSD_DD
support
R_SUPPORT
1
R
[130]
0h
2
TBD
Enhanced
User
Data
Start
Address
Reserved
Bad Block Management mode
Production state awareness
Package Case Temperature is
controlled
SEC_BAD_BLK_MGMNT
PRODUCTION_STATE_A
WARENESS
Reserved
Vendor Specific Fields
NATIVE_SECTOR_SIZE
1
Native sector size
NATIVE_SECTOR_SIZE
1
Sector size emulation
USE_NATIVE_SECTOR
Sector size
1st initialization after disabling
sector size emulation
Class 6 commands control
Number of addressed group to
be Released
]
[139:136
]
[129:128
]
0h
0h
0h
0h
R
[63]
0h
1
R/W
[62]
0h
DATA_SECTOR_SIZE
1
R
[61]
0h
INI_TIMEOUT_EMU
1
R
[60]
0h
CLASS_6_CTRL
1
R/W/E_P
[59]
0h
DYNCAP_NEEDED
1
R
[58]
0h
Cell
CSD-
Type
slice
R/W/E_P
[57:56]
Field
(Byte
s)
Exception events control
[142:140
0h
[127:64]
Size
Name
Value
0h
MKEV008GCB-SS510
RL
EXCEPTION_EVENTS_ST
Exception events status
Extended Partitions Attribute
Context configuration
turn
the
the
R/W
[53:52]
0h
15
R/W/E_P
[51:37]
0h
1
R
[36]
0h
1
R
[35]
0h
1
R/W/E_P
[34]
0h
CACHE_CTRL
1
R/W/E_P
[33]
0h
FLUSH_CACHE
1
W/E_P
[32]
0h
BARRIER_CTRL
1
R/W
[31]
0h
MODE_CONFIG
1
R/W/E_P
[30]
0h
1
W/E_P
[29]
0h
2
TBD
[28:27]
0h
1
R
[26]
0h
4
R/W/E_P
[25:22]
0h
4
R
[21:18]
39A8D0h
[17]
3h
BUTE
PACKED_FAILURE_INDEX
ON
Cache
Flushing of the cache
to
2
EXT_PARTITIONS_ATTRI
POWER_OFF_NOTIFICATI
ON/OFF
Control
0h
TUS
Power Off Notification
turn
[55:54]
PACKED_COMMAND_STA
Packed command failure index
to
R
CONTEXT_CONF
Packed command status
Control
2
ATUS
Barrier
ON/OFF
Mode config
Mode operation codes
MODE_OPERATION_COD
ES
Reserved
FFU status
FFU_STATUS
PRE_LOADING_DATA_SI
Pre loading data size
ZE
Max pre loading data size
Product
state
awareness
MAX_PRE_LOADING_DAT
A_SIZE
PRODUCT_STATE_AWAR
1
R/W/E &
enablement
ENESS_ENABLEMENT
Secure Removal Type
SECURE_REMOVAL_TYPE
1
R/W & R
[16]
1h
Command Queue Mode Enable
CMDQ_MODE_EN
1
R/W/E_P
[15]
0h
15
TBD
[14:0]
0h
Reserved
28
Note：Reserved bits should be read as “0”.
Table 8-5 Extend CSD Table
Top page
28 / 44
R
MKEV008GCB-SS510
9.
Production Specifications
9.1 Performance
Sustained
Capacity
Part Number
Mode
Sequential
Read (MB/s)
8 GB
P/N
HS200
130
SLC
Sequential
Write
(MB/s)
45
Sustained
Sequential
Write (MB/s)
22
Test Condition: Bus width x8, 200MHz SDR, 512KB data transfer, w/o file system overhead, measured on internal
board.
Table 9-1 MKEV008GCB-SS510 performance
Top page
29 / 44
MKEV008GCB-SS510
9.2
Power Consumption
Operating Current
Capacity
NAND Type
8 GB
64Gb x 1
Icc
Iccq
（Max）
（Max）
Read
50
150
mA
Write
50
100
mA
Operation
Unit
Note:
-
Power measurement conditions: Bus configuration =x8 @200MHz DDR
-
Max RMS current is the average RMS current consumption over a period of 100ms.
-
Temperature: 25℃
-
VCC=3.3V, VCCQ=1.8V
-
Not 100% tested
Standby Power Consumption
Capacity
8 GB
NAND
Type
64Gb x 1
State
Standby
Icc
Iccq
Unit
25℃
85℃
25℃
85℃
50
150
150
600
uA
50
150
150
600
uA
Note:
-
Power measurement conditions: Bus configuration =x8, No CLK
-
VCC=3.3V, VCCQ=1.8V
-
Not 100% tested
Sleep Power Consumption
Capacity
8 GB
NAND
Type
64Gb x 1
State
Sleep
Icc
Iccq
Unit
25℃
85℃
25℃
85℃
0
0
150
600
uA
0
0
150
600
uA
Note:
30 / 44
MKEV008GCB-SS510
-
Power measurement conditions: Bus configuration = x8, No CLK
-
Enter sleep state by CMD5, VCC power is switched off, VCCQ=1.8V
-
Not 100% tested
Top page
31 / 44
MKEV008GCB-SS510
10.
Package Dimension
Figure 10-2 Package Outline Dimension Drawing
Top page
32 / 44
MKEV008GCB-SS510
11. Partition Configuration
11.1 Partition Management
The memory configuration initially consists (before any partitioning operation) of the User Data Area
and RPMB Area Partitions and two Boot Area Partitions.
The embedded device also offers the host the possibility to configure additional local memory
partitions with independent address spaces, starting from logical address 0x00000000, for different
usage models.
Therefore, the memory block areas can be classified as follows:
-
Two Boot Area Partitions, whose size is multiple of 128 KB and where booting from e•MMC
can be performed.
-
One RPMB Partition accessed through a trusted mechanism, whose size is defined as
multiple of 128 KB.
-
Four General Purpose Area Partitions to store sensitive data or for other host usage
models, whose sizes are a multiple of a Write Protect Group.
Boot and RPMB Area Partitions' sizes and attributes are defined by the memory manufacturer (readonly), while General Purpose Area Partitions' sizes and attributes can be programmed by the host
only once in the device life-cycle (one-time programmable).
Moreover, the host is free to configure one segment in the User Data Area to be implemented as
enhanced storage media, and to specify its starting location and size in terms of Write Protect
Groups. The attributes of this Enhanced User Data Area can be programmed only once during the
device life-cycle (one-time programmable).
33 / 44
MKEV008GCB-SS510
A possible final configuration can be the following:
11.2 User Density
34 / 44
MKEV008GCB-SS510
Boot and RPMB Size
Capacity
Boot1 Size
Boot2 Size
RPMB Size
8 GB
4096 KB
4096 KB
4096 KB
User Density Size
Capacity
User Area Capacity
7,738,916,864 Bytes
8 GB
SEC_COUNT in Extended CSD
0xE6A340
(7.2 GB)
Maximum Enhanced Partition Size
Max.
Capacity
Enhanced
MAX_ENH_SIZE_M
HC_WP_GRP_SI
HC_ERASE_GRP_S
Partition
ULT
ZE
IZE
0x133h
0x10h
0x1h
Size
2,575,302,
8 GB
656 Bytes
(2450 MB)
Max Enhanced Area = MAX_ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512kBytes
35 / 44
MKEV008GCB-SS510
11.3 Boot Operation Mode
In boot operation mode, the master can read boot data from the slave (device) by keeping
CMD line low or sending CMD0 with argument + 0xFFFFFFFA, before issuing CMD1. The data
can be read from either boot area or user area depending on register setting.
State diagram (boot mode)
Boot operation complete Clock = 400 kHz
(Compatible with the description which ≤400kHz)
State diagram (alternative boot mode)
Top page
36 / 44
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