Mini57
ARM Cortex® -M0
32-bit Microcontroller
NuMicro® Family
Mini57 Series
Datasheet
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Apr. 06, 2017
Page 1 of 131
Rev.1.00
MINI57 SERIES DATASHEET
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Mini57
TABLE OF CONTENTS
1 GENERAL DESCRIPTION................................................................................. 7
2 FEATURES ........................................................................................................ 8
3 ABBREVIATIONS ............................................................................................ 12
4 PARTS INFORMATION LIST AND PIN CONFIGURATION............................ 13
4.1
NuMicro® Mini57 Naming Rule ................................................................................... 13
4.2
NuMicro® Mini57 Series Selection Guide ................................................................... 14
4.3
Pin Configuration ........................................................................................................ 15
4.3.1
4.3.2
4.3.3
4.4
TSSOP 28-Pin ................................................................................................................ 15
TSSOP 20-Pin ................................................................................................................ 16
QFN 33-Pin .................................................................................................................... 17
Pin Description ........................................................................................................... 19
4.4.1
4.4.2
Mini57 Series Pin Description ......................................................................................... 19
GPIO Multi-function Pin Summary .................................................................................. 31
5 BLOCK DIAGRAM ........................................................................................... 34
5.1
NuMicro® Mini57 Block Diagram ................................................................................ 34
6 FUNCTIONAL DESCRIPTION ......................................................................... 35
6.1
ARM® Cortex® -M0 Core ............................................................................................. 35
6.1.1
6.1.2
6.2
System Manager ........................................................................................................ 37
MINI57 SERIES DATASHEET
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.3
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Overview ........................................................................................................................ 87
Auto Trim ........................................................................................................................ 89
System Clock and SysTick Clock ................................................................................... 89
Peripherals Clock Source Selection ............................................................................... 90
Power-down Mode Clock ................................................................................................ 92
Frequency Divider Output ............................................................................................... 92
Flash Memory Controller (FMC) ................................................................................. 94
6.4.1
6.4.2
6.5
Overview ........................................................................................................................ 37
System Reset ................................................................................................................. 37
Power Modes and Wake-up Sources ............................................................................. 43
System Power Architecture ............................................................................................ 46
System Memory Mapping ............................................................................................... 47
Register Protection ......................................................................................................... 48
Memory Organization ..................................................................................................... 50
System Timer (SysTick) ................................................................................................. 53
Nested Vectored Interrupt Control (NVIC) ...................................................................... 58
System Control Registers ............................................................................................... 78
Clock Controller .......................................................................................................... 87
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.4
Overview ........................................................................................................................ 35
Features ......................................................................................................................... 36
Overview ........................................................................................................................ 94
Features ......................................................................................................................... 94
General Purpose I/O (GPIO) ...................................................................................... 95
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Mini57
6.5.1
6.5.2
6.5.3
6.6
Timer Controller (TIMER) ........................................................................................... 97
6.6.1
6.6.2
6.7
Overview ........................................................................................................................ 99
Features ......................................................................................................................... 99
Basic PWM Generator (BPWM) ............................................................................... 101
6.9.1
6.9.2
6.10
Overview ........................................................................................................................ 98
Features ......................................................................................................................... 98
Enhanced PWM Generator (EPWM) ......................................................................... 99
6.8.1
6.8.2
6.9
Overview ........................................................................................................................ 97
Features ......................................................................................................................... 97
Enhanced Input Capture Timer (ECAP) ..................................................................... 98
6.7.1
6.7.2
6.8
Overview ........................................................................................................................ 95
Features ......................................................................................................................... 95
GPIO Interrupt and Wake-up Function ........................................................................... 96
Overview ...................................................................................................................... 101
Features ....................................................................................................................... 101
Watchdog Timer (WDT) ........................................................................................... 102
6.10.1 Overview ...................................................................................................................... 102
6.10.2 Features ....................................................................................................................... 102
6.11
USCI – Universal Serial Control Interface Controller ............................................... 103
6.11.1 Overview ...................................................................................................................... 103
6.11.2 Features ....................................................................................................................... 103
6.12
USCI – UART Mode ................................................................................................. 104
6.12.1 Overview ...................................................................................................................... 104
6.12.2 Features ....................................................................................................................... 104
6.13
USCI – SPI Mode ..................................................................................................... 105
6.14
USCI – I2C Mode ...................................................................................................... 107
6.14.1 Overview ...................................................................................................................... 107
6.14.2 Features ....................................................................................................................... 107
6.15
Hardware Divider (HDIV).......................................................................................... 108
6.15.1 Overview ...................................................................................................................... 108
6.15.2 Features ....................................................................................................................... 108
6.16
Analog to Digital Converter (ADC) ........................................................................... 109
6.16.1 Overview ...................................................................................................................... 109
6.16.2 Features ....................................................................................................................... 109
6.17
Analog Comparator (ACMP) .................................................................................... 110
6.17.1 Overview ...................................................................................................................... 110
6.17.2 Features ....................................................................................................................... 110
6.18
Programmable Gain Amplifier (PGA) ....................................................................... 111
6.18.1 Overview ...................................................................................................................... 111
6.18.2 Features ....................................................................................................................... 111
7 APPLICATION CIRCUIT ................................................................................ 112
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6.13.1 Overview ...................................................................................................................... 105
6.13.2 Features ....................................................................................................................... 105
Mini57
8 ELECTRICAL CHARACTERISTICS .............................................................. 113
8.1
Absolute Maximum Ratings ..................................................................................... 113
8.2
DC Electrical Characteristics .................................................................................... 114
8.3
AC Electrical Characteristics .................................................................................... 119
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
Analog Characteristics ............................................................................................. 121
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.5
External Input Clock ..................................................................................................... 119
External 4~24 MHz High Speed Crystal (HXT)............................................................. 119
External 32.768 kHz XTAL Oscillator (LXT) ................................................................. 119
Typical Crystal Application Circuits............................................................................... 119
48 MHz Internal High Speed RC Oscillator (HIRC) ...................................................... 120
10 kHz Internal Low Speed RC Oscillator (LIRC) ......................................................... 120
12-bit SAR ADC............................................................................................................ 121
LDO & Power Management .......................................................................................... 122
Low Voltage Reset ....................................................................................................... 122
Brown-out Detector....................................................................................................... 123
Power-on Reset ............................................................................................................ 123
Comparator .................................................................................................................. 124
PGA .............................................................................................................................. 124
Flash DC Electrical Characteristics .......................................................................... 126
9 PACKAGE DIMENSIONS .............................................................................. 127
9.1
28-Pin TSSOP (4.4x9.7x1.0 mm)............................................................................. 127
9.2
20-Pin TSSOP (4.4x6.5x0.9 mm)............................................................................. 128
9.3
33-pin QFN33 (4x4x0.8 mm) .................................................................................... 129
10 REVISION HISTORY................................................................................. 130
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List of Figures
Figure 4.1-1 NuMicro® Mini57 Series Selection Code ................................................................... 13
Figure 4.3-1 NuMicro® Mini57 Series TSSOP 28-pin Diagram ...................................................... 15
Figure 4.3-2 NuMicro® Mini57 Series TSSOP 28-pin Multi-function Diagram ............................... 15
Figure 4.3-3 NuMicro® Mini57 Series TSSOP 20-pin Diagram ...................................................... 16
Figure 4.3-4 NuMicro® Mini57 Series TSSOP 20-pin Multi-function Diagram ............................... 16
Figure 4.3-5 NuMicro® Mini57 Series QFN 33-pin Diagram .......................................................... 17
Figure 4.3-6 NuMicro® Mini57 Series QFN 33-pin Multi-function Diagram .................................... 18
Figure 5.1-1 NuMicro® Mini57 Block Diagram ............................................................................... 34
Figure 6.1-1 Functional Block Diagram .......................................................................................... 35
Figure 6.2-1 System Reset Resources .......................................................................................... 38
Figure 6.2-2 nRESET Reset Waveform ......................................................................................... 40
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 40
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 41
Figure 6.2-5 Brown-out Detector (BOD) Waveform ....................................................................... 42
Figure 6.2-6 Power Mode State Machine ...................................................................................... 43
Figure 6.2-7 NuMicro® Mini57 Series Power Architecture Diagram .............................................. 46
Figure 6.2-8 NuMicro® Mini57 Flash, Security and Configuration Map ......................................... 50
Figure 6.2-9 SRAM Block Diagram ................................................................................................ 52
Figure 6.3-1 Clock Generator Block Diagram ................................................................................ 87
Figure 6.3-2 Clock Generator Global View Diagram...................................................................... 88
Figure 6.3-4 SysTick Clock Control Block Diagram ....................................................................... 90
Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK ................................................... 91
Figure 6.3-6 Clock Source of Frequency Divider ........................................................................... 93
Figure 6.3-7 Block Diagram of Frequency Divider ......................................................................... 93
Figure 6.5-1 I/O Pin Block Diagram ............................................................................................... 95
Figure 6.13-1 SPI Master Mode Application Block Diagram (x=0, 1) .......................................... 105
Figure 6.13-2 SPI Slave Mode Application Block Diagram (x=0, 1) ............................................ 105
Figure 6.14-1 I2C Bus Timing ....................................................................................................... 107
Figure 8.3-1 Mini57 Typical Crystal Application Circuit................................................................ 120
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Figure 6.3-3 System Clock Block Diagram .................................................................................... 89
Mini57
List of Tables
Table 3-1 List of Abbreviations....................................................................................................... 12
Table 4.2-1 NuMicro® Mini57 Series Selection Guide ................................................................... 14
Table 4.4-1 TSSOP28 Pin Description .......................................................................................... 22
Table 4.4-2 TSSOP20 Pin Description .......................................................................................... 26
Table 4.4-3 QFN33 Pin Description ............................................................................................... 30
Table 4.4-4 TSSOP20 Multi-function Pin Summary....................................................................... 33
Table 6.2-1 Reset Value of Registers ............................................................................................ 39
Table 6.2-2 Power Mode Difference Table .................................................................................... 43
Table 6.2-3 Clocks in Power Modes .............................................................................................. 44
Table 6.2-4 Condition of Entering Power-down Mode Again ......................................................... 45
Table 6.2-5 Memory Mapping Table .............................................................................................. 47
Table 6.2-6 Protected Registers .................................................................................................... 49
Table 6.2-7 Address Space Assignments for On-Chip Modules ................................................... 51
Table 6.2-8 Exception Model ......................................................................................................... 59
Table 6.2-9 System Interrupt Map Vector Table ............................................................................ 60
Table 6.2-10 Vector Table Format ................................................................................................. 60
Table 6.3-1 Peripheral Clock Source Selection Table ................................................................... 92
MINI57 SERIES DATASHEET
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Mini57
1
GENERAL DESCRIPTION
The NuMicro® Mini57 series 32-bit microcontrollers are embedded with ARM® Cortex® -M0 core for
industrial applications which need high performance, high integration, and low cost. The Cortex® M0 is the newest ARM® embedded processor with 32-bit performance at a cost equivalent to the
traditional 8-bit microcontroller.
The Mini57 series can run up to 48 MHz and operate at 2.1V ~ 5.5V, -40℃ ~ 105℃, and thus can
support a variety of industrial control applications which need high CPU performance. The Mini57
offers 29.5 Kbytes embedded program Flash, size configurable Data Flash (shared with program
Flash), 2 Kbytes Flash for the ISP, 1.5 Kbytes SPROM for security, and 4 Kbytes SRAM.
Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM, ADC,
Watchdog Timer, Analog Comparator and Brown-out Detector, have been incorporated into the
Mini57 to reduce component count, board space and system cost. These useful functions make
the Mini57 powerful for a wide range of applications.
Additionally, the Mini57 series is equipped with ISP (In-System Programming) and ICP (In-Circuit
Programming) functions, which allow the user to update program memory without removing the
chip from the actual end product.
MINI57 SERIES DATASHEET
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Mini57
2
FEATURES
Core
-
ARM® Cortex® -M0 core running up to 48 MHz
-
One 24-bit system timer
-
Supports low power Idle mode
-
A single-cycle 32-bit hardware multiplier
-
NVIC for the 32 interrupt inputs, each with 4-level of priority
-
Supports Serial Wire Debug (SWD) interface and two watchpoints/four
breakpoints
Built-in LDO for wide operating voltage ranged: 2.1V to 5.5V
Memory
-
29.5 Kbytes Flash memory for program memory (APROM)
-
Configurable Flash memory for data memory (Data Flash)
-
2 KB Flash memory for loader (LDROM)
-
Three 0.5 KB Flash memory for security protection (SPROM)
-
4 KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
-
Programmable system clock source
MINI57 SERIES DATASHEET
-
4 ~ 24 MHz external crystal input (HXT)
-
32.768 kHz external crystal input (LXT) for idle wake-up and system operation
clock
-
48 MHz internal oscillator (HIRC) (±1% accuracy at 250C, 5V)
Apr. 06, 2017
Switch clock sources on-the-fly
Dynamically calibrating the HIRC OSC to 48 MHz ±1% from -40℃ to 105℃
by external 32.768K crystal oscillator (LXT)
10 kHz internal low-power oscillator (LIRC) for Watchdog Timer and idle wakeup
I/O Port
-
Up to 22 general-purpose I/O (GPIO) pins and 1 Reset pin for QFN-33 package
-
Four I/O modes:
Quasi-bidirectional input/output
Push-Pull output
Open-Drain output
Input only with high impendence
-
Optional TTL/Schmitt trigger input
-
I/O pin can be configured as interrupt source with edge/level setting
-
Supports high driver and high sink I/O mode
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Mini57
-
Supports software selectable slew rate control
-
GPIO built-in Pull-up/Pull-low resistor for selection
Timer
-
Provides two channel 32-bit Timers; one 8-bit pre-scalar counter with 24-bit uptimer for each timer
-
Independent clock source for each timer
-
Provides One-shot, Periodic, Toggle and Continuous operation modes
-
24-bit up counter value is readable through CNT (Timer Data Register)
-
Provides trigger counting/free counting/counter reset function triggered by
external capture pin or internal comparator signal
-
Supports event counter function
-
Supports Toggle Output mode
-
Supports wake-up from Idle or Power-down mode
-
Timer0, Timer1 and Systick provided with Continuous capture function to
capture at most 4 edges continuously on one signal
Continuous Capture
-
Apr. 06, 2017
Enhanced Input Capture
-
One unit of 24-bit input capture counter
-
Capture surce:
I/O inputs: ECAP0, ECAP1 and ECAP2
PWM Trigger
ADC Trigger
WDT (Watchdog Timer)
-
Programmable clock source and time-out period
-
Supports wake-up function in Power-down mode and Idle mode
-
Interrupt or reset selectable on watchdog time-out
PWM
-
Supports a built-in 16-bit PWM clock generators, providing six PWM outputs or
three complementary paired PWM outputs
-
Shared same as clock source, clock divider, period and dead-zone generator
-
Supports group/synchronous/independent/ complementary modes
-
Supports One-shot or Auto-reload mode
-
Supports Edge-aligned and Center-aligned type
-
Supports Asymmetric mode
-
Programmable dead-zone insertion between complementary channels
-
Each output has independent polarity setting control
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MINI57 SERIES DATASHEET
Timer0, Timer1 and Systick have support Continuous capture function can
Continuous Capture 4 edge on one signal
Mini57
MINI57 SERIES DATASHEET
Apr. 06, 2017
-
Hardware fault brake and software brake protections
-
Supports rising, falling, central, period, and fault break interrupts
-
Supports duty/period trigger A/D conversion
-
Timer comparing matching event trigger PWM to do phase change
-
Supports comparator event trigger PWM to force PWM output low for current
period
-
Provides interrupt accumulation function
USCI (Universal Serial Control Interface Controller)
-
Two USCI devices
-
Supports to be configured as UART, SPI or I²C individually
-
Supports programmable baud-rate generator
ADC (Analog-to-Digital Converter)
-
12-bit ADC with 700 kSPS
-
Supports 2 sample/hold
-
Up to 8-ch single-end input from I/O and one internal input from band-gap.
-
Conversion started either by software trigger, PWM trigger, ACMP trigger or
external pin trigger
-
Supports temperature sensor for measurement chip temperature
-
Supports Simultaneous and Sequential function to continuous conversion 4
channels maximum.
Programmable Gain Amplifier (PGA)
-
Supports 8 level gain selects from 1, 2, 3, 5, 7, 9, 11 and 13
-
Unity gain frequency up to 8 MHz
Analog Comparator
-
Two analog comparators with programmable 16-level internal voltage reference
-
Built-in CRV (comparator reference voltage)
-
Supports Hysteresis function
-
Interrupt when compared results changed
Hardware Divider
-
Signed (two’s complement) integer calculation
-
32-bit dividend with 16-bit divisor calculation capacity
-
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends
to 32-bit)
-
Divided by zero warning flag
-
6 HCLK clocks taken for one cycle calculation
-
Waiting for calculation ready automatically when reading quotient and remainder
ISP (In-System Programming) and ICP (In-Circuit Programming)
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Mini57
BOD (Brown-out Detector)
-
8 programmable threshold levels: 4.3V/4.0V/3.7V/3.0V/2.7V/2.4V/2.2V/2.0V
-
Supports Brown-out interrupt and reset option
96-bit unique ID
LVR (Low Voltage Reset)
Operating Temperature: -40℃~105℃
Reliability: EFT > ± 4KV, ESD HBM pass 4KV
Packages:
-
Green package (RoHS)
-
20-pin TSSOP, 28-pin TSSOP, 33-pin QFN
MINI57 SERIES DATASHEET
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3
ABBREVIATIONS
MINI57 SERIES DATASHEET
Acronym
Description
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AHB
Advanced High-Performance Bus
APB
Advanced Peripheral Bus
BOD
Brown-out Detection
BPWM
Basic Pulse Width Modulation
DAP
Debug Access Port
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
48 MHz Internal High Speed RC Oscillator
HXT
4~24 MHz External High Speed Crystal Oscillator
ICP
In Circuit Programming
ISP
In System Programming
ISR
Interrupt Service Routine
LDO
Low Dropout Regulator
LIRC
10 kHz internal low speed RC oscillator (LIRC)
LXT
32.768 kHz External Low Speed Crystal Oscillator
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PWM
Pulse Width Modulation
SPI
Serial Peripheral Interface
SPS
Samples per Second
TMR
Timer Controller
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
WDT
Watchdog Timer
Table 3-1 List of Abbreviations
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Mini57
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® Mini57 Naming Rule
ARM–Based
32-bit Microcontroller
Mini57-X X X
CPU Core
Corte® -M0
Temperature
E: -40oC ~ +105oC
Flash ROM
57
: 29.5 KB Flash ROM
Reserved
Package Type
F: TSSOP 20
E: TSSOP 28
T: QFN 33 4x4mm
Figure 4.1-1 NuMicro® Mini57 Series Selection Code
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4.2 NuMicro® Mini57 Series Selection Guide
* USCI can be set to UART, SPI or I2C
Part
Number
ISP
APROM RAM Data Flash Loader
ROM
Connectivity
I/O
Timer
Comp. PWM
ADC
PGA
ISP
ICP
IAP
USCI*
IRC
10 kHz
Package
48 MHz
Mini57TDE 29.5 KB 4 KB Configurable 2.5 KB up to 22 2x32-bit
2
2
8
8x12-bit
v
v
v
QFN33(4x4)
Mini57EDE 29.5 KB 4 KB Configurable 2.5 KB up to 22 2x32-bit
2
2
8
8x12-bit
v
v
v
TSSOP28
Mini57FDE 29.5 KB 4 KB Configurable 2.5 KB up to 18 2x32-bit
2
2
8
8x12-bit
v
v
v
TSSOP20
Table 4.2-1 NuMicro® Mini57 Series Selection Guide
MINI57 SERIES DATASHEET
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Mini57
4.3 Pin Configuration
4.3.1
TSSOP 28-Pin
VDD
1
28
VSS
PD.6
2
27
LDO_CAP
PB.0
3
26
PC.4
PB.1
4
25
PA.0
PB.2
5
24
PA.1
PB.4
6
23
PA.2
PC.1
7
22
PA.3
nRESET
8
21
PA.4
PB.3
9
20
PA.5
PC.2
10
19
PD.5
PD.2
11
18
PC.3
PD.3
12
17
PD.1
13
16
PD.4
14
15
PC.0
NC
NC
Figure 4.3-1 NuMicro® Mini57 Series TSSOP 28-pin Diagram
1
28
VSS
2
27
LDO_CAP
PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0
3
26
PC.4/ECAP_P3
PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1
4
25
PA.0/CLKO/EPWM_CH0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2
5
24
PA.1/EPWM_CH1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PB.4/ADC1_CH0/ACMP0_N/TM1
6
23
PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PC.1/ADC0_CH4/STADC/ACMP0_P3/ACMP1_P1/SPI0_MOSI/SPI1_MISO
7
22
PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
nRESET
8
21
PA.4/XT_IN/EPWM_CH4
PB.3/ACMP1_N/PGA_I/TM0
9
20
PA.5/XT_OUT/EPWM_CH5/ACMP0_O
PC.2/ADC1_CH2/BRAKE/CCAP_P1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
10
19
PD.5/UART0_TXD
PD.2/ICE_DAT/ADC1_CH1/CCAP_P0/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
11
18
PC.3/ACMP1_O/PGA_O/SPI0_CLK/SPI1_SS
PD.3/BPWM_CH1/UART1_TXD
12
17
PD.1/ICE_CLK/ACMP1_P2/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
NC
13
16
PD.4/BPWM_CH0/UART1_RXD
NC
14
15
PC.0/ADC0_CH3/BPWM_CH0/ACMP1_P0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
Figure 4.3-2 NuMicro® Mini57 Series TSSOP 28-pin Multi-function Diagram
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MINI57 SERIES DATASHEET
VDD
PD.6/UART0_RXD
Mini57
4.3.2
TSSOP 20-Pin
VDD
1
20
VSS
PB.0
2
19
PA.0
PB.1
3
18
PA.1
PB.2
4
17
PA.2
PB.4
5
16
PA.3
PC.1
6
15
PA.4
nRESET
7
14
PA.5
PB.3
8
13
PC.3
PC.2
9
12
PD.1
PD.2
10
11
PC.0
Figure 4.3-3 NuMicro® Mini57 Series TSSOP 20-pin Diagram
VDD
1
20
VSS
PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0
2
19
PA.0/CLKO/EPWM_CH0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1
3
18
PA.1/EPWM_CH1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2
4
17
PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PB.4/ADC1_CH0/ACMP0_N/TM1
5
16
PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
PC.1/ADC0_CH4/STADC/ACMP0_P3/ACMP1_P1/SPI0_MOSI/SPI1_MISO
6
15
PA.4/XT_IN/EPWM_CH4
nRESET
7
14
PA.5/XT_OUT/EPWM_CH5/ACMP0_O
PB.3/ACMP1_N/PGA_I/TM0
8
13
PC.3/ACMP1_O/PGA_O/SPI0_CLK/SPI1_SS
PC.2/ADC1_CH2/BRAKE/CCAP_P1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
9
12
PD.1/ICE_CLK/ACMP1_P2/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
10
11
PC.0/ADC0_CH3/BPWM_CH0/ACMP1_P0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PD.2/ICE_DAT/ADC1_CH1/CCAP_P0/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
MINI57 SERIES DATASHEET
Figure 4.3-4 NuMicro® Mini57 Series TSSOP 20-pin Multi-function Diagram
Apr. 06, 2017
Page 16 of 131
Rev.1.00
Mini57
PC.4
PA.0
PA.1
PC.0
PC.3
PD.1
PD.4
QFN 33-Pin
NC
4.3.3
32 31 30 29 28 27 26 25
LDO_CAP
VSS
VDD
PD.6
PB.0
1
24
2
23
3
22
PB.1
PB.2
PB.4
6
Mini57
QFN 33-pin
4
5
21
20
19
7
18
33 VSS
8
NC
PA.4
PA.5
PD.5
NC
NC
NC
NC
PD.2
PD.3
PC.2
10 11 12 13 14 15 16
PC.1
nRESET
PB.3
9
17
PA.2
PA.3
MINI57 SERIES DATASHEET
Figure 4.3-5 NuMicro® Mini57 Series QFN 33-pin Diagram
Apr. 06, 2017
Page 17 of 131
Rev.1.00
MINI57 SERIES DATASHEET
24
2
23
PB.1/ADC0_CH1/ACMP0_P1/ECAP_P1
PB.2/ADC0_CH2/BPWM_CH1/ACMP0_P2/ECAP_P2
PB.4/ADC1_CH0/ACMP0_N/TM1
6
Apr. 06, 2017
8
NC
NC
9
PC.2/ADC1_CH2/BRAKE/CCAP_P1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
1
5
PD.2/ICE_DAT/ADC1_CH1/CCAP_P0/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PD.3/BPWM_CH1/UART1_TXD
LDO_CAP
VSS
VDD
PD.6/UART0_RXD
PB.0/ADC0_CH0/ACMP0_P0/ECAP_P0
4
PB.3/ACMP1_N/PGA_I/TM0
PC.1/ADC0_CH4/STADC/ACMP0_P3/ACMP1_P1/SPI0_MOSI/SPI1_MISO
nRESET
PC.4/ECAP_P3
PA.0/CLKO/EPWM_CH0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PA.1/EPWM_CH1/I2C1_SDA/SPI0_MISO/SPI1_MOSI/UART1_RXD
PC.0/ADC0_CH3/BPWM_CH0/ACMP1_P0/I2C1_SCL/SPI0_SS/SPI1_CLK/UART1_TXD
PC.3/ACMP1_O/PGA_O/SPI0_CLK/SPI1_SS
PD.1/ICE_CLK/ACMP1_P2/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
PD.4/BPWM_CH0/UART1_RXD
NC
Mini57
32 31 30 29 28 27 26 25
3
Mini57
QFN 33-pin
22
21
20
7
19
33 VSS
18
17
Page 18 of 131
PA.2/EPWM_CH2/I2C0_SDA/SPI0_MOSI/SPI1_MISO/UART0_RXD
PA.3/EPWM_CH3/I2C0_SCL/SPI0_CLK/SPI1_SS/UART0_TXD
NC
PA.4/XT_IN/EPWM_CH4
PA.5/XT_OUT/EPWM_CH5/ACMP0_O
PD.5/UART0_TXD
NC
NC
10 11 12 13 14 15 16
Figure 4.3-6 NuMicro® Mini57 Series QFN 33-pin Multi-function Diagram
Rev.1.00
Mini57
4.4 Pin Description
4.4.1
Mini57 Series Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFP)
PA.0 MFP0 means SYS_GPA_MFP[3:0]=0x0.
PA.4 MFP5 means SYS_GPA_MFP[19:16]=0x5.
MFP only configures the ouput data or input data of PAD; the direction of PAD is configured by PMD.
The priority of MFP in the same multi-function was GPA > GPB > GPC > GPD.
The type A of multi-function needs to be configured to be input port.
4.4.1.1
Pin No.
Mini57 Series TSSOP28 Pin Description
Pin Name
MFP*
Description
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
I/O
MFP0
General purpose digital I/O pin.
I
MFPB
Data receiver input pin for UART0.
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH0
A
MFP2
ADC0 channel0 analog input.
ACMP0_P0
A
MFP4
Analog comparator0 positive input pin.
ECAP_P0
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH1
A
MFP2
ADC0 channel1 analog input.
ACMP0_P1
A
MFP4
Analog comparator0 positive input pin.
ECAP_P1
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH2
A
MFP2
ADC0 channel2 analog input.
BPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
ACMP0_P2
A
MFP4
Analog comparator0 positive input pin.
ECAP_P2
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC1_CH0
A
MFP2
ADC1 channel0 analog input.
ACMP0_N
A
MFP4
Analog comparator0 negative input pin.
TM1
I/O
MFP7
Timer1 event counter input / toggle output
PC.1
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC0 channel4 analog input.
1
VDD
2
PD.6
UART0_RXD
3
4
5
6
7
PB.0
PB.1
PB.2
PB.4
ADC0_CH4
Apr. 06, 2017
Page 19 of 131
MINI57 SERIES DATASHEET
Type
Rev.1.00
Mini57
Pin No.
Pin Name
Type
MFP*
Description
STADC
I
MFP3
ADC external trigger input.
ACMP0_P3
A
MFP4
Analog comparator0 positive input pin.
ACMP1_P1
A
MFP5
Analog comparator1 positive input pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
I/O
MFP0
General purpose digital I/O pin.
ACMP1_N
A
MFP5
Analog comparator1 negative input pin.
PGA_I
A
MFP6
PGA input pin
TM0
I/O
MFP7
Timer0event counter input / toggle output
PC.2
I/O
MFP0
General purpose digital I/O pin.
ADC1_CH2
A
MFP2
ADC1 channel2 analog input.
BRAKE
I
MFP3
Brake input pin of EPWM.
CCAP_P1
I
MFP7
Timer Continuous Capture input pin
I2C1_SDA
I/O
MFP8
I C1 data input/output pin.
SPI0_MISO
I/O
MFP9
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MOSI
I/O
MFPA
SPI1 MOSI (Master Out, Slave In) pin.
I
MFPB
Data receiver input pin for UART1.
PD.2
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
ADC1_CH1
A
MFP2
ADC1 channel1 analog input.
CCAP_P0
I
MFP7
Timer Continuous Capture input pin
I2C0_SDA
I/O
MFP8
I C0 data input/output pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFPB
Data receiver input pin for UART0.
PD.3
I/O
MFP0
General purpose digital I/O pin.
BPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
8
nRESET
9
PB.3
10
UART1_RXD
11
MINI57 SERIES DATASHEET
UART0_RXD
12
2
2
13
NC
No Connection
14
NC
No Connection
15
PC.0
ADC0_CH3
Apr. 06, 2017
I/O
MFP0
General purpose digital I/O pin.
A
MFP2
ADC0 channel3 analog input.
Page 20 of 131
Rev.1.00
Mini57
Pin No.
16
17
18
20
21
Type
MFP*
Description
BPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
ACMP1_P0
A
MFP5
Analog comparator1 positive input pin.
I2C1_SCL
I/O
MFP8
I C1 clock pin.
SPI0_SS
I/O
MFP9
SPI0 slave select pin.
SPI1_CLK
I/O
MFPA
SPI1 serial clock pin
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
PD.4
I/O
MFP0
General purpose digital I/O pin.
BPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
UART1_RXD
I
MFPB
Data receiver input pin for UART1.
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
ACMP1_P2
A
MFP5
Analog comparator1 positive input pin.
I2C0_SCL
I/O
MFP8
I C0 clock pin.
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PC.3
I/O
MFP0
General purpose digital I/O pin.
ACMP1_O
O
MFP5
Analog comparator1 output.
PGA_O
A
MFP6
PGA output pin
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
PD.5
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PA.5
I/O
MFP0
General purpose digital I/O pin.
XT_OUT
O
MFP1
External 4~24 MHz (high speed) crystal output pin.
EPWM_CH5
I/O
MFP3
PWM channel5 output/capture input.
ACMP0_O
O
MFP4
Analog comparator0 output.
PA.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) crystal input pin.
EPWM_CH4
I/O
MFP3
PWM channel4 output/capture input.
PA.3
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH3
I/O
MFP3
PWM channel3 output/capture input.
I2C0_SCL
I/O
MFP8
I C0 clock pin.
PD.1
XT_IN
22
Apr. 06, 2017
2
2
2
Page 21 of 131
Rev.1.00
MINI57 SERIES DATASHEET
19
Pin Name
Mini57
Pin No.
Pin Name
Type
MFP*
Description
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PA.2
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH2
I/O
MFP3
PWM channel2 output/capture input.
I2C0_SDA
I/O
MFP8
I C0 data input/output pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFPB
Data receiver input pin for UART0.
PA.1
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
I2C1_SDA
I/O
MFP8
I C1 data input/output pin.
SPI0_MISO
I/O
MFP9
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MOSI
I/O
MFPA
SPI1 MOSI (Master Out, Slave In) pin.
I
MFPB
Data receiver input pin for UART1.
PA.0
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
EPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
I2C1_SCL
I/O
MFP8
I C1 clock pin.
SPI0_SS
I/O
MFP9
SPI0 slave select pin.
SPI1_CLK
I/O
MFPA
SPI1 serial clock pin
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
PC.4
I/O
MFP0
General purpose digital I/O pin.
ECAP_P3
I
MFP7
Enhanced Input Capture input pin
27
LDO_CAP
A
MFP0
LDO output pin.
28
VSS
A
MFP0
Ground pin for digital circuit.
23
UART0_RXD
24
UART1_RXD
25
MINI57 SERIES DATASHEET
26
2
2
2
Table 4.4-1 TSSOP28 Pin Description
Apr. 06, 2017
Page 22 of 131
Rev.1.00
Mini57
4.4.1.2
Pin No.
Mini57 Series TSSOP20 Pin Description
Pin Name
MFP*
Description
A
MFP0
Power supply for I/O ports and LDO source for internal
PLL and digital function.
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH0
A
MFP2
ADC0 channel0 analog input.
ACMP0_P0
A
MFP4
Analog comparator0 positive input pin.
ECAP_P0
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH1
A
MFP2
ADC0 channel1 analog input.
ACMP0_P1
A
MFP4
Analog comparator0 positive input pin.
ECAP_P1
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH2
A
MFP2
ADC0 channel2 analog input.
BPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
ACMP0_P2
A
MFP4
Analog comparator0 positive input pin.
ECAP_P2
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC1_CH0
A
MFP2
ADC1 channel0 analog input.
ACMP0_N
A
MFP4
Analog comparator0 negative input pin.
TM1
I/O
MFP7
Timer1 event counter input / toggle output
PC.1
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH4
A
MFP2
ADC0 channel4 analog input.
STADC
I
MFP3
ADC external trigger input.
ACMP0_P3
A
MFP4
Analog comparator0 positive input pin.
ACMP1_P1
A
MFP5
Analog comparator1 positive input pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFP0
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
I/O
MFP0
General purpose digital I/O pin.
ACMP1_N
A
MFP5
Analog comparator1 negative input pin.
PGA_I
A
MFP6
PGA input pin
TM0
I/O
MFP7
Timer0event counter input / toggle output
PC.2
I/O
MFP0
General purpose digital I/O pin.
1
VDD
2
PB.0
3
4
5
6
PB.1
PB.2
PB.4
7
nRESET
8
PB.3
9
Apr. 06, 2017
Page 23 of 131
Rev.1.00
MINI57 SERIES DATASHEET
Type
Mini57
Pin No.
Pin Name
Type
MFP*
Description
ADC1_CH2
A
MFP2
ADC1 channel2 analog input.
BRAKE
I
MFP3
Brake input pin of EPWM.
CCAP_P1
I
MFP7
Timer Continuous Capture input pin
I2C1_SDA
I/O
MFP8
I C1 data input/output pin.
SPI0_MISO
I/O
MFP9
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MOSI
I/O
MFPA
SPI1 MOSI (Master Out, Slave In) pin.
I
MFPB
Data receiver input pin for UART1.
PD.2
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
ADC1_CH1
A
MFP2
ADC1 channel1 analog input.
CCAP_P0
I
MFP7
Timer Continuous Capture input pin
I2C0_SDA
I/O
MFP8
I C0 data input/output pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFPB
Data receiver input pin for UART0.
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH3
A
MFP2
ADC0 channel3 analog input.
BPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
ACMP1_P0
A
MFP5
Analog comparator1 positive input pin.
I2C1_SCL
I/O
MFP8
I C1 clock pin.
SPI0_SS
I/O
MFP9
SPI0 slave select pin.
SPI1_CLK
I/O
MFPA
SPI1 serial clock pin
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
PD.1
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
ACMP1_P2
A
MFP5
Analog comparator1 positive input pin.
I2C0_SCL
I/O
MFP8
I C0 clock pin.
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PC.3
I/O
MFP0
General purpose digital I/O pin.
ACMP1_O
O
MFP5
Analog comparator1 output.
PGA_O
A
MFP6
PGA output pin
UART1_RXD
10
UART0_RXD
11
MINI57 SERIES DATASHEET
12
13
PC.0
Apr. 06, 2017
2
2
2
2
Page 24 of 131
Rev.1.00
Mini57
Pin No.
14
15
Pin Name
Type
MFP*
Description
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
PA.5
I/O
MFP0
General purpose digital I/O pin.
XT_OUT
O
MFP1
External 4~24 MHz (high speed) crystal output pin.
EPWM_CH5
I/O
MFP3
PWM channel5 output/capture input.
ACMP0_O
O
MFP4
Analog comparator0 output.
PA.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP1
External 4~24 MHz (high speed) crystal input pin.
EPWM_CH4
I/O
MFP3
PWM channel4 output/capture input.
PA.3
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH3
I/O
MFP3
PWM channel3 output/capture input.
I2C0_SCL
I/O
MFP8
I C0 clock pin.
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PA.2
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH2
I/O
MFP3
PWM channel2 output/capture input.
I2C0_SDA
I/O
MFP8
I C0 data input/output pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFPB
Data receiver input pin for UART0.
PA.1
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
I2C1_SDA
I/O
MFP8
I C1 data input/output pin.
SPI0_MISO
I/O
MFP9
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MOSI
I/O
MFPA
SPI1 MOSI (Master Out, Slave In) pin.
I
MFPB
Data receiver input pin for UART1.
PA.0
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
EPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
I2C1_SCL
I/O
MFP8
I C1 clock pin.
SPI0_SS
I/O
MFP9
SPI0 slave select pin.
SPI1_CLK
I/O
MFPA
SPI1 serial clock pin
XT_IN
16
17
18
UART1_RXD
19
Apr. 06, 2017
2
MINI57 SERIES DATASHEET
UART0_RXD
2
2
2
Page 25 of 131
Rev.1.00
Mini57
Pin No.
20
Pin Name
Type
MFP*
Description
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
VSS
A
MFP0
Ground pin for digital circuit.
Table 4.4-2 TSSOP20 Pin Description
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 26 of 131
Rev.1.00
Mini57
4.4.1.3
Mini57 Series QFN33 Pin Description
QFN33 Pin
Pin Name
No.
1
Type
MFP*
Description
LDO_CAP
A
MFP0
LDO output pin.
VSS
A
MFP0
Ground pin for digital circuit.
VDD
A
MFP0
Power supply for I/O ports and LDO source for internal PLL and digital
function.
I/O
MFP0
General purpose digital I/O pin.
I
MFPB
Data receiver input pin for UART0.
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH0
A
MFP2
ADC0 channel0 analog input.
ACMP0_P0
A
MFP4
Analog comparator0 positive input pin.
ECAP_P0
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH1
A
MFP2
ADC0 channel1 analog input.
ACMP0_P1
A
MFP4
Analog comparator0 positive input pin.
ECAP_P1
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH2
A
MFP2
ADC0 channel2 analog input.
BPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
ACMP0_P2
A
MFP4
Analog comparator0 positive input pin.
ECAP_P2
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC1_CH0
A
MFP2
ADC1 channel0 analog input.
ACMP0_N
A
MFP4
Analog comparator0 negative input pin.
TM1
I/O
MFP7
Timer1 event counter input / toggle output
PC.1
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH4
A
MFP2
ADC0 channel4 analog input.
STADC
I
MFP3
ADC external trigger input.
ACMP0_P3
A
MFP4
Analog comparator0 positive input pin.
ACMP1_P1
A
MFP5
Analog comparator1 positive input pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFP0
External reset input: active LOW, with an internal pull-up. Set this pin low
reset to initial state.
2
33
3
PD.6
4
UART0_RXD
PB.0
5
PB.1
6
PB.2
7
MINI57 SERIES DATASHEET
PB.4
8
9
10
nRESET
Apr. 06, 2017
Page 27 of 131
Rev.1.00
Mini57
PB.3
I/O
MFP0
General purpose digital I/O pin.
ACMP1_N
A
MFP5
Analog comparator1 negative input pin.
PGA_I
A
MFP6
PGA input pin
TM0
I/O
MFP7
Timer0event counter input / toggle output
PC.2
I/O
MFP0
General purpose digital I/O pin.
ADC1_CH2
A
MFP2
ADC1 channel2 analog input.
BRAKE
I
MFP3
Brake input pin of EPWM.
CCAP_P1
I
MFP7
Timer Continuous Capture input pin
I2C1_SDA
I/O
MFP8
I C1 data input/output pin.
SPI0_MISO
I/O
MFP9
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MOSI
I/O
MFPA
SPI1 MOSI (Master Out, Slave In) pin.
I
MFPB
Data receiver input pin for UART1.
PD.2
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
ADC1_CH1
A
MFP2
ADC1 channel1 analog input.
CCAP_P0
I
MFP7
Timer Continuous Capture input pin
I2C0_SDA
I/O
MFP8
I C0 data input/output pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFPB
Data receiver input pin for UART0.
PD.3
I/O
MFP0
General purpose digital I/O pin.
BPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
11
12
UART1_RXD
13
UART0_RXD
MINI57 SERIES DATASHEET
14
2
2
15
NC
No Connection
16
NC
No Connection
17
NC
No Connection
18
NC
No Connection
PD.5
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PA.5
I/O
MFP0
General purpose digital I/O pin.
XT_OUT
O
MFP1
External 4~24 MHz (high speed) crystal output pin.
EPWM_CH5
I/O
MFP3
PWM channel5 output/capture input.
ACMP0_O
O
MFP4
Analog comparator0 output.
PA.4
I/O
MFP0
General purpose digital I/O pin.
19
20
21
Apr. 06, 2017
Page 28 of 131
Rev.1.00
Mini57
XT_IN
EPWM_CH4
22
I
MFP1
External 4~24 MHz (high speed) crystal input pin.
I/O
MFP3
PWM channel4 output/capture input.
NC
No Connection
PA.3
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH3
I/O
MFP3
PWM channel3 output/capture input.
I2C0_SCL
I/O
MFP8
I C0 clock pin.
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PA.2
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH2
I/O
MFP3
PWM channel2 output/capture input.
I2C0_SDA
I/O
MFP8
I C0 data input/output pin.
SPI0_MOSI
I/O
MFP9
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1_MISO
I/O
MFPA
SPI1 MISO (Master In, Slave Out) pin.
I
MFPB
Data receiver input pin for UART0.
PA.1
I/O
MFP0
General purpose digital I/O pin.
EPWM_CH1
I/O
MFP3
PWM channel1 output/capture input.
I2C1_SDA
I/O
MFP8
I C1 data input/output pin.
SPI0_MISO
I/O
MFP9
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1_MOSI
I/O
MFPA
SPI1 MOSI (Master Out, Slave In) pin.
I
MFPB
Data receiver input pin for UART1.
PA.0
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Out
EPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
I2C1_SCL
I/O
MFP8
I C1 clock pin.
SPI0_SS
I/O
MFP9
SPI0 slave select pin.
SPI1_CLK
I/O
MFPA
SPI1 serial clock pin
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
PC.4
I/O
MFP0
General purpose digital I/O pin.
I
MFP7
Enhanced Input Capture input pin
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH3
A
MFP2
ADC0 channel3 analog input.
BPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
ACMP1_P0
A
MFP5
Analog comparator1 positive input pin.
2
23
2
24
UART0_RXD
2
25
UART1_RXD
MINI57 SERIES DATASHEET
26
2
27
ECAP_P3
PC.0
28
Apr. 06, 2017
Page 29 of 131
Rev.1.00
Mini57
29
I/O
MFP8
I C1 clock pin.
SPI0_SS
I/O
MFP9
SPI0 slave select pin.
SPI1_CLK
I/O
MFPA
SPI1 serial clock pin
UART1_TXD
O
MFPB
Data transmitter output pin for UART1.
PD.4
I/O
MFP0
General purpose digital I/O pin.
BPWM_CH0
I/O
MFP3
PWM channel0 output/capture input.
UART1_RXD
I
MFPB
Data receiver input pin for UART1.
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
ACMP1_P2
A
MFP5
Analog comparator1 positive input pin.
I2C0_SCL
I/O
MFP8
I C0 clock pin.
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
UART0_TXD
O
MFPB
Data transmitter output pin for UART0.
PC.3
I/O
MFP0
General purpose digital I/O pin.
ACMP1_O
O
MFP5
Analog comparator1 output.
PGA_O
A
MFP6
PGA output pin
SPI0_CLK
I/O
MFP9
SPI0 serial clock pin.
SPI1_SS
I/O
MFPA
SPI1 slave select pin
PD.1
30
31
32
2
I2C1_SCL
NC
2
No Connection
MINI57 SERIES DATASHEET
Table 4.4-3 QFN33 Pin Description
Apr. 06, 2017
Page 30 of 131
Rev.1.00
Mini57
4.4.2
GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFP)
PA.0 MFP0 means SYS_GPA_MFP[3:0]=0x0.
PA.4 MFP5 means SYS_GPA_MFP[19:16]=0x5.
Group
Pin Name
GPIO
MFP*
Type
Description
ACMP0_P0
PB.0
MFP4
A
Comparator0 positive input pin.
ACMP0_P1
PB.1
MFP4
A
Comparator0 positive input pin.
ACMP0_P2
PB.2
MFP4
A
Comparator0 positive input pin.
ACMP0_N
PB.4
MFP4
A
Comparator0 negative input pin.
ACMP0_P3
PC.1
MFP4
A
Comparator0 positive input pin.
ACMP0_O
PA.5
MFP4
O
Comparator0 output pin.
ACMP1_P1
PC.1
MFP5
A
Comparator1 positive input pin.
ACMP1_N
PB.3
MFP5
A
Comparator1 negative input pin.
ACMP1_O
PC.3
MPF5
O
Comparator1 output pin.
ACMP1_P2
PD.1
MFP5
A
Comparator1 positive input pin.
ACMP1_P0
PC.0
MFP5
A
Comparator1 positive input pin.
ADC0_CH0
PB.0
MFP2
A
ADC0 analog input channel 0.
ADC0_CH1
PB.1
MFP2
A
ADC0 analog input channel 1.
ADC0_CH2
PB.2
MFP2
A
ADC0 analog input channel 2.
ADC0_CH4
PC.1
MFP2
A
ADC0 analog input channel 4.
ADC0_CH3
PC.0
MFP2
A
ADC0 analog input channel 3.
ADC1_CH0
PB.4
MFP2
A
ADC1 analog input channel 0.
ADC1_CH2
PC.2
MFP2
A
ADC1 analog input channel 2.
ADC1_CH1
PD.2
MFP2
A
ADC1 analog input channel 1.
BPWM_CH1
PB.2
MFP3
O
Basic PWM channel 1 output
BPWM_CH0
PC.0
MFP3
O
Basic PWM channel 0 output
BPWM_CH1
PD.3
MFP3
O
Basic PWM channel 1 output
BPWM_CH0
PD.4
MFP3
O
Basic PWM channel 0 output
CCAP_P1
PC.2
MFP7
I
Continuous Capture Input
CCAP_P0
PD.2
MFP7
I
Continuous Capture Input
CLKO
PA.0
MFP1
O
Clock output pin.
ECAP_P0
PB.0
MFP7
I
Input capture channel 0
ECAP_P1
PB.1
MFP7
I
Input capture channel 1
ECAP_P2
PB.2
MFP7
I
Input capture channel 2
ACMP0
ACMP1
ADC0
MINI57 SERIES DATASHEET
ADC1
BPWM
CCAP
CLKO
ECAP
Apr. 06, 2017
Page 31 of 131
Rev.1.00
Mini57
EPWM
2
BRAKE
PC.2
MFP3
I
EPWM brake pin.
EPWM_CH5
PA.5
MFP3
O
Enhanced PWM output pin.
EPWM_CH4
PA.4
MFP3
O
Enhanced PWM output pin.
EPWM_CH3
PA.3
MFP3
O
Enhanced PWM output pin.
EPWM_CH2
PA.2
MFP3
O
Enhanced PWM output pin.
EPWM_CH1
PA.1
MFP3
O
Enhanced PWM output pin.
EPWM_CH0
PA.0
MFP3
O
Enhanced PWM output pin.
I2C1_SDA
PC.2
MFP8
I/O
I C1 data pin.
I2C0_SDA
PD.2
MFP8
I/O
I C0 data pin.
I2C0_SCL
PD.1
MFP8
I/O
I C0 clock pin.
I2C1_SCL
PC.0
MFP8
I/O
I C1 clock pin.
I2C0_SCL
PA.3
MFP8
I/O
I C0 clock pin.
I2C0_SDA
PA.2
MFP8
I/O
I C0 data pin.
I2C1_SDA
PA.1
MFP8
I/O
I C1 data pin.
I2C1_SCL
PA.0
MFP8
I/O
I C1 clock pin.
ICE_DAT
PD.2
MFP1
I/O
Serial wired debugger data pin
ICE_CLK
PD.1
MFP1
I
Serial wired debugger clock pin
I
External reset pin, internal pull-high.
IC
2
2
2
2
2
2
2
2
ICE
nRESET
nRESET
PGA_I
PB.3
MFP6
A
PGA analog input pin.
PGA_O
PC.3
MFP6
A
PGA analog output pin.
SPI0_MOSI
PC.1
MFP9
I/O
SPI0 MOSI (Master Out, Slave In) pin.
SPI0_MISO
PC.2
MFP9
I/O
SPI0 MISO (Master In, Slave Out) pin.
SPI0_MOSI
PD.2
MFP9
I/O
SPI0 MOSI (Master Out, Slave In) pin.
SPI0_CLK
PC.3
MFP9
I/O
SPI0 clock pin.
SPI0_CLK
PD.1
MFP9
I/O
SPI0 clock pin.
SPI0_SS
PC.0
MFP9
I
SPI0_CLK
PA.3
MFP9
I/O
SPI0 clock pin.
SPI0_MOSI
PA.2
MFP9
I/O
SPI0 MOSI (Master Out, Slave In) pin.
SPI0_MISO
PA.1
MFP9
I/O
SPI0 MISO (Master In, Slave Out) pin.
SPI0_SS
PA.0
MFP9
I
SPI1_MISO
PC.1
MFPA
I/O
SPI1 MISO (Master In, Slave Out) pin
SPI1_MOSI
PC.2
MFPA
I/O
SPI1 MOSI (Master Out, Slave In) pin.
SPI1_MISO
PD.2
MFPA
I/O
SPI1 MISO (Master In, Slave Out) pin
SPI1_SS
PC.3
MFPA
I/O
SPI1 Slave Select
PGA
MINI57 SERIES DATASHEET
SPI0
SPI0 slave selection pin.
SPI0 slave selection pin.
SPI1
Apr. 06, 2017
Page 32 of 131
Rev.1.00
Mini57
SPI1_SS
PD.1
MFPA
I/O
SPI1 Slave Select
SPI1_CLK
PC.0
MFPA
I/O
SPI1 clock pin.
SPI1_SS
PA.3
MFPA
I
SPI1_MISO
PA.2
MFPA
I/O
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MOSI
PA.1
MFPA
I/O
SPI1 MOSI (Master Out, Slave In) pin.
SPI1_CLK
PA.0
MFPA
I/O
SPI1 clock pin.
STADC
STADC
PC.1
MFP3
I
External ADC trigger input pin.
TM0
TM0
PB.3
MFP7
I
Timer0 event counter input / toggle output
TM1
TM1
PB.4
MFP7
I
Timer1 event counter input / toggle output
UART0_RXD
PD.2
MFPB
I
UART0 data receiver input pin.
UART0_TXD
PD.1
MFPB
O
UART0 data transmitter output pin.
UART0_TXD
PA.3
MFPB
O
UART0 data transmitter output pin.
UART0_RXD
PA.2
MFPB
I
UART0 data receiver input pin.
UART0_TXD
PD.5
MFPB
O
UART0 data transmitter output pin.
UART0_RXD
PD.6
MFPB
I
UART0 data receiver input pin.
UART1_RXD
PC.2
MFPB
I
UART1 data receiver input pin.
UART1_TXD
PC.0
MFPB
O
UART1 data transmitter output pin.
UART1_RXD
PA.1
MFPB
I
UART1 data receiver input pin.
UART1_TXD
PA.0
MFPB
O
UART1 data transmitter output pin.
UART1_TXD
PD.3
MFPB
O
UART1 data transmitter output pin.
UART1_RXD
PD.4
MFPB
I
UART1 data receiver input pin.
XT_OUT
PA.5
MPF1
A
External crystal output pin.
XT_IN
PA.4
MFP1
A
External crystal input pin.
SPI1 slave selection pin.
UART0
UART1
MINI57 SERIES DATASHEET
XT
Table 4.4-4 TSSOP20 Multi-function Pin Summary
Apr. 06, 2017
Page 33 of 131
Rev.1.00
Mini57
5
BLOCK DIAGRAM
5.1 NuMicro® Mini57 Block Diagram
MINI57 SERIES DATASHEET
Figure 5.1-1 NuMicro® Mini57 Block Diagram
Apr. 06, 2017
Page 34 of 131
Rev.1.00
Mini57
6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
6.1.1
Overview
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes – Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6.1-1 shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Wakeup
Interrupt
Controller
(WIC)
Debug
Cortex-M0
Processor
Core
Breakpoint
and
Watchpoint
Unit
Bus matrix
Debugger
interface
AHB-Lite interface
Debug
Access Port
(DAP)
Serial Wire or
JTAG debug port
MINI57 SERIES DATASHEET
Figure 6.1-1 Functional Block Diagram
Apr. 06, 2017
Page 35 of 131
Rev.1.00
Mini57
6.1.2
Features
The implemented device provides:
MINI57 SERIES DATASHEET
Apr. 06, 2017
A low gate count processor:
-
ARMv6-M Thumb® instruction set
-
Thumb-2 technology
-
ARMv6-M compliant 24-bit SysTick timer
-
A 32-bit hardware multiplier
-
System interface supported with little-endian data accesses
-
Ability to have deterministic, fixed-latency, interrupt handling
-
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
-
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
-
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
-
32 external interrupt inputs, each with four levels of priority
-
Dedicated Non-maskable Interrupt (NMI) input
-
Supports for both level-sensitive and pulse-sensitive interrupt lines
-
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support:
-
Four hardware breakpoints
-
Two watchpoints
-
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
-
Single step and vector catch capabilities
Bus interfaces:
-
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
-
Single 32-bit slave port that supports the DAP (Debug Access Port)
Page 36 of 131
Rev.1.00
Mini57
6.2 System Manager
6.2.1
Overview
System management includes the following sections:
6.2.2
System Reset
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip
through peripheral reset signals. Software reset can trigger reset through control registers.
Apr. 06, 2017
-
Power-on Reset (POR)
-
Low level on the nRESET pin
-
Watchdog Timer Time-out Reset (WDT)
-
Low Voltage Reset (LVR)
-
Brown-out Detector Reset (BOD Reset)
Software Reset Sources
-
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
-
MCU Reset to reboot but keeping the booting setting from APROM or LDROM
by writing 1 to SYSRESETREQ (SCS_AIRCR[2])
-
CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
Page 37 of 131
Rev.1.00
MINI57 SERIES DATASHEET
Hardware Reset Sources
Mini57
Glitch Filter
16.8 us
nRESET
~50k ohm
@5v
VDD
Power-on
Reset
VDD
Low Voltage
Reset
Reset Pulse Width
3.2ms
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT
Reset
Reset Pulse Width
64 WDT clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(SCS_AIRCR[2])
Software Reset
Reset Pulse Width
2 system clocks
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Resources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However,
there are small differences between each reset source and they are listed in Table 6.2-5.
MINI57 SERIES DATASHEET
Reset Sources
POR
nRESET
WDT
LVR
BOD
CHIP
MCU
CPU
SYS_RSTSTS
0x001
Bit 1 = 1
Bit 2 = 1
0x001
Bit 4 = 1
Bit 0 = 1
Bit 5 = 1
Bit 7 = 1
CHIPRST
0x0
-
-
-
-
-
-
-
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG
0
-
Reload
from
CONFIG0
Reload
from
CONFIG0
-
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
-
0x1
-
-
0x1
-
Register
(SYS_IPRST0[0])
BODEN
(SYS_BODCTL[0])
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
XTLEN
(CLK_PWRCTL[1:0])
WDTCKEN
-
(CLK_APBCLK0[0])
Apr. 06, 2017
Page 38 of 131
Rev.1.00
Mini57
HCLKSEL
0x8
0x8
0x8
0x8
0x8
0x8
0x8
-
0x3
0x3
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
0x0
-
-
-
-
-
-
-
0x0
0x0
-
-
-
-
-
-
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
0x0700
-
-
WDT_ALTCTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
WWDT_RLDCNT
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
WWDT_CTL
0x3F0800
0x3F0800
0x3F0800
0x3F080
0
0x3F0800
0x3F0800
-
-
WWDT_STATUS
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
WWDT_CNT
0x3F
0x3F
0x3F
0x3F
0x3F
0x3F
-
-
BS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG
0
Reload
from
CONFIG0
Reload
from
CONFIG0
-
-
FMC_DFBA
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG
1
Reload
from
CONFIG1
Reload
from
CONFIG1
-
-
CBS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG
0
Reload
from
CONFIG0
Reload
from
CONFIG0
-
-
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG
0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
-
-
(CLK_CLKSEL0[1:0])
WDTSEL
(CLK_CLKSEL1[1:0])
XLTSTB
(CLK_STATUS[0])
LIRCSTB
0x0
(CLK_STATUS[3])
HIRCSTB
(CLK_STATUS[4])
CLKSFAIL
(CLK_STATUS[7])
(FMC_ISPCTL[1])
ISPEN
(FMC_ISPCTL[16])
VECMAP
(FMC_ISPSTS[20:9])
Other
Registers
Peripheral
FMC Registers
Reset Value
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
6.2.2.1
nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
Apr. 06, 2017
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MINI57 SERIES DATASHEET
(FMC_ISPSTS[2:1))
Mini57
voltage is lower than 0.2 VDD and the state keeps longer than 16.8 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 36 us (glitch filter). The PINRF (SYS_RSTSTS[1]) will be
set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
nRESET
0.7 VDD
16.8 us
0.2 VDD
16.8 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2
Power-On Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the PORF (SYS_RSTSTS[0]) will be
set to 1 to indicate there is a POR reset event. The PORF (SYS_RSTSTS[0]) bit can be cleared
by writing 1 to it. Figure 6.2-3 shows the waveform of Power-On reset.
MINI57 SERIES DATASHEET
VPOR
0.1V
VDD
Power On
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3
Low Voltage Reset (LVR)
Low Voltage Reset detects AVDD during system operation. When the AVDD voltage is lower than
Apr. 06, 2017
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Mini57
VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset. The LVR
reset will control the chip in reset state until the AVDD voltage rises above VLVR and the state
keeps longer than De-glitch time. The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous
reset source is nRESET reset. Figure 6.2-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < de-glitch time) ( = de-glitch time)
Low Voltage Reset
T3
( = de-glitch time)
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AVDD during system
operation. When the AVDD voltage is lower than VBOD which is decided by BODEN
(SYS_BODCTL[0]) and BODVL (SYS_BODCTL[2:1]) and the state keeps longer than De-glitch
time (Max(20*HCLK cycles, 1*LIRC cycle)), chip will be reset. The BOD reset will control the chip
in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De-glitch
time. The default value of BODEN, BODVL and BODRSTEN is set by Flash controller user
configuration register CBODEN (CONFIG0[12]), CBOV (CONFIG0[15:13]) and CBORST
(CONFIG0[12]) respectively. User can determine the initial BOD setting by setting the CONFIG0
register. Figure 6.2-5 shows the Brown-Out Detector waveform.
Apr. 06, 2017
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MINI57 SERIES DATASHEET
6.2.2.4
Mini57
AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< de-glitch time) (= de-glitch time)
BODOUT
T3
(= de-glitch time)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
MINI57 SERIES DATASHEET
6.2.2.5
Watchdog Timer Reset
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer (WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking WDTRF
(SYS_RSTSTS[2]).
6.2.2.6
CPU Reset, CHIP Reset and SYSTEM Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST (SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and BS
(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG setting. User can set the CHIPRST
(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS (FMC_ISPCTL[1]) will not
be reloaded from CONFIG setting and keep its original software setting for booting from APROM
or LDROM. User can set the SYSRESETREQ (SCS_AIRCR[2]) to 1 to assert the MCU Reset.
Apr. 06, 2017
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Mini57
6.2.3
Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, SPI,
ACMP, BOD and GPIO
Available Clocks
All
All except CPU clock
LXT and LIRC
After Wake-up
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-2 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
Idle Mode
Wake-up events
occur
Power-down Mode
CPU Clock OFF
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash Halt
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
Flash Halt
Figure 6.2-6 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
Normal Mode
Idle Mode
Power-Down Mode
HXT (4~20 MHz XTL)
ON
ON
Halt
HIRC (12/16 MHz OSC)
ON
ON
Halt
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MINI57 SERIES DATASHEET
1. SLEEPDEEP (SCS_SCR[2]) = 1
2. PDEN (CLK_PWRCTL[7]) = 1 and
PDWKIF (CLK_PWRCTL[8]) = 1
3. CPU executes WFI
Mini57
1
LXT (32768 Hz XTL)
ON
ON
ON/OFF
LIRC (10 kHz OSC)
ON
ON
ON/OFF
LDO
ON
ON
ON
CPU
ON
Halt
Halt
HCLK/PCLK
ON
ON
Halt
SRAM retention
ON
ON
ON
FLASH
ON
ON
Halt
GPIO
ON
ON
Halt
TIMER
ON
ON
ON/OFF
BPWM
ON
ON
Halt
EPWM
ON
ON
Halt
WDT
ON
ON
ON/OFF
USCI
ON
ON
Halt
ADC
ON
ON
Halt
ACMP
ON
ON
Halt
ECAP
ON
ON
Halt
HDIV
ON
ON
Halt
PGA
ON
ON
Halt
2
3
4
Table 6.2-3 Clocks in Power Modes
MINI57 SERIES DATASHEET
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, SPI, BOD, ACMP and GPIO
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN (CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
Source
BOD
System Can Enter Power-Down Mode Again Condition*
Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF].
GPIO
GPIO Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
Timer Interrupt
After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
(TIMERx_INTSTS[0]).
WDT
WDT Interrupt
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
USCI UART
Incoming data wake-up
TIMER
Apr. 06, 2017
After software writes 1 to clear WKF (UUART_WKSTS[0]).
Page 44 of 131
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Mini57
USCI SPI
2
USCI I C
ACMP
SS transaction wake-up
After software writes 1 to clear WKF (USPI_WKSTS[0]).
Data toggle
After software writes 1 to clear WKF (UI2C_WKSTS[0]).
Address match
After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], then writes 1
to clear WKF (UI2C_WKSTS[0]).
Comparator Power-down
Wake-Up Interrupt
After software writes 1 to clear ACMPF0 (ACMP_STATUS[0]) and ACMPF1
(ACMP_STATUS[1]).
Table 6.2-4 Condition of Entering Power-down Mode Again
MINI57 SERIES DATASHEET
Apr. 06, 2017
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Mini57
6.2.4
System Power Architecture
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation. AVDD must be equal to VDD to avoid leakage current.
Digital power from VDD and VSS supplies power to the I/O pins and internal regulator
which provides a fixed 1.5V power for digital operation.
A built-in capacitor for internal voltage regulator
The output of internal voltage regulator, LDO, does not require an external capacitor and doesn’t
bond out to external pin. Analog power (AVDD) should be the same voltage level of the digital
power (VDD).
Temperature
Sensor
SRAM
Flash
Digital Logic
1.5V
48 MHz HIRC
Oscillator
POR15
XT_OUT
XT_IN
4~24 MHz or
32.768 kHz
crystal oscillator
MINI57 SERIES DATASHEET
12-bit ADC
POR50
2.1~5.5V
to 1.5V
LDO
Brown-out
Detector
Low Voltage
Reset
Power On
Control
10 kHz
LIRC
Oscillator
IO Cell
GPIO
Analog
Comparator
VSS
VDD
Mini57 power distribution
Figure 6.2-7 NuMicro® Mini57 Series Power Architecture Diagram
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6.2.5
System Memory Mapping
Mini57
4 GB
System Control
0xFFFF_FFFF
Reserved
|
0xE000_F000
System C ontrol
System C ontrol
0xE000_ED00
SC S_BA
External Interrupt C ontrol
0xE000_E100
SC S_BA
System Timer C ontrol
0xE000_E010
SC S_BA
0xE000_EFFF
0xE000_E000
0xE000_E00F
Reserved
|
0x6002_0000
Reserved
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
Reserved
|
0x5020_0000
AHB
Reserved
AHB peripherals
0x501F_FFFF
FMC
0x5000_C 000
FMC _BA
0x5000_0000
GPIO C ontrol
0x5000_4000
GP_BA
0x4FFF_FFFF
Interrupt Multiplexer C ontrol
0x5000_0300
INT_BA
C lock C ontrol
0x5000_0200
C LK_BA
System Global C ontrol
0x5000_0000
SYS_BA
EC AP C ontrol
0x401B_0000
EC AP_BA
USC I1 C ontrol
0x4017_0000
USC I1_BA
BPWM C ontrol
0x4014_0000
BPWM_BA
PGA C ontrol
0x400F_0000
PGA_BA
ADC C ontrol
0x400E_0000
ADC _BA
0x2000_1000
AC MP 0/1 C ontrol
0x400D_0000
AC MP_BA
0x2000_0FFF
USC I0 C ontrol
0x4007_0000
USC I0_BA
0x2000_0000
EPWM C ontrol
0x4004_0000
EPWM_BA
0x1FFF_FFFF
Timer0/Timer1 C ontrol
0x4001_0000
TMR01_BA
WDT C ontrol
0x4000_4000
WDT_BA
|
0x4020_0000
0x401F_FFFF
APB
1 GB
|
0x4000_0000
0x3FFF_FFFF
Reserved
4 KB SRAM
Reserved
|
MINI57 SERIES DATASHEET
0.5 GB
|
APB peripherals
0x0000_7600
0x0000_75FF
29.5 KB on-chip Flash (Mini57)
0 GB
|
0x0000_0000
Table 6.2-5 Memory Mapping Table
Apr. 06, 2017
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Mini57
6.2.6
Register Protection
Some of the system control registers need to be protected to avoid inadvertent write and disturb
the chip operation. These system control registers are protected after the power on reset till user
to disable register protection. For user to program these protected registers, a register protection
disable sequence needs to be followed by a special programming. The register protection disable
sequence is writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL continuously. Any
different data value, different sequence or any other write to other address during these three
data writing will abort the whole sequence.
After the protection is disabled, user can check REGLCTL (SYS_REGLCTL [0]), “1” is protection
disable, “0” is protection enable. Then user can update the target protected register value and
then write any data to SYS_REGLCTL to enable register protection.
The protected registers are listed in Table 6.2-6.
Register
Bit
Description
[1] CPURST
Processor Core One-shot Reset (Write Protect)
[0] CHIPRST
Chip One-shot Reset (Write Protect)
[15] LVREN
Low Voltage Reset Enable Control (Write Protect)
[6] BODLPM
Brown-out Detector Low Power Mode (Write Protect)
[4] BODRSTEN
Brown-out Reset Enable Control (Write Protect)
[3:1] BODVL
Brown-out Detector Threshold Voltage Selection (Write Protect)
[0] BODEN
Brown-out Detector Enable Control (Write Protect)
SYS_PORCTL
[15:0] POROFF
Power-on Reset Enable Control (Write Protect)
INT_NMICTL
[8] NMISELEN
NMI Interrupt Enable Control (Write Protected)
[11:10] HXTGAIN
HXT Gain Control (Write Protect)
[7] PDEN
System Power-down Enable Control (Write Protect)
[5] PDWKIEN
Power-down Mode Wake-up Interrupt Enable Control (Write Protect)
[4] PDWKDLY
Wake-up Delay Counter Enable Control (Write Protect)
[3] LIRCEN
LIRC Enable Control (Write Protect)
[2] HIRCEN
HIRC Enable Control (Write Protect)
[1:0] XTLEN
XTL Enable Control (Write Protect)
[0] WDTCKEN
Watchdog Timer Clock Enable Control (Write Protect)
[4:3] STCLKSEL
Cortex® -M0 SysTick Clock Source Selection (Write Protect)
[1:0] HCLKSEL
HCLK Clock Source Selection (Write Protect)
[1:0] WDTSEL
Watchdog Timer Clock Source Selection (Write Protect)
[6] ISPFF
ISP Fail Flag (Write Protect)
[5] LDUEN
LDROM Update Enable Control (Write Protect)
[4] CFGUEN
CONFIG Update Enable Control (Write Protect)
SYS_IPRST0
SYS_BODCTL
MINI57 SERIES DATASHEET
CLK_PWRCTL
CLK_APBCLK
CLK_CLKSEL0
CLK_CLKSEL1
FMC_ISPCTL
Apr. 06, 2017
Page 48 of 131
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Mini57
[3] APUEN
APROM Update Enable Control (Write Protect)
[2] SPUEN
SPROM Update Enable Control (Write Protect)
[1] BS
Boot Select (Write Protect)
[0] ISPEN
ISP Enable Control (Write Protect)
FMC_ISPTRG
[0] ISPGO
ISP Start Trigger (Write Protect)
FMC_ISPSTS
[6] ISPFF
ISP Fail Flag (Write Protect)
TIMER0_CTL
[31] ICEDEBUG
ICE Debug Mode Acknowledge Disable Control (Write Protect)
TIMER1_CTL
[31] ICEDEBUG
ICE Debug Mode Acknowledge Disable Control (Write Protect)
[31] ICEDEBUG
ICE Debug Mode Acknowledge Disable Control (Write Protect)
[7] WDTEN
Watchdog Timer Enable Control (Write Protect)
[6] INTEN
Watchdog Timer Time-out Interrupt Enable Control (Write Protect)
[4] WKEN
Watchdog Timer Time-out Wake-up Function Control (Write Protect)
[1] RSTEN
Watchdog Timer Time-out Reset Enable Control (Write Protect)
[0] RSTCNT
Reset Watchdog Timer Up Counter (Write Protect)
WDT_CTL
Table 6.2-6 Protected Registers
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 49 of 131
Rev.1.00
Mini57
6.2.7
6.2.7.1
Memory Organization
Overview
The NuMicro® Mini57 series provides 4G-byte addressing space. The addressing space assigned
to each on-chip controllers is shown in Figure 6.2-8. The detailed register definition, addressing
space, and programming details will be described in the following sections for each on-chip
peripheral. The Mini57 series only supports little-endian data format.
Reserved
Reserved
0x0030_0004
0x0030_0000
User
User Configuration
Configuration
(8B)
(8B)
Reserved
Reserved
0x0028_01FF
0x0028_0000
Security
Security Protection
Protection
ROM2
ROM2
(SPROM1
(SPROM1 512B)
512B)
Reserved
Reserved
0x0024_01FF
0x0024_0000
Security
Security Protection
Protection
ROM1
ROM1
(SPROM1
(SPROM1 512B)
512B)
Reserved
Reserved
0x0020_01FF
0x0020_0000
Security
Security Protection
Protection
ROM0
ROM0
(SPROM0
(SPROM0 512B)
512B)
Reserved
Reserved
0x0010_07FF
0x0010_0000
Loader
Loader ROM
ROM
(LDROM
(LDROM 2KB)
2KB)
Reserved
Reserved
MINI57 SERIES DATASHEET
0x0000_75FF
ApplicationROM
ApplicationROM
(APROM
(APROM 29.5KB)
29.5KB)
0x0000_0000
Figure 6.2-8 NuMicro® Mini57 Flash, Security and Configuration Map
6.2.7.2
System Memory Map
The Mini57 series provides 4G-byte addressing space. The memory locations assigned to each
on-chip controllers are shown in Table 6.2-7. The detailed register definition, memory space, and
programming will be described in the following sections for each on-chip peripheral. The Mini57
series only supports little-endian data format.
The memory locations assigned to each on-chip controllers are shown in Table 6.2-7.
Apr. 06, 2017
Page 50 of 131
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Mini57
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_75FF
FLASH_BA
FLASH Memory Space (29.5KB)
0x0010_0000 – 0x0010_07FF
LD_BA
Loader Memory Space (2 KB)
0x0020_0000 – 0x0020_01FF
SP0_BA
Security Program Memory 0 Space (0.5 KB)
0x0024_0000 – 0x0024_01FF
SP1_BA
Security Program Memory 1 Space (0.5 KB)
0x0028_0000 – 0x0028_01FF
SP2_BA
Security Program Memory 2 Space (0.5 KB)
0x2000_0000 – 0x2000_0FFF
SRAM_BA
SRAM Memory Space (4 KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
SYS_BA
System Control Registers
0x5000_0200 – 0x5000_02FF
CLK_BA
Clock Control Registers
0x5000_0300 – 0x5000_03FF
INT_BA
Interrupt Multiplexer Control Registers
0x5000_4000 – 0x5000_7FFF
GPIO_BA
GPIO Control Registers
0x5000_C000 – 0x5000_FFFF
FMC_BA
Flash Memory Control Registers
0x5001_4000 – 0x5001_7FFF
HDIV_BA
Hardware Divider Control Register
APB Controllers Space (0x4000_0000 ~ 0x401F_FFFF)
WDT_BA
Watchdog Timer Control Registers
0x4001_0000 – 0x4001_3FFF
TMR01_BA
Timer0/Timer1 Control Registers
0x4004_0000 – 0x4004_3FFF
EPWM_BA
Enhance PWM Control Registers
0x4007_0000 – 0x4007_3FFF
USCI0_BA
USCI0 Control Registers
0x400D_0000 – 0x400D_3FFF
ACMP_BA
Analog Comparator 0/1 Control Registers
0x400E_0000 – 0x400E_3FFF
ADC_BA
ADC Control Registers
0x400F_0000 – 0x400F_3FFF
PGA_BA
Programmable Gain Amplifier Control Register
0x4014_0000 – 0x4014_3FFF
BPWM_BA
Basic PWM Control Registers
0x4017_0000 – 0x4017_3FFF
USCI1_BA
USCI1 Control Registers
0x401B_0000 – 0x401B_3FFF
ECAP_BA
Enhanced Input Capture Timer Register
MINI57 SERIES DATASHEET
0x4000_4000 – 0x4000_7FFF
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
SCS_BA
System Timer Control Registers
0xE000_E100 – 0xE000_ECFF
SCS_BA
External Interrupt Controller Control Registers
0xE000_ED00 – 0xE000_ED8F
SCS_BA
System Control Registers
Table 6.2-7 Address Space Assignments for On-Chip Modules
Apr. 06, 2017
Page 51 of 131
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Mini57
6.2.7.3
SRAM Memory Organization
The Mini57 supports embedded SRAM with total 4 Kbytes size.
AHB Bus
Supports total 4 Kbytes SRAM
Supports byte / half word / word write
Supports oversize response error
AHB interface
controller
SRAM decoder
SRAM 4KB
Figure 6.2-9 SRAM Block Diagram
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 52 of 131
Rev.1.00
Mini57
6.2.8
System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
cleared-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used in several different ways, for example:
An RTOS tick timer fires at a programmable rate (for example 100Hz) and invokes a SysTick
routine.
A high-speed alarm timer uses Core clock.
A variable rate alarm or signal timer – the duration range is dependent on the reference clock
used and the dynamic range of the counter.
A simple counter can be used by software to measure task completion time.
An internal Clock Source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
When enabled, the timer will count down from the value in the SysTick Current Value Register
(SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock edge, and then decrement on subsequent clocks. When the
counter transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on read.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 53 of 131
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Mini57
6.2.8.1
System Timer Control Register Map
R: read only, W: write only, R/W: both read and write, W&C: write 1 to clear
Register
Offset
R/W
Description
Reset Value
SCS Base Address:
SCS_BA = 0xE000_E000
SYST_CTL
SCS_BA+0x10
R/W
SysTick Control and Status
0x0000_0004
SYST_RVR
SCS_BA+0x14
R/W
SysTick Reload Value Register
0xXXXX_XXXX
SYST_CVR
SCS_BA+0x18
R/W
SysTick Current Value Register
0xXXXX_XXXX
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 54 of 131
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Mini57
6.2.8.2
System Timer Control Register Description
SysTick Control and Status （SYST_CTL）
Register
Offset
R/W
Description
Reset Value
SYST_CTL
SCS_BA+0x10
R/W
SysTick Control and Status
0x0000_0004
31
30
29
28
27
26
25
24
19
18
17
16
Reserved
23
22
21
20
Reserved
15
14
13
12
COUNTFLAG
11
10
9
8
3
2
1
0
CLKSRC
TICKINT
ENABLE
Reserved
7
6
5
4
Reserved
Bits
Description
[31:17]
Reserved
Reserved.
System Tick Counter Flag
[16]
COUNTFLAG
Return 1 If Timer Counted to 0 Since Last Time this Register Was Read
0 = COUNTFLAG is cleared on read or by a write to the Current Value register.
1 = COUNTFLAG is set by a count transition from 1 to 0.
Reserved
[2]
CLKSRC
Reserved.
System Tick Clock Source Select Bit
0 = Clock source is optional, refer to STCLKSEL.
1 = Core clock used for SysTick timer.
System Tick Interrupt Enable Bit
[1]
TICKINT
0 = Counting down to 0 will not cause the SysTick exception to be pended. User can use
COUNTFLAG to determine if a count to zero has occurred.
1 = Counting down to 0 will cause the SysTick exception to be pended. Clearing the
SysTick Current Value register by a register write in software will not cause SysTick to be
pended.
System Tick Counter Enable Bit
[0]
ENABLE
0 = System Tick counter Disabled.
1 = System Tick counter will operate in a multi-shot manner.
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MINI57 SERIES DATASHEET
[15:3]
Mini57
SysTick Reload Value Register (SYST_RVR）
Register
Offset
R/W
Description
Reset Value
SYST_RVR
SCS_BA+0x14
R/W
SysTick Reload Value Register
0xXXXX_XXXX
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
RELOAD
15
14
13
12
RELOAD
7
6
5
4
RELOAD
Bits
Description
[31:24]
Reserved
[23:0]
RELOAD
Reserved.
System Tick Reload Value
Value to load into the Current Value register when the counter reaches 0.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 56 of 131
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Mini57
SysTick Current Value Register （SYST_CVR）
Register
Offset
R/W
Description
Reset Value
SYST_CVR
SCS_BA+0x18
R/W
SysTick Current Value Register
0xXXXX_XXXX
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
Reserved
23
22
21
20
CURRENT
15
14
13
12
CURRENT
7
6
5
4
CURRENT
Bits
Description
[31:24]
Reserved
Reserved.
System Tick Current Value
[23:0]
CURRENT
Current counter value. This is the value of the counter at the time it is sampled. The
counter does not provide read-modify-write protection. The register is write-clear. A
software write of any value will clear the register to 0.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 57 of 131
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Mini57
6.2.9
6.2.9.1
Nested Vectored Interrupt Control (NVIC)
Overview
The Cortex® -M0 CPU provides an interrupt controller as an integral part of the exception mode,
named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the
processor core and provides following features.
6.2.9.2
Features
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority change
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the Interrupt Service Routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
MINI57 SERIES DATASHEET
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
6.2.9.3
Exception Model and System Interrupt Map
Table 6.2-8 lists the exception model supported by the Mini57 series. Software can set four levels
of priority on some of these exceptions as well as on all interrupts. The highest user-configurable
priority is denoted as 0 and the lowest priority is denoted as 3. The default priority of all the userconfigurable interrupts is 0. Note that the priority 0 is treated as the fourth priority on the system,
after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Apr. 06, 2017
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Exception Name
Vector Number
Priority
Reset
1
-3
NMI
2
-2
Hard Fault
3
-1
Reserved
4 ~ 10
Reserved
SVCall
11
Configurable
Reserved
12 ~ 13
Reserved
PendSV
14
Configurable
SysTick
15
Configurable
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Configurable
Table 6.2-8 Exception Model
Vector
Number
Interrupt Number
(Bit
In
Registers)
Interrupt Interrupt Name
Interrupt Description
-
-
System exceptions
16
0
BOD_OUT
Brown-Out low voltage detected interrupt
17
1
WDTPINT
Watchdog Timer interrupt
18
2
USCI0
USCI0 interrupt
19
3
USCI1
USCI1 interrupt
20
4
GP_INT
External interrupt from GPA ~ GPD pins
21
5
EPWM_INT
EPWM interrupt
22
6
BRAKE0_INT
EPWM brake interrupt from PWM0 or PWM_BRAKE pin
23
7
BRAKE1_INT
EPWM brake interrupt from PWM1
24
8
BPWM0_INT
BPWM0 interrupt
25
9
BPWM1_INT
BPWM1 interrupt
26
10
Reserved
Reserved
27
11
Reserved
Reserved
28
12
Reserved
Reserved
29
13
Reserved
Reserved
30
14
Reserved
Reserved
31
15
ECAP_INT
Enhanced Input Capture interrupt
32
16
CCAP_INT
Continues Input Capture interrupt
33
17
Reserved
Reserved
Apr. 06, 2017
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MINI57 SERIES DATASHEET
0 ~ 15
Rev.1.00
Mini57
34
18
Reserved
Reserved
35
19
Reserved
Reserved
36
20
Reserved
Reserved
37
21
HIRCTRIM_INT
HIRC TRIM interrupt
38
22
TMR0_INT
Timer 0 interrupt
39
23
TMR1_INT
Timer 1 interrupt
40
24
Reserved
Reserved
41
25
Reserved
Reserved
42
26
ACMP_INT
Analog Comparator 0 or Comparator 1 interrupt
43
27
Reserved
Reserved
44
28
PWRWU_INT
Chip wake-up from Power-down state interrupt
45
29
ADC0_INT
ADC0 interrupt
46
30
ADC1_INT
ADC1 interrupt
47
31
ADCWCMP_INT
ADC Window Compare interrupt
Table 6.2-9 System Interrupt Map Vector Table
6.2.9.4
Vector Table
MINI57 SERIES DATASHEET
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table
based address is fixed at 0x00000000. The vector table contains the initialization value for the
stack pointer on reset, and the entry point addresses for all exception handlers. The vector
number on previous page defines the order of entries in the vector table associated with the
exception handler entry as illustrated in previous section.
Vector Table Word Offset (Bytes)
0x00
Exception Number * 0x04
Description
Initial Stack Pointer Value
Exception Entry Pointer using that Exception Number
Table 6.2-10 Vector Table Format
6.2.9.5
Operation Description
The NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt SetEnable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
Apr. 06, 2017
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Mini57
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 61 of 131
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Mini57
6.2.9.6
NVIC Control Registers Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
SCS Base Address:
SCS_BA = 0xE000_E000
NVIC_ISER
SCS_BA+0x100
R/W
IRQ0 ~ IRQ31 Set-Enable Control Register
0x0000_0000
NVIC_ICER
SCS_BA+0x180
R/W
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x0000_0000
NVIC_ISPR
SCS_BA+0x200
R/W
IRQ0 ~ IRQ31 Set-Pending Control Register
0x0000_0000
NVIC_ICPR
SCS_BA+0x280
R/W
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x0000_0000
NVIC_IPR0
SCS_BA+0x400
R/W
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x0000_0000
NVIC_IPR1
SCS_BA+0x404
R/W
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x0000_0000
NVIC_IPR2
SCS_BA+0x408
R/W
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x0000_0000
NVIC_IPR3
SCS_BA+0x40C
R/W
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x0000_0000
NVIC_IPR4
SCS_BA+0x410
R/W
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x0000_0000
NVIC_IPR5
SCS_BA+0x414
R/W
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x0000_0000
NVIC_IPR6
SCS_BA+0x418
R/W
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x0000_0000
NVIC_IPR7
SCS_BA+0x41C
R/W
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x0000_0000
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 62 of 131
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Mini57
IRQ0 ~ IRQ31 Set-enable Control Register (NVIC_ISER)
Register
Offset
R/W
Description
Reset Value
NVIC_ISER
SCS_BA+0x100
R/W
IRQ0 ~ IRQ31 Set-Enable Control Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SETENA
23
22
21
20
SETENA
15
14
13
12
SETENA
7
6
5
4
SETENA
Bits
Description
Interrupt Enable Register
Enable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
Write operation:
0 = No effect.
[31:0]
SETENA
1 = Write 1 to enable associated interrupt.
Read operation:
0 = Associated interrupt status Disabled.
MINI57 SERIES DATASHEET
1 = Associated interrupt status Enabled.
Read value indicates the current enable status.
Apr. 06, 2017
Page 63 of 131
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IRQ0 ~ IRQ31 Clear-enable Control Register (NVIC_ICER)
Register
Offset
R/W
Description
Reset Value
NVIC_ICER
SCS_BA+0x180
R/W
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CLRENA
23
22
21
20
CLRENA
15
14
13
12
CLRENA
7
6
5
4
CLRENA
Bits
Description
Interrupt Disable Register
Disable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
Write operation:
0 = No effect.
[31:0]
CLRENA
1 = Write 1 to disable associated interrupt.
Read operation:
0 = Associated interrupt status Disabled.
MINI57 SERIES DATASHEET
1 = Associated interrupt status Enabled.
Note: Read value indicates the current enable status.
Apr. 06, 2017
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IRQ0 ~ IRQ31 Set-pending Control Register (NVIC_ISPR)
Register
Offset
R/W
Description
Reset Value
NVIC_ISPR
SCS_BA+0x200
R/W
IRQ0 ~ IRQ31 Set-Pending Control Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SETPEND
23
22
21
20
SETPEND
15
14
13
12
SETPEND
7
6
5
4
SETPEND
Bits
Description
Set Interrupt Pending Register
Write operation:
0 = No effect.
[31:0]
SETPEND
1 = Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
Read operation:
0 = Associated interrupt in not in pending status.
1 = Associated interrupt is in pending status.
Apr. 06, 2017
Page 65 of 131
MINI57 SERIES DATASHEET
Note: Read value indicates the current pending status.
Rev.1.00
Mini57
IRQ0 ~ IRQ31 Clear-pending Control Register (NVIC_ICPR)
Register
Offset
R/W
Description
Reset Value
NVIC_ICPR
SCS_BA+0x280
R/W
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CLRPEND
23
22
21
20
CLRPEND
15
14
13
12
CLRPEND
7
6
5
4
CLRPEND
Bits
Description
Clear Interrupt Pending Register
Write operation:
0 = No effect.
[31:0]
CLRPEND
1 = Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~
IRQ31 (Vector number from 16 ~ 47).
Read operation:
0 = Associated interrupt in not in pending status.
1 = Associated interrupt is in pending status.
MINI57 SERIES DATASHEET
Note: Read value indicates the current pending status.
Apr. 06, 2017
Page 66 of 131
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Mini57
IRQ0 ~ IRQ3 Interrupt Priority Register (NVIC_IPR0)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR0
SCS_BA+0x400
R/W
IRQ0 ~ IRQ3 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_3
23
21
20
19
PRI_2
24
18
17
16
10
9
8
2
1
0
Reserved
14
13
12
11
PRI_1
7
Reserved
6
5
4
3
PRI_0
Description
[31:30]
PRI_3
[29:24]
Reserved
[23:22]
PRI_2
[21:16]
Reserved
[15:14]
PRI_1
[13:8]
Reserved
[7:6]
PRI_0
[5:0]
Reserved
Reserved
Priority of IRQ3
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ2
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ1
MINI57 SERIES DATASHEET
Bits
Apr. 06, 2017
25
Reserved
22
15
26
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ0
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 67 of 131
Rev.1.00
Mini57
IRQ4 ~ IRQ7 Interrupt Priority Register (NVIC_IPR1)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR1
SCS_BA+0x404
R/W
IRQ4 ~ IRQ7 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_7
23
21
20
19
PRI_6
24
18
17
16
10
9
8
2
1
0
Reserved
14
13
12
11
PRI_5
7
Reserved
6
5
4
3
PRI_4
MINI57 SERIES DATASHEET
Bits
Description
[31:30]
PRI_7
[29:24]
Reserved
[23:22]
PRI_6
[21:16]
Reserved
[15:14]
PRI_5
[13:8]
Reserved
[7:6]
PRI_4
[5:0]
Reserved
Apr. 06, 2017
25
Reserved
22
15
26
Reserved
Priority of IRQ7
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ6
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ5
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ4
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 68 of 131
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Mini57
IRQ8 ~ IRQ11 Interrupt Priority Register (NVIC_IPR2)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR2
SCS_BA+0x408
R/W
IRQ8 ~ IRQ11 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_11
23
21
20
19
PRI_10
24
18
17
16
10
9
8
2
1
0
Reserved
14
13
12
11
PRI_9
7
Reserved
6
5
4
3
PRI_8
Description
[31:30]
PRI_11
[29:24]
Reserved
[23:22]
PRI_10
[21:16]
Reserved
[15:14]
PRI_9
[13:8]
Reserved
[7:6]
PRI_8
[5:0]
Reserved
Reserved
Priority of IRQ11
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ10
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ9
MINI57 SERIES DATASHEET
Bits
Apr. 06, 2017
25
Reserved
22
15
26
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ8
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 69 of 131
Rev.1.00
Mini57
IRQ12 ~ IRQ15 Interrupt Priority Register (NVIC_IPR3)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR3
SCS_BA+0x40C
R/W
IRQ12 ~ IRQ15 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_15
23
21
20
19
PRI_14
13
12
11
PRI_13
18
17
16
10
9
8
2
1
0
Reserved
6
5
4
3
PRI_12
MINI57 SERIES DATASHEET
Bits
Description
[31:30]
PRI_15
[29:24]
Reserved
[23:22]
PRI_14
[21:16]
Reserved
[15:14]
PRI_13
[13:8]
Reserved
[7:6]
PRI_12
[5:0]
Reserved
Apr. 06, 2017
24
Reserved
14
7
25
Reserved
22
15
26
Reserved
Priority of IRQ15
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ14
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ13
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ12
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 70 of 131
Rev.1.00
Mini57
IRQ16 ~ IRQ19 Interrupt Priority Register (NVIC_IPR4)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR4
SCS_BA+0x410
R/W
IRQ16 ~ IRQ19 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_19
23
21
20
19
PRI_18
13
12
11
PRI_17
18
17
16
10
9
8
2
1
0
Reserved
6
5
4
3
PRI_16
Description
[31:30]
PRI_19
[29:24]
Reserved
[23:22]
PRI_18
[21:16]
Reserved
[15:14]
PRI_17
[13:8]
Reserved
[7:6]
PRI_16
[5:0]
Reserved
Reserved
Priority of IRQ19
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ18
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ17
MINI57 SERIES DATASHEET
Bits
Apr. 06, 2017
24
Reserved
14
7
25
Reserved
22
15
26
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ16
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 71 of 131
Rev.1.00
Mini57
IRQ20 ~ IRQ23 Interrupt Priority Register (NVIC_IPR5)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR5
SCS_BA+0x414
R/W
IRQ20 ~ IRQ23 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_23
23
21
20
19
PRI_22
13
12
11
PRI_21
18
17
16
10
9
8
2
1
0
Reserved
6
5
4
3
PRI_20
MINI57 SERIES DATASHEET
Bits
Description
[31:30]
PRI_23
[29:24]
Reserved
[23:22]
PRI_22
[21:16]
Reserved
[15:14]
PRI_21
[13:8]
Reserved
[7:6]
PRI_20
[5:0]
Reserved
Apr. 06, 2017
24
Reserved
14
7
25
Reserved
22
15
26
Reserved
Priority of IRQ23
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ22
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ21
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ20
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 72 of 131
Rev.1.00
Mini57
IRQ24 ~ IRQ27 Interrupt Priority Register (NVIC_IPR6)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR6
SCS_BA+0x418
R/W
IRQ24 ~ IRQ27 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_27
23
21
20
19
PRI_26
13
12
11
PRI_25
18
17
16
10
9
8
2
1
0
Reserved
6
5
4
3
PRI_24
Description
[31:30]
PRI_27
[29:24]
Reserved
[23:22]
PRI_26
[21:16]
Reserved
[15:14]
PRI_25
[13:8]
Reserved
[7:6]
PRI_24
[5:0]
Reserved
Reserved
Priority of IRQ27
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ26
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ25
MINI57 SERIES DATASHEET
Bits
Apr. 06, 2017
24
Reserved
14
7
25
Reserved
22
15
26
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ24
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 73 of 131
Rev.1.00
Mini57
IRQ28 ~ IRQ31 Interrupt Priority Register (NVIC_IPR7)
Register
Offset
R/W
Description
Reset Value
NVIC_IPR7
SCS_BA+0x41C
R/W
IRQ28 ~ IRQ31 Interrupt Priority Control Register
0x0000_0000
31
30
29
28
27
PRI_31
23
21
20
19
PRI_30
13
12
11
PRI_29
18
17
16
10
9
8
2
1
0
Reserved
6
5
4
3
PRI_28
MINI57 SERIES DATASHEET
Bits
Description
[31:30]
PRI_31
[29:24]
Reserved
[23:22]
PRI_30
[21:16]
Reserved
[15:14]
PRI_29
[13:8]
Reserved
[7:6]
PRI_28
[5:0]
Reserved
Apr. 06, 2017
24
Reserved
14
7
25
Reserved
22
15
26
Reserved
Priority of IRQ31
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ30
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ29
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Priority of IRQ28
0 denotes the highest priority and 3 denotes the lowest priority.
Reserved.
Page 74 of 131
Rev.1.00
Mini57
6.2.9.7
Interrupt Source Control Registers
Besides the interrupt control registers associated with the NVIC, the Mini57 series also
implements some specific control registers to facilitate the interrupt functions, including ”NMI
source selection” and “IRQ number identity”, which are described below.
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
INT Base Address:
INT_BA = 0x5000_0300
INT_NMICTL
INT_BA+0x80
R/W
NMI Source Interrupt Select Control Register
0x0000_0000
INT_IRQSTS
INT_BA+0x84
R/W
MCU IRQ Number Identity Register
0x0000_0000
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 75 of 131
Rev.1.00
Mini57
NMI Interrupt Source Select Control Register (INT_NMICTL)
Register
Offset
R/W
Description
Reset Value
INT_NMICTL
INT_BA+0x80
R/W
NMI Source Interrupt Select Control Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
NMISELEN
4
3
Reserved
Bits
Description
[31:9]
Reserved
2
1
0
NMISEL
Reserved.
NMI Interrupt Enable Bit (Write Protected)
0 = NMI interrupt Disabled.
[8]
NMISELEN
1 = NMI interrupt Enabled.
Note: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88
to address 0x5000_0100 to disable register protection. Refer to the register
SYS_REGLCTL at address SYS_BA+0x100.
MINI57 SERIES DATASHEET
[7:5]
Reserved
[4:0]
NMISEL
Reserved.
NMI Interrupt Source Selection
Apr. 06, 2017
®
The NMI interrupt to Cortex -M0 can be selected from one of the peripheral interrupt by
setting NMTSEL.
Page 76 of 131
Rev.1.00
Mini57
MCU Interrupt Request Source Register (INT_IRQSTS)
Register
Offset
R/W
Description
Reset Value
INT_IRQSTS
INT_BA+0x84
R/W
MCU IRQ Number Identity Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IRQ
23
22
21
20
IRQ
15
14
13
12
IRQ
7
6
5
4
IRQ
Bits
Description
MCU IRQ Source Register
The IRQ collects all the interrupts from the peripherals and generates the synchronous
®
®
interrupt to Cortex -M0 core. There is one mode to generate interrupt to Cortex -M0 - the
normal mode.
[31:0]
IRQ
The IRQ collects all interrupts from each peripheral and synchronizes them then interrupts
®
the Cortex -M0.
®
When the IRQ[n] is 0, setting IRQ[n] to 1 will generate an interrupt to Cortex -M0 NVIC[n].
When the IRQ[n] is 1 (i.e. an interrupt is assert), setting 1 to the MCU_bit[n] will clear the
interrupt and setting IRQ[n] 0 has no effect.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 77 of 131
Rev.1.00
Mini57
6.2.10 System Control Registers
Key control and status features of Cortex® -M0 are managed centrally in a System Control Block
within the System Control Registers.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 78 of 131
Rev.1.00
Mini57
6.2.10.1 System Control Register Memory Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
SCS Base Address:
SCS_BA = 0xE000_E000
SCS_CPUID
SCS_BA+0xD00
R
CPUID Base Register
0x410C_C200
SCS_ICSR
SCS_BA+0xD04
R/W
Interrupt Control State Register
0x0000_0000
SCS_AIRCR
SCS_BA+0xD0C
R/W
Application
Register
SCS_SCR
SCS_BA+0xD10
R/W
System Control Register
0x0000_0000
SCS_SHPR2
SCS_BA+0xD1C
R/W
System Handler Priority Register 2
0x0000_0000
SCS_SHPR3
SCS_BA+0xD20
R/W
System Handler Priority Register 3
0x0000_0000
Interrupt
and
Reset
Control
0xFA05_0000
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 79 of 131
Rev.1.00
Mini57
6.2.10.2 System Control Register Description
CPUID Base Register (CPUID)
Register
Offset
R/W
Description
Reset Value
SCS_CPUID
SCS_BA+0xD00
R
CPUID Base Register
0x410C_C200
31
30
29
28
27
26
25
24
18
17
16
IMPLEMENTER
23
22
21
20
19
Reserved
15
14
PART
13
12
11
10
9
8
3
2
1
0
PARTNO
7
6
5
4
PARTNO
MINI57 SERIES DATASHEET
Bits
Description
[31:24]
IMPLEMENTER
[23:20]
Reserved
[19:16]
PART
[15:4]
PARTNO
[3:0]
REVISION
Apr. 06, 2017
REVISION
Implementer Code
Implementer code assigned by ARM ( ARM = 0x41).
Reserved.
Architecture of the Processor
Reads as 0xC for ARMv6-M parts
Part Number of the Processor
Reads as 0xC20.
Revision Number
Reads as 0x0
Page 80 of 131
Rev.1.00
Mini57
Interrupt Control State Register (ICSR)
Register
Offset
R/W
Description
Reset Value
SCS_ICSR
SCS_BA+0xD04
R/W
Interrupt Control State Register
0x0000_0000
31
30
NMIPENDSET
23
29
Reserved
22
ISRPREEMPT ISRPENDING
15
14
28
27
PENDSVSET PENDSVCLR
21
20
6
25
24
PENDSTSET
PENDSTCLR
Reserved
18
17
16
9
8
19
Reserved
VECTPENDING
13
12
11
VECTPENDING
7
26
10
Reserved
5
4
3
2
VECTACTIVE
1
0
VECTACTIVE
Bits
Description
NMI Set-pending Bit
Write Operation:
0 = No effect.
1 = Changes NMI exception state to pending.
[31]
NMIPENDSET
Read Operation:
0 = NMI exception not pending.
1 = NMI exception pending.
[30:29]
Reserved
Reserved.
PendSV Set-pending Bit
Write Operation:
0 = No effect.
[28]
PENDSVSET
1 = Changes PendSV exception state to pending.
Read Operation:
0 = PendSV exception is not pending.
1 = PendSV exception is pending.
Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending
PendSV Clear-pending Bit
Write Operation:
[27]
PENDSVCLR
0 = No effect.
1 = Removes the pending state from the PendSV exception.
This bit is write-only. To clear the PENDSV bit, you must “write 0 to PENDSVSET
andwrite 1 to PENDSVCLR” at the same time.
[26]
Apr. 06, 2017
PENDSTSET
SysTick Exception Set-pending Bit
Page 81 of 131
Rev.1.00
MINI57 SERIES DATASHEET
Note: Because NMI is the highest-priority exception, normally the processor entersthe
NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler
then clears this bit to 0. This means a read of this bit by the NMI exceptionhandler returns
1 only if the NMI signal is reasserted while the processor is executingthat handler.
Mini57
Write Operation:
0 = No effect.
1 = Changes SysTick exception state to pending.
Read Operation:
0 = SysTick exception is not pending.
1 = SysTick exception is pending.
SysTick Exception Clear-pending Bit
Write Operation:
[25]
PENDSTCLR
0 = No effect.
1 = Removes the pending state from the SysTick exception.
Note: This bit is write-only. When you want to clear PENDST bit, you must “write 0
toPENDSTSET and write 1 to PENDSTCLR” at the same time.
[24]
Reserved
[23]
ISRPREEMPT
[22]
ISRPENDING
Reserved.
Interrupt Preempt Bit(Read Only)
If set, a pending exception will be serviced on exit from the debug halt state
Interrupt Pending Flag,Excluding NMI and Faults (Read Only)
0 = Interrupt not pending.
1 = Interrupt pending.
[21]
Reserved
[20:12]
VECTPENDING
Reserved.
Exception Number of the Highest Priority Pending Enabled Exception
0 = No pending exceptions.
Non-zero = Exception number of the highest priority pending enabled exception.
[11:9]
Reserved
Reserved.
Contains the Active Exception Number
[8:0]
VECTACTIVE
0 = Thread mode.
Non-zero = Exception number of the currently active exception.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 82 of 131
Rev.1.00
Mini57
Application Interrupt and Reset Control Register (AIRCR)
Register
Offset
R/W
Description
Reset Value
SCS_AIRCR
SCS_BA+0xD0C
R/W
Application Interrupt and Reset Control Register
0xFA05_0000
31
30
29
28
27
26
25
24
18
17
16
11
10
9
8
3
2
1
0
VECTORKEY
23
22
21
20
19
VECTORKEY
15
14
13
12
Reserved
7
6
5
4
Reserved
Bits
SYSRESETRE VECTCLRAC
Q
TIVE
Reserved
Description
Register Access Key
Write Operation:
[31:16]
VECTORKEY
When writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise
the write operation would be ignored. The VECTORKEY filed is used to prevent accidental
write to this register from resetting the system or clearing of the exception status.
Read Operation:
Read as 0xFA05.
[15:3]
Reserved
Reserved.
[2]
SYSRESETREQ
Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is
requested.
The bit is a write only bit and self-clears as part of the reset sequence.
[1]
Exception Active Status Clear Bit
VECTCLRACTIVE Reserved for debug use. When writing to the register, user must write 0 to this bit,
otherwise behavior is unpredictable.
[0]
Reserved
Apr. 06, 2017
Reserved.
Page 83 of 131
Rev.1.00
MINI57 SERIES DATASHEET
System Reset Request
Mini57
System Control Register (SCR)
Register
Offset
R/W
Description
Reset Value
SCS_SCR
SCS_BA+0xD10
R/W
System Control Register
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
4
3
2
1
0
SEVONPEND
Reserved
Reserved
23
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
Reserved
Bits
Description
[31:5]
Reserved
SLEEPDEEP SLEEPONEXI
T
Reserved
Reserved.
Send Event on Pending Bit
0 = Only enabled interrupts or events can wake-up the processor, disabled interrupts
areexcluded.
[4]
SEVONPEND
1 = Enabled events and all interrupts, including disabled interrupts, can wake-up
theprocessor.
When an event or interrupt enters pending state, the event signal wakes up the
processorfrom WFE. If the processor is not waiting for an event, the event is registered
and affectsthe next WFE.
MINI57 SERIES DATASHEET
The processor also wakes up on execution of an SEV instruction or an external event.
[3]
Reserved
Reserved.
Processor Deep Sleep and Sleep Mode Selection
[2]
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = Sleep mode.
1 = Deep Sleep mode.
Sleep-on-exit Enable Bit
This bit indicates sleep-on-exit when returning from Handler mode to Thread mode.
[1]
SLEEPONEXIT
0 = Do not sleep when returning to Thread mode.
1 = Enter Sleep or Deep Sleep when returning from ISR to Thread mode.Setting this bit
to 1 enables an interrupt driven application to avoid returning to an emptymain
application.
[0]
Apr. 06, 2017
Reserved
Reserved.
Page 84 of 131
Rev.1.00
Mini57
System Handler Priority Register 2 (SHPR2)
Register
Offset
R/W
Description
Reset Value
SCS_SHPR2
SCS_BA+0xD1C
R/W
System Handler Priority Register 2
0x0000_0000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PRI_11
23
Reserved
22
21
20
Reserved
15
14
13
12
Reserved
7
6
5
4
Reserved
Bits
Description
[31:30]
PRI_11
[29:0]
Reserved
Priority of System Handler 11 – SVCall
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 85 of 131
Rev.1.00
Mini57
System Handler Priority Register 3 (SHPR3)
Register
Offset
R/W
Description
Reset Value
SCS_SHPR3
SCS_BA+0xD20
R/W
System Handler Priority Register 3
0x0000_0000
31
30
29
28
27
26
25
24
18
17
16
11
10
9
8
3
2
1
0
PRI_15
23
Reserved
22
21
20
19
PRI_14
15
Reserved
14
13
12
Reserved
7
6
5
4
Reserved
Bits
Description
[31:30]
PRI_15
[29:24]
Reserved
[23:22]
PRI_14
[21:0]
Reserved
Priority of System Handler 15 – SysTick
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved.
Priority of System Handler 14 – PendSV
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 86 of 131
Rev.1.00
Mini57
6.3 Clock Controller
6.3.1
Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when the Cortex® -M0 core executes the WFI instruction only if the PDEN
(CLK_PWRCTL[7]) bit set to 1. After that, chip enters Power-down mode and waits for wake-up
interrupt source triggered to exit Power-down mode. In Power-down mode, the clock controller
turns off the 4~24 MHz external high speed crystal (HXT) and 48 MHz internal high speed RC
oscillator (HIRC) to reduce the overall system power consumption. Figure 6.3-2 shows the clock
generator and the overview of the clock source control.
The clock generator consists of 4 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
48 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
XT_IN
External 32.768
kHz Crystal
(LXT)
LXT
XT_OUT
HXTEN (CLK_PWRCTL[0])
MINI57 SERIES DATASHEET
External 4~24
MHz Crystal
(HXT)
HXT
HIRCEN (CLK_PWRCTL[2])
Internal 48 MHz
Oscillator
(HIRC)
HIRC
LIRCEN (CLK_PWRCTL[3])
Internal 10 kHz
Oscillator
(LIRC)
LIRC
Figure 6.3-1 Clock Generator Block Diagram
Apr. 06, 2017
Page 87 of 131
Rev.1.00
Mini57
HIRC
CPUCLK
48 MHz
HXT
10 kHz
LXT
4~24 MHz/32.768kHz
LIRC
11
HCLK
1/(HCLKDIV+1)
01
PCLK
00
CLK_CLKSEL0[1:0]
48 MHz
10 kHz
T0~T1
BOD
FMC
HCLK
HCLK
HCLK
1/(PGADIV+1)
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
ACMP
PGA
4~24 MHz/32.768kHz
4~24 MHz/32.768kHz
000
ECAP
HCLK
HCLK
001
4~24 MHz/32.768kHz
48 MHz
48 MHz
010
10 kHz
HDIV
TMR 0
TMR 1
011
HCLK
48 MHz
HCLK
111
1/2
11
1/2
10
1/2
01
CPUCLK
1
SysTick
0
11
10
4~24 MHz/32.768kHz
00
Clock Output
SYST_CTL[2]
CLK_CLKSEL0[4:3]
00
CLK_CLKSEL1[31:30]
48 MHz
MINI57 SERIES DATASHEET
HCLK
4~24 MHz/32.768kHz
11
10
1/(ADCDIV+1)
HCLK
PWM 10
HCLK
PWM 32
HCLK
PWM 54
ADC
00
CLK_CLKSEL1[5:4]
4~24MHz/32.768kHz
HCLK
1
0
USCI0
USCI1
USCI0_BRGEN[0]
USCI1_BRGEN[0]
10 kHz
HCLK
1/2048
4~24MHz/32.768kHz
11
10
WDT
00
CLK_CLKSEL1[1:0]
Figure 6.3-2 Clock Generator Global View Diagram
Apr. 06, 2017
Page 88 of 131
Rev.1.00
Mini57
6.3.2
Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate
LXT (32.768 kHz crystal oscillator), automatically gets accurate HIRC output frequency, 0.25 %
deviation within all temperature ranges.
For instance, the system needs an accurate 48MHz clock. In such case, if users do not want to use
PLL as the system clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL
(SYS_IRCTCTL[0] trim frequency selection) to “1”, and the auto-trim function will be enabled. Interrupt
status bit FREQLOCK (SYS_IRCTISTS[0] HIRC frequency lock status) “1” indicates the HIRC output
frequency is accurate within 0.25% deviation. To get better results, it is recommended to set both
LOOPSEL (SYS_IRCTCTL[5:4] trim calculation loop) and RETRYCNT (SYS_IRCTCTL[7:6] trim value
update limitation count) to “11”.
6.3.3
System Clock and SysTick Clock
The system clock has three clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[1:0]). The block diagram is
shown in Figure 6.3-3.
HCLKSEL (CLK_CLKSEL0[1:0])
48 MHz HIRC
10 kHz LXT
11
01
CPUCLK
1/(HCLKDIV+1)
4~24 MHz HXT or
32.768 kHz LXT
HCLKDIV (CLK_CLKDIV[3:0])
HCLK
PCLK
CPU
AHB
APB
00
CPU in Power Down Mode
Figure 6.3-3 System Clock Block Diagram
The clock source of SysTick in the Cortex® -M0 core can use CPU clock or external clock
CLKSRC(SYST_CTL[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources.
The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[4:3]).
The block diagram is shown in Figure 6.3-4.
Apr. 06, 2017
Page 89 of 131
Rev.1.00
MINI57 SERIES DATASHEET
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Mini57
48 MHz HIRC
HCLK
4~24 MHz HXT or
32.768 kHz LXT
1/2
11
1/2
10
CPUCLK
0
1/2
4~24 MHz HXT or
32.768 kHz LXT
00
1
SysTick
01
SYST_CTL[2]
CLK_CLKSEL0[4:3]
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-4 SysTick Clock Control Block Diagram
6.3.4
Peripherals Clock Source Selection
The peripheral clock has different clock source switch settings depending on different peripherals.
Please note that, while switching clock source from one to another, user must wait until both clock
sources are running stabled.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 90 of 131
Rev.1.00
Mini57
PCLK
Watch Dog Timer
WDTCKEN (CLK_APBCLK[0])
TMR0CKEN (CLK_APBCLK[2])
TMR1CKEN (CLK_APBCLK[3])
CLKOCKEN (CLK_APBCLK[6])
ECAPCKEN (CLK_APBCLK[8])
PGACKEN (CLK_APBCLK[12])
EPWMCKEN (CLK_APBCLK[20])
BPWMCKEN (CLK_APBCLK[16])
UART1CKEN (CLK_APBCLK[17])
USCI0CKEN (CLK_APBCLK[24])
USCI1CKEN (CLK_APBCLK[25])
ACMPCKEN (CLK_APBCLK[30])
Timer1
Frequency Divider
ECAP
PGA
EPWM
BPWM
UART1
USCI0
USCI1
ADC
MINI57 SERIES DATASHEET
ADCCKEN (CLK_APBCLK[28])
Timer0
ACMP
Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK
Apr. 06, 2017
Page 91 of 131
Rev.1.00
Mini57
Peripheral Clock Selectable
Ext. CLK
(HXT Or LXT)
HIRC
LIRC
HCLK
WDT
Yes
Yes
No
Yes
Yes
WWDT
Yes
Yes
No
Yes
Yes
Timer0
Yes
Yes
Yes
Yes
Yes
Timer1
Yes
Yes
Yes
Yes
Yes
USCI0
Yes
Yes
Yes
Yes
Yes
USCI1
Yes
Yes
Yes
Yes
Yes
ADC
Yes
Yes
Yes
No
Yes
ACMP
No
No
No
No
Yes
ECAP
No
No
No
No
Yes
EBWM
No
No
No
No
Yes
BPWM
No
No
No
No
Yes
HDIV
No
No
No
No
Yes
Table 6.3-1 Peripheral Clock Source Selection Table
Note: For the peripherals those peripheral clock are not selectable, its clock source is fixed to
PCLK.
MINI57 SERIES DATASHEET
6.3.5
Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
The clocks still kept active are listed below:
6.3.6
Clock Generator
10 kHz internal low speed oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock (If PDLXT = 1 and
XTLEN[1:0] = 10)
Peripherals Clock (When 10 kHz low speed oscillator is adopted as clock source)
Watchdog Clock
Timer 0/1 Clock
Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed of 16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
Apr. 06, 2017
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multiplexer is reflected to the CKO pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stay in low state.
if DIV1EN(CLK_CLKOCTL[5]) set to 1, the frequency divider clock will bypass power-of-2
frequency divider. The frequency divider clock will be output to CLKO pin directly.
CLKOSEL (CLK_CLKSEL1[31:30])
CLKOCKEN (CLK_APBCLK[6])
48 MHz HIRC
11
HCLK
CLKO_CLK
10
Reserved
01
4~24 MHz HXT or
32.768 kHz LXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
00
Figure 6.3-6 Clock Source of Frequency Divider
Enable
divide-by-2 counter
CLKO_CLK
1/2
1/22
FREQSEL
(CLK_CLKOCTL[3:0])
16 chained
divide-by-2 counter
1/23
…...
1/215
1/216
000
000
0
1
:
:
111
111
0
1
DIV1EN
(CLK_CLKOCTL[5])
16 to 1
MUX
0
CLKO
1
Figure 6.3-7 Block Diagram of Frequency Divider
Apr. 06, 2017
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MINI57 SERIES DATASHEET
CLKOEN
(CLK_CLKOCTL[4])
Mini57
6.4 Flash Memory Controller (FMC)
6.4.1
Overview
The Mini57 series is equipped with 29.5 Kbytes on chip embedded Flash for application program
memory (APROM) that can be updated through ISP procedure. In System Programming (ISP)
function enables user to update program memory when chip is soldered on PCB. After chip
powered on Cortex® -M0 CPU fetches code from APROM or LDROM decided by boot select
(CBS) in Config0. By the way, the Mini57 series also provides Data Flash Region, where the Data
Flash is shared with original program memory and its start address is configurable and defined by
user in Config1. The Data Flash size is defined by user depending on the application request.
Security program memory (SPROM) provides user to protect any program code within SPROM.
6.4.2
Features
Running up to 48 MHz with one wait state and 24 MHz without
discontinuous address read access
29.5 Kbytes application program memory (APROM)
2 Kbytes in system programming (ISP) loader program memory (LDROM)
Programmable Data Flash start address and memory size with 512 bytes page erase
unit
Three 512 bytes security program memory (SPROM)
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory.
wait state for
MINI57 SERIES DATASHEET
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6.5 General Purpose I/O (GPIO)
6.5.1
Overview
The Mini57 series has up to 22 General Purpose I/O pins. These pins could be shared with other
functions depending on the chip configuration. 22 pins are arranged in 4 ports named as PA, PB,
PC, and PD. Each of the 22 pins is independent and has the corresponding register bits to control
the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V.
PIN[n]
(Px_PIN)
PULLSEL[0]
(Px_PUEN)
DOUT[n]
(Px_DOUT)
PAD
MODE[n]
(Px_MODE)
MINI57 SERIES DATASHEET
PULLSEL[1]
(Px_PUEN)
Note: Px_ means PA_, PB_, PC_, or PD_
Figure 6.5-1 I/O Pin Block Diagram
6.5.2
Features
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
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6.5.3
Supports High Drive and High Sink I/O mode
Supports software selectable slew rate control
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
CIOIN = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
CIOIN = 1, all GPIO pins in input mode after chip reset
GPIOA supports the pull-up and pull-low resistor enabled in four I/O modes
GPIOB to GPIOD internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
GPIO Interrupt and Wake-up Function
Each GPIO pin can be set as chip interrupt source by setting correlative RHIEN
(Px_INTEN[n+16])/ FLIEN (Px_INTEN[n]) bit and TYPE (Px_INTTYPE[n]). There are five types of
interrupt conditions to be selected: low level trigger, high level trigger, falling edge trigger, rising
edge trigger and both rising and falling edge trigger. For edge trigger condition, user can enable
input signal de-bounce function to prevent unexpected interrupt happened which caused by noise.
The de-bounce clock source and sampling cycle period can be set through DBCLKSRC
(GPIO_DBCTL[4]) and DBCLKSEL (GPIO_DBCTL[3:0]) register.
The GPIO can also be the chip wake-up source when chip enters Idle/Power-down mode. The
setting of wake-up trigger condition is the same as GPIO interrupt trigger.
1. To ensure the I/O status before entering Idle/Power-down mode
When using toggle GPIO to wake-up system, user must make sure the I/O status before entering
Idle/Power-down mode according to the relative wake-up settings.
MINI57 SERIES DATASHEET
For example, if configuring the wake-up event occurred by I/O rising edge/high level trigger, user
must make sure the I/O status of specified pin is at low level before entering Idle/Power-down
mode; and if configuring I/O falling edge/low level trigger to trigger a wake-up event, user must
make sure the I/O status of specified pin is at high level before entering Power-down mode.
2. To disable the I/O de-bounce function before entering Idle/Power-down mode
If the specified wake-up I/O pin with enabling input signal de-bounce function, system will
encounter two GPIO interrupt events while the system is woken up by this GPIO pin. One
interrupt event is caused by wake-up function, the other is caused by I/O input de-bounce
function. User should be disable the de-bounce function before entering Idle/Power-down mode to
avoid the second interrupt event occurred after system woken up.
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6.6 Timer Controller (TIMER)
6.6.1
Overview
The Timer Controller includes two 32-bit timers, TIMER0 ~ TIMER1, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.6.2
Features
Supports two sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Supports independent clock source for each channel (TMR0_CLK, TMR1_CLK)
Supports four timer counting modes: one-shot, periodic, toggle and continuous
counting
Time-out period = (period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
CMPDAT)
Supports maximum counting cycle time = (1 / T MHz) * (28) * (224); T is the period of
timer clock
24-bit up counter value is readable through TIMERx_CNT (Timer Data Register)
Supports event counting function to count the event from external pin (TM0, TM1)
Supports internal capture triggered while internal ACMP output signal transition
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
MINI57 SERIES DATASHEET
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6.7 Enhanced Input Capture Timer (ECAP)
6.7.1
Overview
This device provides an Input Capture Timer/Counter whose capture function can detect the
digital edge-changed signal at channel inputs. This unit has three input capture channels. The
timer/counter is equipped with up counting, reload and compare-match capabilities.
6.7.2
Features
24-bit Input Capture up-counting timer/counter.
3 input channels thatl has its own capture counter hold register.
Noise filter in front end of input ports.
Edge detector with three options.
Rising edge detection.
Falling edge detection.
Both edge detection.
Supports ADC compare output and ACMP output as input sources
Captured events reset and/or reload capture counter.
Supports compare-match function.
Supports interrupt function.
MINI57 SERIES DATASHEET
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6.8 Enhanced PWM Generator (EPWM)
6.8.1
Overview
The Mini57 series has built in one PWM unit which is specially designed for motor driving control
applications. The PWM unit supports six PWM generators which can be configured as six
independent PWM outputs, PWM0~PWM5, or as three complementary PWM pairs, (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5) with three programmable dead-zone generators.
Every complementary PWM pairs share one clock divider providing nine divided frequencies (1,
1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256) for each channel. Each PWM output shares one 16bit counter for PWM period control, and 16-bit comparators for PWM duty control. The six PWM
generators provide fourteen independent PWM interrupt flags which are set by hardware when
the corresponding PWM period counter comparison matched period and duty. Each PWM
interrupt source with its corresponding enable bit can request PWM interrupt. The PWM
generators can be configured as One-shot mode to produce only one PWM cycle signal or Autoreload mode to output PWM waveform continuously.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period up counter and 16bit comparator are implemented with double buffer. When user writes data to counter/comparator
buffer registers, the updated value will be loaded into the 16-bit counter/comparator at the end of
current period. The double buffering feature avoids glitch at PWM outputs.
Besides PWM, Motor controlling also need Timer, ACMP and ADC to work together. To control
motor more precisely, some registers are provided to configure not only PWM but also Timer,
ADC and ACMP. By doing so, it can save more CPU time and control motor with ease especially
in BLDC.
6.8.2
Features
Supports one PWM clock timer and one 9 level Divider (1, 1/2, 1/4, 1/8, 1/16, 1/32,
1/64, 1/128, 1/256).
Supports six independent 16-bit PWM duty control units with maximum six port pins:
Six independent PWM outputs – PWM0, PWM1, PWM2, PWM3, PWM4, and
PWM5
Three complementary PWM pairs, with each pin in a pair mutually complement
to each other and capable of programmable dead-zone insertion – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
Three synchronous PWM pairs, with each pin in a pair in-phase – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
Supports group function.
Supports one-shot (only edge alignment mode) or auto-reload mode PWM
Supports 16-bit resolution PWM counter
Supports Edge-aligned and Center-aligned mode
Supports Programmable dead-zone insertion between complementary paired PWMs
Supports hardware fault brake protections
Apr. 06, 2017
Two Interrupt source types:
one type is brake directed, and one type can resume from brake.
fault brake source:
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MINI57 SERIES DATASHEET
Mini57
BRK0: ACMP0, ACMP1, EADC and External pin (BRAKE).
BRK1: ACMP0, ACMP1, EADC and External pin (BRAKE).
The PWM signals before polarity control stage are defined in the view of positive
logic. The PWM ports is active high or active low are controlled by polarity control
register.
Supports independently falling CMPDAT matching, central matching (in Centeraligned mode), rising CMPDAT matching (in Center-aligned mode), period matching
to trigger EADC conversion
Supports ACMP output event trigger PWM to force PWM output at most one period
low, this feature is usually for step motor control
Supports interrupt accumulation function
MINI57 SERIES DATASHEET
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6.9 Basic PWM Generator (BPWM)
6.9.1
Overview
The Mini57 series has one set of BPWM group supporting one set of PWM generator that can be
configured as 2 independent PWM outputs, BPWM CH0~BPWM CH1, or as 1 complementary
PWM pairs, (BPWM CH0, BPWM CH1) with programmable Dead-zone generators.
The PWM generator has one 8-bit pre-scalar, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-counters for
PWM period control, two 16-bit comparators for PWM duty control and one dead-zone generator.
The PWM generator provides two independent PWM interrupt flags which are set by hardware
when the corresponding PWM period down counter reaches zero. Each PWM interrupt source
with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators
can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode
to output PWM waveform continuously.
When DTCNT01(BPWM_CTL[4]) is set, BPWM CH0 and BPWM CH1 perform complementary; the
paired PWM timing, period, duty and dead-time are determined by PWM0 timer and Dead-zone
generator 0.
To prevent PWM driving output pin from glitches, the 16-bit period down counter and 16-bit
comparator are implemented with double buffer. When user writes data to counter/comparator
buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time
down counter reaching zero. The double buffering feature avoids glitch at PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWMtimer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with BPWM
Counter Register(BPWM_PERIODx, x=0,1) automatically then start decreasing, repeatedly. If the
PWM-timer is set as one-shot mode, the down counter will stop and generate one interrupt
request when it reaches zero.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
Features
One PWM generator which supports one 8-bit pre-scalar, one clock divider, two PWM
timers (down counter), one dead-zone generator and two PWM outputs.
Up to 16-bit resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode PWM
Edge-aligned type or Center-aligned type option
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MINI57 SERIES DATASHEET
6.9.2
Mini57
6.10 Watchdog Timer (WDT)
6.10.1 Overview
The Watchdog Timer is used to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer
supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for Watchdog Timer time-out interval
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval
period is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer time-out wake-up function only if WDT clock source is
selected as 10 kHz
MINI57 SERIES DATASHEET
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6.11 USCI – Universal Serial Control Interface Controller
6.11.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
Note: For detailed USCI UART, I2C and SPI information, please refer to section 6.12, 6.13 and
6.14.
6.11.2 Features
The controller can be individually configured to match the application needs. The following
protocols are supported:
UART
SPI
I2C
To increase readability, the registers of USCI have different alias names that depending on the
selected protocol. For example, register USCI_CTL has alias name UUART_CTL for protocol
UART, has alias name USPI_CTL for protocol SPI, and has alias name UI2C_CTL for protocol
I2C.
MINI57 SERIES DATASHEET
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6.12 USCI – UART Mode
6.12.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of
asynchronous data frames. It performs a serial-to-parallel conversion on data received from the
peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver
and transmitter are independent, frames can start at different points in time for transmission and
reception.
The UART controller also provides the LIN function. There is incoming data to wake up the
system.
6.12.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports programmable baud-rate generator
Supports 9-Bit Data Transfer
Supports LIN function
Supports baud rate detection by built-in capture event of baud rate generator
Supports Wake-up function
MINI57 SERIES DATASHEET
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6.13 USCI – SPI Mode
6.13.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows
full duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received
from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral
device. The SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1.
The SPI protocol can operate as master or Slave mode by setting the SLAVE
(USPI_PROTCTL[0]) to communicate with the off-chip SPI Slave or master device. The
application block diagrams in master and Slave mode are shown as Figure 6.13-1 and Figure
6.13-2.
USCI
USCI SPI
SPI Master
Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
(USCIx_DAT0)
SPI_MISO
Master Receive Data
(USCIx_DAT1)
SPI_CLK
Serial Bus Clock
(USCIx_CLK)
SPI_SS
Slave Select
(USCIx_CTL)
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_SS
Note: x = 0, 1
Figure 6.13-1 SPI Master Mode Application Block Diagram (x=0, 1)
MINI57 SERIES DATASHEET
USCI
USCI SPI
SPI Slave
Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
(USCIx_DAT0)
SPI_MISO
Slave Transmit Data
(USCIx_DAT1)
SPI_CLK
Serial Bus Clock
(USCIx_CLK)
SPI_SS
Slave Select
(USCIx_CTL)
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_SS
Note: x = 0, 1
Figure 6.13-2 SPI Slave Mode Application Block Diagram (x=0, 1)
6.13.2 Features
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Supports master or slave mode operation (the maximum frequency for Master = fPCLK /
2, for Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
MINI57 SERIES DATASHEET
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6.14 USCI – I2C Mode
6.14.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and
SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL
clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows
each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line
may be changed only during the low period of SCL and must be held stable during the high period
of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 6.14-1 for more detailed I2C BUS Timing.
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
tr
SCL
tHD_STA
tf
tHIGH
tHD_DAT
tSU_DAT
tSU_STA
tSU_STO
Figure 6.14-1 I2C Bus Timing
The device on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 0100B. When this port is enabled, the USCI interfaces to the I2C
bus via two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins
function to I2C in advance.
Note: A pull-up resistor is needed for I2C operation because the SDA and SCL are set to opendrain pins when USCI is selected to I2C operation mode.
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
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MINI57 SERIES DATASHEET
6.14.2 Features
Mini57
6.15 Hardware Divider (HDIV)
6.15.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider
is a signed, integer divider with both quotient and remainder outputs.
6.15.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
MINI57 SERIES DATASHEET
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6.16 Analog to Digital Converter (ADC)
6.16.1 Overview
The Mini57 series contains one 12-bit successive approximation analog-to-digital converter (SAR
A/D converter) with 8 single-end external input channels. The A/D converters can be started by
software, external pin (STADC/PC.1) or PWM trigger.
6.16.2 Features
Analog input voltage range: 0~VDD.
12-bit resolution and 10-bit accuracy guaranteed.
Up to 8 single-end analog input channels.
ADC clock frequency up to 16MHz.
Configurable ADC internal sampling time.
MINI57 SERIES DATASHEET
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6.17 Analog Comparator (ACMP)
6.17.1 Overview
The Mini57 series contains two comparators which can be used in a number of different
configurations. The comparator output is logic 1 when positive input greater than negative input,
otherwise the output is 0. Each comparator can be configured to generate interrupt when the
comparator output value changes.
6.17.2 Features
Analog input voltage range: 0 ~ VDD
Supports Hysteresis function
Optional internal reference voltage source for each comparator negative input
MINI57 SERIES DATASHEET
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6.18 Programmable Gain Amplifier (PGA)
6.18.1 Overview
The Mini57 series contains a programmable gain amplifier (PGA) which can be enabled through
the PGAEN bit. User can measure the outputs of the programmable gain amplifier as the
programmable gain amplifier output to the integrated A/D converter channel, where digital results
can be taken. Furthermore, user can adjust gain to 1, 2, 3, 5, 7, 9, 11, and 13.
Note: The analog input port pins must be configured as input type before the PGA function is
enabled.
6.18.2 Features
Supports analog input voltage range: 0~ VDD.
Supports programmable gain: 1,2, 3,5,7,9.11,13
Supports PGA output as input of ADC and ACMP
MINI57 SERIES DATASHEET
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7
APPLICATION CIRCUIT
DVCC
[1]
AVCC
AVDD
DVCC
Power
CS
CLK
MISO
MOSI
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
FB
VDD
VDD
SPI Device
VSS
0.1uF
0.1uF
VSS
FB
AVSS
VDD
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
DVCC
4.7K
20p
XT_IN
Crystal
4~24 MHz
or
32.768 kHz
crystal
20p
4.7K
[2]
Mini57EDE
TSSOP28
DVCC
CLK
I2Cx_SCL
I2Cx_SDA
VDD
DIO
I2C Device
VSS
XT_OUT
DVCC
Reset
Circuit
10K
RS232 Transceiver
PC COM Port
nRESET
[2]
10uF/25V
UARTx_RXD
ROUT
UARTx_TXD
TIN
RIN
TOUT
UART
MINI57 SERIES DATASHEET
LDO_CAP
1uF
Note 1: For the SPI device, the Mini57 chip
supply voltage must be equal to SPI device
working voltage. For example, when the SPI
Flash working voltage is 3.3 V, the Mini57 chip
supply voltage must also be 3.3V.
LDO
Note 2: x denotes 0 or 1.
Apr. 06, 2017
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8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD VSS
DC Power Supply
-0.3
+7.0
V
VIN
Input Voltage
VSS -0.3
VDD +0.3
V
1/tCLCL
Oscillator Frequency
4
24
TA
Operating Temperature
-40
+105
TST
Storage Temperature
-55
+150
℃
IDD
Maximum Current into VDD
-
120
mA
ISS
Maximum Current out of VSS
-
120
mA
Maximum Current sunk by an I/O pin
-
35
mA
Maximum Current sourced by an I/O pin
-
35
mA
Maximum Current sunk by total I/O pins
-
100
mA
Maximum Current sourced by total I/O pins
-
100
mA
IIO
MHz
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life
and reliability of the device.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 113 of 131
Rev.1.00
Mini57
8.2 DC Electrical Characteristics
(VDD - VSS = 2.1 ~ 5.5 V, TA = 25C)
Symbol Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 2.1V ~ 5.5V up to 48 MHz
VDD
Operation voltage
2.1
-
5.5
V
VSS / AVSS
Power Ground
-0.3
-
-
V
VLDO
LDO Output Voltage
1.5
V
VBG
Band-gap Voltage
1.2
V
IDD5
-
9.7
-
Operating Current
HCLK = 48 MHz
TA = -40C~105C
All Digital
VDD
HXT
HIRC
5.5V
X
48 MHz
V
mA
Normal Run Mode
IDD6
VDD = 3.0V ~ 5.5V,
Modules
-
7.4
-
mA
5.5V
X
48 MHz
X
-
9.7
-
mA
3V
X
48 MHz
V
-
7.4
-
mA
3V
X
48 MHz
X
VDD
HXT
HIRC
5.5V
24 MHz
X
V
while(1){}
IDD7
Executed from Flash
IDD8
IDD1
-
5.4
-
mA
Operating Current
Normal Run Mode
IDD2
HCLK = 24 MHz
All Digital
Modules
MINI57 SERIES DATASHEET
-
4.4
-
mA
5.5V
24 MHz
X
X
-
5.4
-
mA
3V
24 MHz
X
V
-
4.4
-
mA
3V
24 MHz
X
X
VDD
HXT
HIRC
5.5V
16 MHz
X
V
while(1){}
IDD3
Executed from Flash
IDD4
IDD9
-
3.7
-
mA
Operating Current
Normal Run Mode
IDD10
HCLK = 16 MHz
All Digital
Modules
-
3.0
-
mA
5.5V
16 MHz
X
X
-
3.7
-
mA
3V
16 MHz
X
V
-
3.1
-
mA
3V
16 MHz
X
X
VDD
HXT
HIRC
5.5V
12 MHz
X
while(1){}
IDD11
Executed from Flash
IDD12
Operating Current
IDD9
Normal Run Mode
-
2.8
-
mA
HCLK = 12 MHz
Apr. 06, 2017
Page 114 of 131
All Digital
Modules
V
Rev.1.00
Mini57
IDD10
while(1){}
-
2.3
-
mA
5.5V
12 MHz
X
X
IDD11
-
2.8
-
mA
3V
12 MHz
X
V
IDD12
-
2.3
-
mA
3V
12 MHz
X
X
VDD
HXT
HIRC
5.5V
4 MHz
X
V
IDD13
Executed from Flash
-
1.2
-
mA
Operating Current
Normal Run Mode
IDD14
HCLK = 4 MHz
All Digital
Modules
-
1.0
-
mA
5.5V
4 MHz
X
X
-
1.2
-
mA
3V
4 MHz
X
V
-
1.0
-
mA
3V
4 MHz
X
X
VDD
LXT
LIRC
5.5V
32 kHz
V
while(1){}
IDD15
Executed from Flash
IDD16
IDD17
-
291.7
-
μA
Operating Current
Normal Run Mode
IDD18
HCLK = 32 kHz
-
290.7
-
μA
5.5V
32 kHz
V
-
280.8
-
μA
3V
32 kHz
V
-
281.4
-
μA
3V
32 kHz
V
VDD
HXT
LIRC
5.5V
X
10 kHz
All Digital
Modules
V
[1]
X
while(1){}
IDD19
Executed from Flash
IDD20
IDD17
-
248.0
-
μA
Operating Current
IDD18
HCLK = 10 kHz
[1]
X
All Digital
Modules
V
[2]
-
247.7
-
μA
5.5V
X
10 kHz
X
-
237.9
-
μA
3V
X
10 kHz
-
237.5
-
μA
3V
X
10 kHz
VDD
HXT
HIRC
5.5V
X
V
V
while(1){}
IDD19
Executed from Flash
IDD20
IIDLE5
-
4.9
-
mA
Operating Current
IIDLE6
Idle Mode
V
[2]
X
All Digital
Modules
-
2.6
-
mA
5.5V
X
V
X
IIDLE7
-
4.9
-
mA
3V
X
V
V
IIDLE8
-
2.6
-
mA
3V
X
V
X
VDD
HXT
HIRC
5.5V
24 MHz
X
HCLK= 48 MHz
Operating Current
IIDLE1
Idle Mode
-
2.8
-
mA
HCLK = 24 MHz
Apr. 06, 2017
Page 115 of 131
All Digital
Modules
V
Rev.1.00
MINI57 SERIES DATASHEET
Normal Run Mode
V
Mini57
IIDLE2
-
1.9
-
mA
5.5V
24 MHz
X
X
IIDLE3
-
2.8
-
mA
3V
24 MHz
X
V
IIDLE4
-
1.9
-
mA
3V
24 MHz
X
X
VDD
HXT
HIRC
5.5V
V
X
V
IIDLE9
-
2.0
-
mA
Operating Current
IIDLE10
Idle Mode
All Digital
Modules
-
1.3
-
mA
5.5V
V
X
X
IIDLE11
-
2.0
-
mA
3V
V
X
V
IIDLE12
-
1.4
-
mA
3V
V
X
X
VDD
HXT
HIRC
5.5V
V
X
V
HCLK = 16 MHz
IIDLE9
-
1.5
-
mA
Operating Current
IIDLE10
Idle Mode
All Digital
Modules
-
1.0
-
mA
5.5V
V
X
X
IIDLE11
-
1.5
-
mA
3V
V
X
V
IIDLE12
-
1.0
-
mA
3V
V
X
X
VDD
HXT
HIRC
5.5V
V
X
V
HCLK = 12 MHz
IIDLE13
-
0.8
-
mA
MINI57 SERIES DATASHEET
Operating Current
IIDLE14
Idle Mode
All Digital
Modules
-
0.6
-
mA
5.5V
V
X
X
IIDLE15
-
0.7
-
mA
3V
V
X
V
IIDLE16
-
0.6
-
mA
3V
V
X
X
VDD
HXT
LIRC
5.5V
X
V
HCLK = 4 MHz
IDD17
-
274.3
-
μA
Operating Current
IDD18
Idle Mode
-
273.0
-
μA
5.5V
X
V
IDD19
-
265.0
-
μA
3V
X
V
IDD20
-
263.9
-
μA
3V
X
V
VDD
HXT
LIRC
5.5V
X
V
All Digital
Modules
V
[1]
X
HCLK = 32 kHz
Operating Current
IDD17
Idle Mode
-
232.6
-
μA
HCLK = 10 kHz
Apr. 06, 2017
Page 116 of 131
V
[1]
X
All Digital
Modules
V
[2]
Rev.1.00
Mini57
IDD18
-
232.2
-
μA
5.5V
X
V
IDD19
-
222.5
-
μA
3V
X
V
IDD20
-
222.1
-
μA
3V
X
V
-
1.9
-
A
VDD = 5.5 V, All oscillators and analog blocks
turned off.
VDD = 3 V, All oscillators and analog blocks
turned off.
IPWD1
Standby Current
X
V
[2]
X
Power-down Mode
IPWD2
(Deep Sleep Mode)
-
1.7
-
A
ILK
Input Leakage Current
PA/PB/PC/PD
-1
-
+1
A
Input Low Voltage
PA/PB/PC/PD (TTL Input)
-0.3
1.33
VIL1
VIH1
VILS
VIHS
RRST
V
-0.3
1.47
Input High Voltage
PA/PB/PC/PD (TTL Input)
Negative-going Threshold
(Schmitt Input), nRESET
Positive-going Threshold
(Schmitt Input), nRESET
Internal nRESET Pin Pullup Resistor
1
VDD = 5.5 V, 0 < VIN< VDD
Open-drain or input only mode
VDD = 5.5 V
VDD = 3.3 V
VDD + 0.3
V
VDD = 5.5 V
1.08
VDD + 0.3
-
-
0.3VDD
V
-
0.7VDD
-
-
V
-
148
kΩ
VDD = 2.1 V ~ 5.5V
48
VDD = 3.3 V
Negative-going Threshold
VILS
(Schmitt input),
PA/PB/PC/PD
-
-
0.3VDD
V
-
0.7VDD
-
-
V
-
A
VDD = 5.5 V, VIN = 0V
Positive-going Threshold
(Schmitt input),
PA/PB/PC/PD
IIL
Logic 0 Input Current
PA/PB/PC/PD (Quasibidirectional Mode)
-
-63.65
ITL
Logic 1 to 0 Transition
Current PA/PB/PC/PD
-
-566.7
-
A
VDD = 5.5 V
-
-372
-
A
VDD = 4.5 V, VIN = 2.4 V
-
-76.8
-
A
VDD = 2.7 V, VIN = 2.2 V
-
-37.3
-
A
VDD = 2.1 V, VIN = 1.8 V
-
-19.2
-
mA
VDD = 4.5 V, VIN = 2.4 V
-
-4
-
mA
VDD = 2.7 V, VIN = 2.2 V
-
-2
-
mA
VDD = 2.1 V, VIN = 1.8 V
-
12.8
-
mA
VDD = 4.5 V, VIN = 0.4 V
-
8.1
-
mA
VDD = 2.7 V, VIN = 0.4 V
ISR11
ISR12
Source Current
PA/PB/PC/PD (Quasibidirectional Mode)
ISR13
ISR21
ISR22
Source Current
PA/PB/PC/PD (Push-pull
Mode)
ISR23
ISK11
ISK12
Sink Current
PA/PB/PC/PD (Quasibidirectional, Open-Drain
Apr. 06, 2017
Page 117 of 131
MINI57 SERIES DATASHEET
VIHS
Rev.1.00
Mini57
and Push-pull Mode)
ISK13
-
6
-
mA
VDD = 2.1 V, VIN = 0.4 V
Notes:
1. Only enable modules which support 32 kHz LIRC clock source
2. Only enable modules which support 10 kHz LIRC clock source
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 118 of 131
Rev.1.00
Mini57
8.3 AC Electrical Characteristics
8.3.1
External Input Clock
tCLCL
tCLCH
0.7 VDD
90%
tCLCX
10%
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tCHCX
Clock High Time
10
-
-
ns
-
tCLCX
Clock Low Time
10
-
-
ns
-
tCLCH
Clock Rise Time
2
-
15
ns
-
tCHCL
Clock Fall Time
2
-
15
ns
-
8.3.2
External 4~24 MHz High Speed Crystal (HXT)
Symbol
Parameter
Typ.
Max
Unit
Test Conditions
VHXT
Operation Voltage
2.1
-
5.5
V
-
TA
Temperature
-40
-
105
℃
-
-
414
-
uA
IHXT
Operating Current
12 MHz, VDD = 5.5V
-
407
-
uA
12 MHz, VDD = 3.3V
4
-
24
MHz
-
fHXT
Clock Frequency
8.3.3
External 32.768 kHz XTAL Oscillator (LXT)
SPECIFICATIONS
SYM.
PARAMETER
TEST CONDITIONS
MIN.
fLXTAL
Oscillator frequency
TLXTAL
Temperature
ILXTAL
Operating current
8.3.4
TYP.
MAX.
UNIT
32.768
kHz
o
105
-40
C
A
17
VDD=2.1V
Typical Crystal Application Circuits
Crystal
C1
C2
4 MHz ~ 24 MHz
20 pF
20 pF
32.768 kHz
20 pF
20 pF
Apr. 06, 2017
Page 119 of 131
Rev.1.00
MINI57 SERIES DATASHEET
Min.
Mini57
XT_IN
XT_OUT
4~24 MHz
or
32.768 kHz
Crystal
C1
C2
Vss
Vss
Figure 8.3-1 Mini57 Typical Crystal Application Circuit
8.3.5
48 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
VHRC
fHRC
Min
Typ
Max
Unit
Test Conditions
Supply Voltage
-
1.5
-
V
-
Center Frequency
-
48
-
MHz
-
-1
-
+1
%
2
%
-
mA
TA = 25 ℃,VDD = 5 V
Unit
Test Conditions
Calibrated Internal
Oscillator Frequency
-2
IHRC
MINI57 SERIES DATASHEET
8.3.6
Operating Current
1.1
-
VDD = 5.5 V
TA = -40℃~105℃
VDD=2.1 V~ 5.5 V
10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
VLRC
Min
Typ
Max
Supply Voltage
-
1.5V
-
V
-
Center Frequency
-
10
-
kHz
-
fLRC
Oscillator Frequency
ILRC
TA = 25 ℃
Operating Current
-50
[1]
-
-
0.3
+50
[1]
0.5
%
μA
VDD = 2.1 V ~ 5.5 V
TA = -40℃ ~ +105℃
TA = 25 ℃,VDD = 5 V
Note: These parameters are characterized but not tested.
Apr. 06, 2017
Page 120 of 131
Rev.1.00
Mini57
8.4 Analog Characteristics
8.4.1
12-bit SAR ADC
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
-
Resolution
-
-
12
Bit
-
DNL
Differential Nonlinearity Error
-
2
-
LSB
VDD = 3.0~5.5 V
INL
Integral Nonlinearity Error
-
±2
-
LSB
VDD = 3.0~5.5 V
EO
Offset Error
-
±1
-
LSB
VDD = 3.0~5.5 V
EG
Gain Error (Transfer Gain)
-
-1
-
LSB
VDD = 3.0~5.5 V
EA
Absolute Error
-
±3
-
LSB
VDD = 3.0~5.5 V
-
Monotonic
-
-
FADC
ADC Clock Frequency
16
MHz
VDD = 3.0 ~5.5 V
FS
Sample Rate (FADC/TCONV)
700
kSPS
VDD = 3.0~5.5 V
Guaranteed
12
VDD = 3.0 ~5.5 V
TACQ
N+1
1/FADC
N is sampling counter,
N=1~1024
200
ns
VDD = 3.0~5.5 V
Acquisition Time (Sample Stage)
1050
ns
VDD = 3.0~5.5 V
3.0
-
5.5
V
-
Supply Current (Avg.)
-
1
-
mA
VDD = 5.5 V
VIN
Analog Input Voltage
0
-
AVDD
V
-
CIN
Input Capacitance
-
1.6
-
pF
-
RIN
Input Load
-
2.5
-
kΩ
-
Conversion Time
VDD
Supply Voltage
IDDA
MINI57 SERIES DATASHEET
1000
TCONV
Note: ADC voltage reference is same with VDD
Apr. 06, 2017
Page 121 of 131
Rev.1.00
Mini57
EF (Full scale error) = EO + EG
Gain Error
EG
Offset Error
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
ADC
output
code
5
Actual transfer curve
4
3
2
DNL
1
1 LSB
Offset Error
EO
MINI57 SERIES DATASHEET
8.4.2
4095
Analog input voltage
(LSB)
LDO & Power Management
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VDD
DC Power Supply
2.1
-
5.5
V
-
VLDO
Output Voltage
V
-
TA
Temperature
1.5
25
-40
105
℃
Note: It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the
device.
8.4.3
Low Voltage Reset
Symbol
Parameter
AVDD
Supply Voltage
2.1
-
TA
Temperature
-40
25
Apr. 06, 2017
Min
Typ
Max
Page 122 of 131
Unit
Test Condition
5.5
V
-
105
℃
-
Rev.1.00
Mini57
ILVR
Quiescent Current
VLVR
Threshold Voltage
8.4.4
Parameter
AVDD
Supply Voltage
TA
Temperature
IBOD
Quiescent Current
VBOD
TA=25℃
1.8
1.9
2.0
V
TA = -40
Min
Typ
Max
Unit
Test Condition
0
-
5.5
V
-
-40
25
105
℃
-
-
100
-
μA
AVDD =5.5V
4.33
4.3
4.39
V
BOV_VL [2:0] = 3
4.03
4.0
4.10
V
BOV_VL [2:0] = 2
3.73
3.7
3.79
V
BOV_VL [2:0] = 7
3.02
3.0
3.09
V
BOV_VL [2:0] = 1
2.72
2.7
2.79
V
BOV_VL [2:0] = 6
2.42
2.4
2.49
V
BOV_VL [2:0] = 0
2.22
2.2
2.30
V
BOV_VL [2:0] = 5
2.02
2.0
2.09
V
BOV_VL [2:0] = 4
4.3
V
BOV_VL [2:0] = 3
4.0
V
BOV_VL [2:0] = 2
3.7
V
BOV_VL [2:0] = 7
3.0
V
BOV_VL [2:0] = 1
2.7
V
BOV_VL [2:0] = 6
2.4
V
BOV_VL [2:0] = 0
2.2
V
BOV_VL [2:0] = 5
2.0
V
BOV_VL [2:0] = 4
~ +105
Brown-out Hysteresis
Brown-out Detector
Power-on Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TA
Temperature
-40
25
105
℃
-
VPOR
Threshold Voltage
1.75
V
VDD = 5.0 V
VPOR
VDD Start Voltage
Power-on Reset
to
Ensure
TBD
mV
RRVDD
VDD Raising Rate
Power-on Reset
to
Ensure
TBD
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
TBD
ms
Apr. 06, 2017
Page 123 of 131
Rev.1.00
MINI57 SERIES DATASHEET
8.4.5
μA
Brown-out Detector
Symbol
VBOD
1
Mini57
8.4.6
Comparator
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VCMP
Supply Voltage
2.1
-
5.5
V
TA
Temperature
-40
25
105
℃
-
ICMP
Operation Current
-
46
μA
VDD=3.3V
VOFF
Input Offset Voltage
±10
mV
-
VSW
Output Swing
VCOM
Input Common Mode Range
-
DC Gain
TPGD
0
-
VDD
V
-
0.1
-
AVDD – 0.1
V
-
-
60
-
dB
-
Propagation Delay
-
225
-
ns
VHYS
Hysteresis
-
10
-
mV
ACMPPHYSEN = 01
VHYS
Hysteresis
-
90
-
mV
ACMPPHYSEN = 10
TSTB
Stable time
-
1.06
-
μs
Typ
Max
[1]
Note: Guaranteed by design, not test in production.
8.4.7
Symbol
PGA
Parameter
Min
Operation voltage range
2.5
3.3
Operating Current
MINI57 SERIES DATASHEET
Operating Temperature
-40
25
Input Offset with calibration
Type
temp=25,VCM=AVDD/2
Unit
5.5
V
5
mA
Test Condition
VDD=5V, T=125℃
125
+2
mV
1
uV/
corner,
Input Offset Average Drift
Output Swing
0.1
VDD - 0.1
V
PGA gain accuracy
-1
+1
%
Input Common Mode Range
0
VDD - 1.5
V
DC Gain
50
Unity Gain Frequency
7
Phase Margin
50°
PSRR+
49
90
dB
VDD = 5V
CMRR
69
90
dB
VDD = 5V
Apr. 06, 2017
80
dB
8.2
MHz
VDD = 5V
°
Page 124 of 131
Rev.1.00
Mini57
Slew Rate+
6.0
7.5
V/us
VDD=5V, RLoad=1.3K,
CLoad=100p
Wake Up Time
20
us
Note: Guaranteed by design, not test in production.
MINI57 SERIES DATASHEET
Apr. 06, 2017
Page 125 of 131
Rev.1.00
Mini57
8.5 Flash DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Supply Voltage
1.35
1.5
1.65
V
NENDUR
Endurance
100,000
-
-
cycles
TRET
Data Retention
20
-
-
year
TERASE
Sector Erase Time
-
5
ms
TPROG
Program Time
-
-
7.5
us
IDD1
Read Current
-
3
4.5
mA
IDD2
Program Current
-
-
4
mA
IDD3
Erase Current
-
-
2
mA
V
[2]
FLA
Test Condition
[1]
TA =125℃
@33 MHz
Notes:
1.
Number of program/erase cycles.
2.
VFLA is source from chip LDO output voltage.
Guaranteed by design, not test in production.
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9
PACKAGE DIMENSIONS
9.1 28-Pin TSSOP (4.4x9.7x1.0 mm)
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Mini57
9.2 20-Pin TSSOP (4.4x6.5x0.9 mm)
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Mini57
9.3 33-pin QFN33 (4x4x0.8 mm)
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Mini57
10 REVISION HISTORY
Date
Revision
Description
2017.04.06
1.00
Preliminary version.
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Page 130 of 131
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Mini57
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Apr. 06, 2017
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Important Notice
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