TH58BVG2S3HBAI4
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4 GBIT (512M
2
8 BIT) CMOS NAND E PROM
DESCRIPTION
The TH58BVG2S3HBAI4 is a single 3.3V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048 64) bytes 64 pages 4096 blocks.
The device has a 2112-byte static register which allows program and read data to be transferred between the
register and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block
unit (128 Kbytes 4 Kbytes: 2112 bytes 64 pages).
The TH58BVG2S3HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TH58BVG2S3HBAI4 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
x8
2112 128K 8 x 2
2112 8
2112 bytes
(128K 4K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 4016 blocks
Max 4096 blocks
Power supply
VCC 2.7V to 3.6V
Access time
Cell array to register 40 s typ. (Single Page Read) / 55us typ. (Multi Page Read)
Serial Read Cycle
25 ns min (CL=50pF)
Program/Erase time
Auto Page Program
Auto Block Erase
330 s/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
100 A max
Package
P-TFBGA63-0911-0.80CZ
(Weight: 0.154 g typ.)
8bit ECC for each 528Byte is implemented on the chip.
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TH58BVG2S3HBAI4
PIN ASSIGNMENT (TOP VIEW)
1
2
A
NC
NC
B
NC
3
C
4
ALE
D
NC
E
NC
F
5
6
7
8
9
10
NC
NC
NC
NC
VSS
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G
NC
NC
NC
NC
NC
NC
H
NC
I/O1
NC
NC
NC
VCC
J
NC
I/O2
NC
VCC
I/O6
I/O8
K
VSS
I/O3
I/O4
I/O5
I/O7
VSS
L
NC
NC
NC
NC
M
NC
NC
NC
NC
PIN NAMES
I/O1 to I/O8
I/O port
Chip enable
Write enable
Read enable
CLE
Command latch enable
ALE
Address latch enable
Write protect
Ready/Busy
VCC
Power supply
VSS
Ground
NC
No Connection
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TH58BVG2S3HBAI4
BLOCK DIAGRAM
ECC Logic
Data register 1
VCC VSS
Status register
Address register
I/O1
Column buffer
I/O
Control circuit
to
Column decoder
I/O8
Command register
Data register 0
Sense amp
CLE
ALE
Logic control
Control circuit
Memory cell array
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
VCC
Power Supply Voltage
0.6 to 4.6
V
VIN
Input Voltage
0.6 to 4.6
V
VI/O
Input /Output Voltage
PD
Power Dissipation
0.3
W
TSOLDER
Soldering Temperature (10 s)
260
°C
TSTG
Storage Temperature
55 to 150
°C
TOPR
Operating Temperature
-40 to 85
°C
CAPACITANCE *(Ta
SYMB0L
0.6 to VCC
25°C, f
V
1 MHz)
PARAMETER
CONDITION
CIN
Input
VIN
COUT
Output
VOUT
*
0.3 ( 4.6 V)
0V
0V
MIN
MAX
UNIT
20
pF
20
pF
This parameter is periodically sampled and is not tested for every device.
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VALID BLOCKS
SYMBOL
NVB
PARAMETER
MIN
Number of Valid Blocks
NOTE:
TYP.
4016
MAX
UNIT
4096
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
VCC
Power Supply Voltage
VIH
High Level input Voltage
Vcc x 0.8
VIL
Low Level Input Voltage
0.3*
TYP.
2.7
MAX
UNIT
3.6
V
VCC
0.3
V
Vcc x 0.2
V
2 V (pulse width lower than 20 ns)
*
DC CHARACTERISTICS (Ta
SYMBOL
-40 to 85 , VCC
PARAMETER
2.7 to 3.6V)
CONDITION
MIN
TYP.
UNIT
20
A
20
A
30
mA
IIL
Input Leakage Current
VIN
ILO
Output Leakage Current
VOUT
ICCO1
Serial Read Current
ICCO2
Programming Current
30
mA
ICCO3
Erasing Current
30
mA
ICCS
Standby Current
100
A
VOH
High Level Output Voltage
IOH
VOL
Low Level Output Voltage
IOL
0.1 mA
Output current of
pin
VOL
0.2 V
IOL
(
)
0 V to VCC
MAX
0 V to VCC
VIL, IOUT
VCC
0 mA, tcycle
0.2 V,
0.1 mA
25 ns
0 V/VCC,
Vcc
V
0.2
0.2
4
4
V
mA
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TH58BVG2S3HBAI4
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
-40 to 85 , VCC
2.7 to 3.6V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCLS
CLE Setup Time
12
ns
tCLH
CLE Hold Time
5
ns
20
ns
tCS
tCH
Setup Time
5
ns
tWP
Write Pulse Width
Hold Time
12
ns
tALS
ALE Setup Time
12
ns
tALH
ALE Hold Time
5
ns
tDS
Data Setup Time
12
ns
tDH
Data Hold Time
5
ns
tWC
Write Cycle Time
25
ns
tWH
High Hold Time
10
ns
tWW
High to
Low
100
ns
tRR
Ready to
Falling Edge
20
ns
tRW
Ready to
Falling Edge
20
ns
tRP
Read Pulse Width
12
ns
tRC
Read Cycle Time
25
ns
tREA
Access Time
20
ns
tCEA
Access Time
25
ns
tCLR
CLE Low to
Low
tAR
ALE Low to
Low
10
ns
10
ns
tRHOH
High to Output Hold Time
25
ns
tRLOH
Low to Output Hold Time
5
ns
tRHZ
High to Output High Impedance
60
ns
tCHZ
High to Output High Impedance
20
ns
tCSD
High to ALE or CLE Don t Care
0
ns
tREH
High Hold Time
10
ns
0
ns
30
ns
30
ns
60
ns
tIR
Output-High-impedance-to-
tRHW
High to
tWHC
High to
tWHR
High to
tWB
High to Busy
tRST
Falling Edge
Low
Low
Low
Device Reset Time (Ready/Read/Program/Erase)
100
ns
5/5/10/500
s
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
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TH58BVG2S3HBAI4
AC TEST CONDITIONS
CONDITION
PARAMETER
VCC: 2.7 to 3.6V
Input level
Vcc-0.2V, 0.2V
Input pulse rise and fall time
3 ns
Input comparison level
Vcc / 2
Output data comparison level
Vcc / 2
Output load
Note:
CL (50 pF)
Busy to ready time depends on the pull-up resistor tied to the
(Refer to Application Note (9) toward the end of this document.)
1 TTL
pin.
PROGRAMMING / ERASING / READING CHARACTERISTICS
(Ta
-40 to 85 , VCC
2.7 to 3.6V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
Average Programming Time (Single Page)
330
700
s
Average Programming Time (Multi Page)
350
700
s
tDCBSYW1
Busy Time in Multi Page Program(following 11h)
0.5
1
s
N
Number of Partial Program Cycles in the Same Page
tBERASE
Block Erasing Time
2.5
5
Memory Cell Array to Starting Address (Sigle Page)
40
120
Memory Cell Array to Starting Address (Multi Page)
55
200
NOTES
tPROG
tR
4
(1)
ms
s
(1) Refer to Application Note (12) toward the end of this document.
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
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TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
Setup Time
Hold Time
tDS
tDH
I/O
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
tCLS
tCS
tCLH
tCH
tWP
tALS
tALH
ALE
tDS
tDH
I/O
: VIH or VIL
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Address Input Cycle Timing Diagram
tCLS
tCLH
CLE
tCH
tCS
tWP
tCS
tWH
tWP
tWC
tWH
tWP
tWC
tWH
tWP
tCH
tWH
tWP
tALS
tALH
ALE
tDS
I/O
tDH
tDS
CA0 to 7
tDS
tDH
CA8 to 11
tDH
tDS
PA0 to 7
tDH
PA8 to 15
tDS
tDH
PA16 to 17
: VIH or VIL
Data Input Cycle Timing Diagram
tCLS
tCLH
CLE
tCH
tCS
tCS
tCH
tALS
tALH
tWC
ALE
tWP
tWH
tDS
tWP
tDH
tDS
DIN0
I/O
tWP
tDH
DIN1
tDS
tDH
DIN2111
.
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TH58BVG2S3HBAI4
Serial Read Cycle Timing Diagram
tRC
tRP
tREA
tREH
tRHZ
tRHOH
tRP
tCHZ
tRP
tRHZ
tRHZ
tRHOH
tREA
tREA
tCEA
tRHOH
tCEA
I/O
tRR
: VIH or VIL
Status Read Cycle Timing Diagram
tCLR
CLE
tCLS
tCLH
tCS
tWP
tCH
tCEA
tCHZ
tWHC
tWHR
tDS
tDH
tRHOH
tIR
tREA
I/O
tRHZ
Status
output
70h/71h*
: VIH or VIL
*: 70h/71h represents the hexadecimal number
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TH58BVG2S3HBAI4
ECC Status Read Cycle Timing Diagram
tCLR
CLE
tCLS
tCLH
tCS
tWP
tCH
tCEA
tWHC
tWHR
tDS
tDH
tIR
tREA
I/O
7Ah*
tREA
tREA
tREA
Status
output
Status
output
Status
output
Status
output
Sector1
Sector2
Sector3
Sector4
: VIH or VIL
*: ECC Status output should be read for all 4 sector information.
**: 7Ah command can be inputted to the device from [ after RY/BY returns to High ] to [before Dout or Next command input].
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TH58BVG2S3HBAI4
Read Cycle Timing Diagram
tCLR
CLE
tCLS tCLH
tCS
tCLS
tCH
tCLR
tCLH
tCS
tCH
tWC
tALH tALS
tALH tALS
ALE
tRC
tR
tWB
tDS tDH
I/O
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
00h
CA8
to 11
PA0
to 7
PA8
to 15
tDS tDH
PA16
to 17
tREA
70h
30h
tREA
status
output
00h
DOUT
N
Data out from
Col. Add. N
Col. Add. N
Read Cycle Timing Diagram: When Interrupted by
tCLR
tCLR
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tCLH
tCH
tWC
tALH
tCSD
tALS
tALH
tALS
ALE
tR
tRC
tWB
tDS tDH
I/O
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
PA16
to 17
Col. Add. N
tDS tDH
30h
tCHZ
tRHZ
tREA
tREA
70h
tRHOH
status
output
00h
DOUT
N
DOUT
N+1
Col. Add. N
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TH58BVG2S3HBAI4
Column Address Change in Read Cycle Timing Diagram (1/2)
tCLR
tCLR
CLE
tCLS tCLH
tCS
tCLS tCLH
tCH
tCH
tCS
tWC
tALH tALS
tALH
tALS
ALE
tR
tRC
tWB
I/O
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
00h
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
PA16
to 17
30h
tREA
70h
Status
Output
00h
DOUT DOUT
A
A 1
DOUT
A N
Page address
P
Page address
P
Column address
A
1
Continues to 1
12
of next page
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TH58BVG2S3HBAI4
Column Address Change in Read Cycle Timing Diagram (2/2)
tCLR
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tRHW
tCLH
tCH
tWC
tCEA
tALH tALS
tALH
tALS
ALE
tWHR
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tRC
tREA
tIR
DOUT
A N
I/O
05h
CA0
to 7
CA8
to 11
E0h
Column address
B
DOUT
B
DOUT
B 1
DOUT
B
Page address
P
Column address
B
1
Continues from 1 of previous page
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TH58BVG2S3HBAI4
Data Output Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
tALH
ALE
tRC
tRP
tCHZ
tREH
tREA
tCEA
Dout
tRR
tRHZ
tREA
tRLOH
tREA
I/O
tRP
tRP
tDS tDH
tRLOH
Dout
tRHOH
Dout
Command
tRHOH
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TH58BVG2S3HBAI4
Auto-Program Operation Timing Diagram
tCLS
CLE
tCLS tCLH
tCS
tCS
tCH
tALH
tALH
tALS
tPROG
tWB
tALS
tRW
ALE
I/O
tDS
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
tDH
tDH
CA8
to 11
PA0
to 7
PA8 PA16
to 15 to 17
DINN
DIN
N+1
DINM*
10h
70h
Status
output
Column address
N
: Do not input data while data is being output.
: VIH or VIL
*) M: up to 2111
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Multi-Page Program Operation Timing Diagram (1/2)
tCLS
CLE
tCLS tCLH
tCS
tCS
tCH
tALH
tALH
tALS
tDCBSYW1
tWB
tALS
ALE
I/O
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
tDS
tDH
CA8
to 11
PA0
to 7
PA8
to 15
PA16
to 17
DINN
tDH
DIN
N+1
Page Address M
District-0
11h
81h
CA0
to 7
DIN2111
: Do not input data while data is being output.
: VIH or VIL
1
Continues to 1 of next page
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TH58BVG2S3HBAI4
Multi-Page Program Operation Timing Diagram (2/2)
tCLS
CLE
tCLS tCLH
tCS
tCS
tCH
tALH
tALH
tALS
tPROG
tWB
tALS
ALE
tDS tDH
81h
CA0
to 7
I/O
tDS
tDS
tDS tDH
tDH
tDH
CA8
to 11
PA0
PA8 PA16
to 7
to 15 to 17
Page Address M
District-1
DINN
DIN
N+1
10h
71h
DIN2111
: Do not input data while data is being output.
: VIH or VIL
1
Continues from
1 of previous page
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2014-03-15C
Status
output
TH58BVG2S3HBAI4
Auto Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
tALH
tALS
tWB
tBERASE
ALE
tDS tDH
I/O
60h
Auto Block
Erase Setup
command
: VIH or VIL
PA0
to 7
PA8
to 15
PA16
to 17
D0h
Erase Start
command
Status
output
70h
Busy
Status Read
command
: Do not input data while data is being output.
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TH58BVG2S3HBAI4
Multi Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
tALH
tALS
tWB
tBERASE
ALE
tDS tDH
I/O
60h
PA0
to 7
PA8
to 15
PA16
to 17
Auto Block
Erase Setup
command
D0h
Erase Start
command
71h
Busy
Status
output
Status Read
command
Repeat 2 times (District-0,1)
: VIH or VIL
: Do not input data while data is being output.
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ID Read Operation Timing Diagram
tCLS
CLE
tCLS
tCS
tCS
tCH
tCEA
tCH
tALH
tALH
tALS
tAR
ALE
tDH
tDS
I/O
tREA
tREA
tREA
tREA
tREA
90h
00h
98h
DCh
See
Table 5
See
Table 5
See
Table 5
ID Read
command
Address
00
Maker code
Device code
3rd Data
4th Data
5th Data
: VIH or VIL
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TH58BVG2S3HBAI4
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of
while ALE is High.
Chip Enable:
The device goes into a low-power Standby mode when
signal is ignored when device is in Busy state (
operation, and will not enter Standby mode even if the
goes High during the device is in Ready state. The
L), such as during a Program or Erase or Read
input goes High.
Write Enable:
The
signal is used to control the acquisition of data from the I/O port.
Read Enable:
The
signal controls serial data output. Data is available t REA after the falling edge of
.
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect:
The
signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when
is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
The
output signal is used to indicate the operating condition of the device. The
signal is
in Busy state (
= L) during the Program, Erase and Read operations and will return to Ready state
(
= H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
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Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
Data Cache
2048
64
Page Buffer
2048
64
I/O8
A page consists of 2112 bytes in which 2048 bytes are
used for main memory storage and 64 bytes are for
redundancy or for other uses.
1 page 2112bytes
1 block 2112 bytes 64 pages (128K 4K) bytes
Capacity 2112 bytes 64pages 4096 blocks
64 Pages 1 block
262144
pages
4096 blocks
An address is read in via the I/O port over five
consecutive clock cycles, as shown in Table 1.
8I/O
2112
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
L
L
L
L
CA11
CA10
CA9
CA8
Third cycle
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth cycle
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
L
L
L
L
L
L
PA17
PA16
First cycle
Second cycle
Fifth cycle
23
CA0 to CA11: Column address
PA0 to PA17: Page address
PA6 to PA17: Block address
PA0 to PA5: NAND address in block
2014-03-15C
TH58BVG2S3HBAI4
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE,
,
,
and
signals, as shown in Table 2.
Table 2. Logic Table
*1
CLE
ALE
Command Input
H
L
L
H
*
Data Input
L
L
L
H
H
Address input
L
H
L
H
*
Serial Data Output
L
L
L
H
During Program (Busy)
*
*
*
*
*
H
During Erase (Busy)
*
*
*
*
*
H
*
*
H
*
*
*
*
*
L
H (*2)
H (*2)
*
Program, Erase Inhibit
*
*
*
*
*
L
Standby
*
*
H
*
*
0 V/VCC
*
During Read (Busy)
H: VIH, L: VIL, *: VIH or VIL
*1: Refer to Application Note (10) toward the end of this document regarding the
signal when Program or Erase Inhibit
is low during read busy,
and
must be held High to avoid unintended command/address input to the device or
*2: If
read to device. Reset or Status Read command can be input during Read Busy.
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TH58BVG2S3HBAI4
Table 3. Command table (HEX)
First Set
Second Set
Serial Data Input
80
Read
00
30
Column Address Change in Serial Data Output
05
E0
Auto Page Program
80
10
Column Address Change in Serial Data Input
85
80
11
81
10
Read for Copy-Back without Data Out
00
35
Copy-Back Program without Data Out
85
10
Auto Block Erase
60
D0
ID Read
90
Status Read
70
Status Read for Multi-Page Program or Multi Block Erase
71
ECC Status Read
7A
Reset
FF
Acceptable while Busy
Multi Page Program
HEX data bit assignment
(Example)
Serial Data Input: 80h
1
0
0
0
0
0
0
8
7
6
5
4
3
2 I/O1
0
Table 4. Read mode operation states
CLE
ALE
Output select
L
L
L
H
Output Deselect
L
L
L
H
I/O1 to I/O8
Power
L
Data output
Active
H
High impedance
Active
H: VIH, L: VIL
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TH58BVG2S3HBAI4
DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and 30h commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. After initial power on sequence, 00h
command is latched into the internal command register. Therefore read operation after power on sequence is
executed by the setting of only five address cycles and 30h command. Refer to the figures below for the
sequence and the block diagram (Refer to the detailed timing chart.).
CLE
ALE
Column Address M
I/O
Busy
Page Address N
00h
30h
tR
70h
Status
00h
M
A data transfer operation from the cell array to the Data
in the
Cache via Page Buffer starts on the rising edge of
30h command input cycle (after the address information has
been latched). The device will be in the Busy state during this
transfer period.
After the transfer period, the device returns to Ready state.
clock
Serial data can be output synchronously with the
from the start address designated in the address input cycle.
m
Page Buffer
Select page
N
Cell array
2111
I/O1 to 8: m
M+2
Page Address N
Start-address input
Data Cache
M+1
M
Random Column Address Change in Read Cycle
CLE
ALE
Busy t
R
Col. M
I/O
30h
00h
Col. M
Page N
M
M 1 M 2 M 3
Page N
Start from Col. M
Start-address input
M
70h Status 00h
E0h
05h
Col. M
M
M 1 M 2 M 3 M 4
Page N
Start from Col. M
During the serial data output from the register, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
page.
M
Select page
N
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TH58BVG2S3HBAI4
Multi Page Read Operation
The device has a Multi Page Read operation.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command
input
(3 cycle)
60
Address input
(3 cycle)
60
Page Address
PA0 to PA17
(District 0)
A
0
Address input
30
Page Address
PA0 to PA17
(District 1)
Command
input
(5 cycle)
00
Address input
70
I/O1
1
Fail
tR
A
(2 cycle)
05
Column + Page Address
CA0 to CA11, PA0 to PA17
(District 0)
Address input
E0
Column Address
CA0 to CA11
(District 0)
Data output
B
(District 0)
B
A
B
A
Pass
Command
input
(5 cycle)
00
Address input
05
Column + Page Address
CA0 to CA11, PA0 to PA17
(District 1)
Address input
E0
Column Address
CA0 to CA11
(District 1)
Data output
(District 1)
B
District 0
District 1
Reading
Selected
page
Selected
page
The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
in the 30h command input cycle (after the 2 Districts address information has been
edge of
latched). The device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state. Serial data can be output synchronously
clock from the start address designated in the address input cycle.
with the
ECC Status command can be used only for Single Page Read. It is not supported for Multi Page Read
operation.
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TH58BVG2S3HBAI4
Internal addressing in relation with the Districts
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
The device consists from 2 Districts.
Each District consists of 1024 erase blocks.
The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(c) District 0: Block 2048, Block 2050, Block 2052,···, Block 4094
(d) District 1: Block 2049, Block 2051, Block 2053,···, Block 4095
Combination of (a) and (b) or (c) and (d) can only be selected.
Address input restriction for the Multi Page Read operation
There are following restrictions in using Multi Page Read;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Page Read operation
Make sure
is held to High level when Multi Page Read operation is performed
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ECC & Sector definition for ECC
Internal ECC logic generates Error Correction Code during busy time in program operation. The ECC logic
manages 9bit error detection and 8bit error correction in each 528Bytes of main data and spare data. A section
of main field (512Bytes) and spare field (16Bytes) are paired for ECC. During read, the device executes ECC of
itself. Once read operation is executed, Read Status Command (70h) can be issued to check the read status. The
read status remains until other valid commands are executed.
To use ECC function, below limitation must be considered.
- A sector is the minimum unit for program operation and the number of program per page must not exceed 4.
2KByte Page Assignment
1 st
2 nd
3 rd
4 th
1 st
2 nd
3 rd
4 th
Main
Main
Main
Main
Spare
Spare
Spare
Spare
512B
512B
512B
512B
16B
16B
16B
16B
Note) The Internal ECC manages all data of Main area and Spare area
Definition of 528Byte Sector
Sector
Column Address (Byte)
Main Field
Spare Field
1 st Sector
0 ~ 511
2,048 ~ 2,063
2 nd Sector
512 ~ 1,023
2,064 ~ 2,079
3 rd Sector
1,024 ~ 1,535
2,080 ~ 2,095
4 th Sector
1,536 ~ 2,047
2,096 ~ 2,111
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TH58BVG2S3HBAI4
Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
CLE
ALE
Din Din Din
80h
I/O
Col. M
Page P
Din
70h
10h
Status
Out
Data
Data input
Program
The data is transferred (programmed) from the Data Cache via
the Page Buffer to the selected page on the rising edge of
following input of the 10h command. After programming, the
programmed data is transferred back to the Page Buffer to be
automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in
the device is reached.
Read& verification
Selected
page
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto Page Program
operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input. After
the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.
80h
Din
Col. M
Din
Din
Din
85h
Din
Col. M
Page N
Col. M
Din
Din
Din
10h
70h
Status
Busy
Col. M
Data input
Program
Reading & verification
Selected
page
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TH58BVG2S3HBAI4
Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto
Page Program. The sequence of command, address and data input is shown below. (Refer to the detailed timing
chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page by 70h command
when the program operation completes. Status bit of I/O 1 is set to 1 when any of the pages fails. Limitation in
addressing with Multi Page Program is shown below.
Multi Page Program
tPROG
tDCBSYW1
I/O1~8
0
80h
Address & Data Input
CA0~CA11
PA0~PA5
PA6
PA7~PA17
81h
11h
Address & Data Input
Note
: Valid
: Valid
: District0
: Valid
CA0~CA11
PA0~PA5
PA6
PA7~PA17
10h
: Valid
: Valid
: District1
: Valid
70h/71h
Pass
I/O1
1
Fail
NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.
80h
11h
81h
10h
Data
Input
Plane 0
(1024 Block)
Plane 1
(1024 Block)
Block 0
Block 1
Block 2
Block 3
Block 2044
Block 2045
Block 2046
Block 2047
The 71h command Status description is as below.
STATUS
OUTPUT
I/O1
Chip Status : Pass/Fail
Pass: 0
Fail: 1
I/O2
District 0 Chip Status : Pass/Fail
Pass: 0
Fail: 1
I/O3
District 1 Chip Status : Pass/Fail
Pass: 0
Fail: 1
I/O4
Not Used
Invalid
I/O5
Not Used
Invalid
I/O6
Ready/Busy
Ready: 1
Busy: 0
I/O7
Ready/Busy
Ready: 1
Busy: 0
I/O8
Write Protect
Protect: 0
I/O1 describes Pass/Fail condition of
district 0 and 1(OR data of I/O2 and I/O3).
If one of the districts fails during multi
page program operation, it shows Fail .
I/O2 to 3 shows the Pass/Fail condition of
each district..
Not Protect: 1
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Internal addressing in relation with the Districts
To use Multi Page Program operation, the internal addressing should be considered in relation with the
District.
The device consists of 2 Districts.
Each District consists from 1024 erase blocks.
The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(c) District 0: Block 2048, Block 2050, Block 2052,···, Block 4094
(d) District 1: Block 2049, Block 2051, Block 2053,···, Block 4095
Combination of (a) and (b) or (c) and (d) can only be selected.
Address input restriction for the Multi Page Program operation
There are following restrictions in using Multi Page Program;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x00040] (10)
(80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x00041] (10)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(80) [District 0] (11) (81) [District 1] (10)
(80) [District 1] (11) (81) [District 0] (10)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Page Program operation
(Restriction)
The operation has to be terminated with 10h command.
Once the operation is started, no commands other than the commands shown in the timing diagram is allowed
to be input except for Status Read command and reset command.
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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of
after the Erase Start command D0h which
follows the Erase Setup command 60h . This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
60
D0
Block Address
input: 3 cycles
70
Status Read
command
Erase Start
command
I/O
Pass
Fail
Busy
Multi Block Erase
The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below
diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by
checking the status by 71h status read command. For details on 71h status read command, refer to section
Multi Page Program .
60
Block Address
input: 3 cycles
District 0
60
D0
71
Status Read
command
Block Address Erase Start
input: 3 cycles command
District 1
I/O
Pass
Fail
Busy
Internal addressing in relation with the Districts
To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.
The device consists from 2 Districts.
Each District consists from 1024 erase blocks.
The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(c) District 0: Block 2048, Block 2050, Block 2052,···, Block 4094
(d) District 1: Block 2049, Block 2051, Block 2053,···, Block 4095
Combination of (a) and (b) or (c) and (d) can only be selected.
Address input restriction for the Multi Block Erase
There are following restrictions in using Multi Block Erase.
(Restriction)
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual address relation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h
command input, input the FFh reset command to terminate the operation.
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READ FOR COPY-BACK WITH DATA OUTPUT TIMING GUIDE
Copy-Back operation is a sequence execution of Read for Copy-Back and of copy-back program with the
destination page address. A read operation with 35h command and the address of source page moves the
whole 2112 bytes data into the internal data buffer. Bit errors are checked by sequential reading the data or by
reading the status in read after read busy time(tR) to check if uncorrectable error occurs. In the case where
there is no bit error or no uncorrectable error, the data don t need to be reloaded. Therefore Copy-Back program
operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual
programming operation begins after Program Confirm command (10h) is issued. Once the program process
starts, the Read Status Register command (70h) may be entered to read the status register. The system
controller can detect the completion of a program cycle by monitoring the
output, or the Status Bit
(I/O7) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit (I/O1) may be
checked. The command register remains in Read Status command mode until another valid command is written
to the command register. During copy-Back program, data modification is possible using random data input
command (85h) as shown below.
Page Copy-Back Program Operation
tR
tPROG
0
I/Ox
00h
Add.(5Cycle
)
35h
70h
Col. Add.1,2 & Page
Add.1,2,3
0
I/O1
1
Data Output
00h
85h
Pass
Add.(5Cycle
)
10h
70h
Col. Add.1,2 & Page
Add.1,2,3
Fail
I/O1
Pass
1
Fail
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
Page Copy-Back Program Operation with Random Data Input
tR
A
0
I/Ox
00h Add.(5Cycles)
35h
70h
I/O1
Col. Add.1,2 & Page Add.1,2,3
Source Address
1
00h
Data Output
Fail
tPROG
A
I/Ox
A
A
Pass
85h Add.(5Cycles)
Data
Col. Add.1,2 & Page Add.1,2,3
Destination Address
85h Add.(2Cycles)
Data
10h
70h
Col. Add.1,2
There is no limitation for the number of repetition
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ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
CLE
tCEA
tAR
ALE
tREA
I/O
90h
00h
98h
DCh
See
table 5
See
table 5
See
table 5
ID Read
command
Address 00
Maker code
Device code
3rd Data
4th Data
5th Data
Table 5. Code table
Description
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
1st Data
Maker Code
1
0
0
1
1
0
0
0
98h
2nd Data
Device Code
1
1
0
1
1
1
0
0
DCh
3rd Data
Chip Number, Cell Type
1
0
0
1
0
0
0
1
91h
4th Data
Page Size, Block Size
0
0
0
1
0
1
0
1
15h
5th Data
Plane Number
1
1
1
1
0
1
1
0
F6h
3rd Data
Description
Internal Chip Number
Cell Type
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
4
8
2 level cell
4 level cell
8 level cell
16 level cell
0
0
1
1
Reserved
1
35
0
0
I/O2
I/O1
0
0
1
1
0
1
0
1
0
1
0
1
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TH58BVG2S3HBAI4
4th Data
Description
Page Size
(without redundant area)
1 KB
2 KB
4 KB
8 KB
Block Size
(without redundant area)
64 KB
128 KB
256 KB
512 KB
I/O Width
I/O8
I/O7
I/O6
0
0
1
1
x8
x16
I/O5
I/O4
I/O3
I/O2
I/O1
0
0
1
1
0
1
0
1
I/O2
I/O1
1
0
0
1
0
1
0
1
Reserved
0
0
1
I/O4
I/O3
0
0
1
1
0
1
0
1
5th Data
Description
Plane Number
ECC engine on chip
I/O8
I/O7
I/O6
I/O5
1 Plane
2 Plane
4 Plane
8 Plane
With ECC engine
1
Reserved
1
36
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2014-03-15C
TH58BVG2S3HBAI4
Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using
after a 70h command input. The Status Read can also be used during a
Read operation to find out the Ready/Busy status.
The resulting information is outlined in Table 6.
Table 6. Status output table
Definition
Page Program
Block Erase
Read
Pass/Fail
Pass/Fail
Pass/Fail(Uncorrectable)
I/O1
Chip Status
Pass: 0
I/O2
Not Used
Invalid
Invalid
Invalid
I/O3
Not Used
0
0
0
0
0
Normal or uncorrectable /
Recommended to rewrite
0
0
0
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Write Protect
Write Protect
Write Protect
Fail: 1
Chip Read Status
I/O4
Normal or uncorrectable: 0
Recommended to rewrite : 1
I/O5
Not Used
I/O6
Ready/Busy
Ready: 1
Busy: 0
I/O7
Ready/Busy
Ready: 1
Busy: 0
I/O8
Write Protect
Not Protected :1
Protected: 0
The Pass/Fail status on I/O1 is only valid during a Program/Erase operation when the device is in the Ready state.
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ECC Status Read
The ECC Status Read function is used to monitor the Error Correction Status. 24nm BENAND can correct up
to 8bit errors.
ECC can be performed on the NAND Flash main and spare areas. The ECC Status Read function can also
show the number of errors in a sector as a result of an ECC check in during a read operation.
8
7
6
Sector Information
5
4
3
2
I/O1
ECC Status
ECC Status
I/O4 to I/O1
ECC Status
0000
No Error
0001
1bit error(Correctable)
0010
2bit error(Correctable)
0011
3bit error(Correctable)
0100
4bit error(Correctable)
0101
5bit error(Correctable)
0110
6bit error(Correctable)
0111
7bit error(Correctable)
1000
8bit error(Correctable)
1111
Uncorrectable Error
I/O8 to I/O5
Sector Information
0000
1st Sector (Main and Spare area)
0001
2nd Sector (Main and Spare area)
0010
3rd Sector (Main and Spare area)
0011
4th Sector (Main and Spare area)
Other
Reserved
Sector Information
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Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
Reset during a Page Copy may not just stop the most recent page program but it may also stop the previous
program to a page depending on when the FF reset is input.
The response to a FFh Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
80
10
FF
00
Internal VPP
tRST (max 10 s)
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TH58BVG2S3HBAI4
When a Reset (FFh) command is input during erasing
D0
FF
00
Internal erase
voltage
tRST (max 500 s)
When a Reset (FFh) command is input during Read operation
00
30
FF
00
tRST (max 5 s)
When a Reset (FFh) command is input during Ready
FF
00
tRST (max 5 s)
When a Status Read command (70h) is input after a Reset
FF
70
I/O status: Pass/Fail
Pass
: Ready/Busy
Ready
When two or more Reset commands are input in succession
10
The second
FF
(1)
(2)
(3)
FF
FF
FF
command is invalid, but the third
40
FF
command is valid.
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TH58BVG2S3HBAI4
APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The
signal is useful for protecting against data corruption at power-on/off.
2.7 V
2.5 V
0 V
,
1ms
VCC
2.7 V
2.5 V
0.5 V
0.5 V
Don t
care
Don t
care
,
CLE, ALE
Don t
care
VIH
VIL
VIL
1.2 ms max
Operation
100 s max
100 s max
Invalid
Invalid
1.2 ms max
Invalid
Ready/Busy
(2)
Power-on Reset
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
(3)
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4)
Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h,71h and FFh.
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(5)
Acceptable commands after Serial Input command 80h
Once the Serial Input command 80h has been input, do not input any command other than the Column
Address Change in Serial Data Input command 85h , Auto Program command 10h , Multi Page Program
command 11h or the Reset command FFh .
80
FF
Address input
If a command other than 85h , 10h , 11h or FFh is input, the Program operation is not performed
and the device operation is set to the mode which the input command specifies.
80
XX
Mode specified by the command.
10
Programming cannot be executed.
Command other than
85h , 10h , 11h or FFh
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
DATA IN: Data (1)
Ex.) Random page program (Prohibition)
Data (64)
DATA IN: Data (1)
Data register
Data (64)
Data register
Page 0
Page 1
Page 2
(1)
(2)
(3)
Page 0
Page 1
Page 2
(2)
(32)
(3)
Page 31
(32)
Page 31
(1)
Page 63
(64)
Page 63
(64)
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(7)
Status Read during a Read operation
00
Command
00
30
[A]
70
Address N
Status Read
command input
Status output
Status Read
.
The device status can be read out by inputting the Status Read command 70h in Read mode. Once the
device has been set to Status Read mode by a 70h command, the device will not return to Read mode
unless the Read command 00h is inputted during [A]. If the Read command 00h is inputted during [A],
Status Read mode is reset, and the device returns to Read mode. In this case, data output starts
automatically from address N and address input is unnecessary
(8)
Auto programming failure
80
10
70
Fail
I/O
80
Address Data
M
input
10
Address Data
N
input
80
If the programming result for page address M is Fail, do not try to program the
page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
command, address and data is necessary.
10
M
N
(9)
: termination for the Ready/Busy pin (
)
A pull-up resistor needs to be used for termination because the
circuit.
VCC
VCC
Ready
buffer consists of an open drain
VCC
R
Busy
Device
tr
tf
CL
VSS
1.5
tr
This data may vary from device to device.
We recommend that you use this data as a
reference when selecting a resistor value.
1.0
0.5
s
tf
s
1 K
3.3 V
25°C
50 pF
15 ns
10 ns
tr
s
0
VCC
Ta
CL
tf
5 ns
2 K
3 K
4 K
R
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(10)
Note regarding the
signal
The Erase and Program operations are automatically reset when
enabled and disabled as follows:
goes Low. The operations are
Enable Programming
DIN
80
10
tWW (100 ns MIN)
Disable Programming
DIN
80
10
tWW (100 ns MIN)
Enable Erasing
DIN
60
D0
tWW (100 ns MIN)
Disable Erasing
DIN
60
D0
tWW (100 ns MIN)
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(11)
When six address cycles are input
Although the device may read in a sixth address, it is ignored inside the chip.
Read operation
CLE
ALE
I/O
00h
30h
Ignored
Address input
Program operation
CLE
ALE
I/O
80h
Ignored
Address input
45
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(12)
Several programming cycles on the same page (Partial Page Program)
Each segment can be programmed individually as follows:
1st programming
2nd programming
All 1 s
Data Pattern 2
All 1 s
4th programming
Result
All 1 s
Data Pattern 1
Data Pattern 1
Data Pattern 2
46
All 1 s
Data Pattern 4
Data Pattern 4
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(13)
Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Bad Block
Bad Block
Please do not perform an erase operation to bad blocks. It may be
impossible to recover the bad block information if the information is
erased.
Check if the device has any bad blocks after installation into the system.
Refer to the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the bit lines by select gates.
The number of valid blocks over the device lifetime is as follows:
MIN
Valid (Good) Block Number
4016
TYP.
MAX
UNIT
4096
Block
Bad Block Test Flow
Regarding invalid blocks, bad block mark is in whole pages.
Please read one column of any page in each block. If the data of the column is 00 (Hex), define the block as a bad
block
Start
Block No
1
Fail
Read Check
Pass
Block No.
Block No.
No
1
Entry Bad Block *1
Last Block
Yes
End
*1:
No erase operation is allowed to detected bad blocks
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(14)
Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
DETECTION AND COUNTERMEASURE SEQUENCE
Block
Erase Failure
Status Read after Erase
Page
Programming Failure
Status Read after Program
Read
9bit Failure(uncorrectable error)
Uncorrectable ECC error
Block Replacement
Block Replacement
ECC: Error Correction Code. 8 bit correction per 528Bytes is executed in a device.
Block Replacement
Program
Error occurs
Buffer
memory
Block A
When an error happens in Block A, try to reprogram the
data into another Block (Block B) by loading from an
external buffer. Then, prevent further system accesses
to Block A ( by creating a bad block table or by using
another appropriate scheme).
Block B
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(15)
Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
(16)
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two
plane operations.
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Package Dimensions
Weight: 0.154 g (typ.)
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Revision History
Date
2013-02-15
2014-03-15
Rev.
0.10
1.00
Description
Preliminary version
Deleted TENTATIVE notation. Clarification for the Package Weight.
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RESTRICTIONS ON PRODUCT USE
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in this document, and related hardware, software and systems (collectively "Product") without notice.
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TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
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own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
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