GD9Fx1GxF2A
GD9Fx1GxF2A
DATASHEET
1
GD9Fx1GxF2A
Contents
1.
FEATURES ........................................................................................................................................................ 4
2.
GENERAL DESCRIPTION ............................................................................................................................... 5
2.1 PRODUCT LIST ............................................................................................................................................ 5
3.
PACKAGE .......................................................................................................................................................... 6
3.1 TSOPI-48 .................................................................................................................................................. 6
3.2 FBGA-63 ................................................................................................................................................... 6
4.
BLOCK DIAGRAM ............................................................................................................................................ 7
4.1 PIN DESCRIPTION ................................................................................................................................... 8
5.
ARRAY ORGANIZATION ................................................................................................................................. 9
5.1 ADDRESSING (X8) ....................................................................................................................................... 9
5.2 ADDRESSING (X16) ..................................................................................................................................... 9
5.3 FACTORY DEFECT MAPPING....................................................................................................................... 10
5.3.1. Device Requirements ................................................................................................................................. 10
5.3.2. Host Requirements ..................................................................................................................................... 11
6.
COMMAND SET .............................................................................................................................................. 12
7.
BUS OPERATION ........................................................................................................................................... 13
7.1 COMMAND INPUT CYCLE ............................................................................................................................ 14
7.2 ADDRESS INPUT CYCLE ............................................................................................................................. 14
7.3 DATA INPUT CYCLE.................................................................................................................................... 15
7.4 DATA OUTPUT CYCLE ................................................................................................................................ 15
7.5 W RITE PROTECT ....................................................................................................................................... 16
8.
OPERATION DESCRIPTION ......................................................................................................................... 17
8.1 PAGE READ OPERATION ............................................................................................................................ 17
8.1.1 Common Page Read (00H-30H) ............................................................................................................... 17
8.1.2 Random Data Output (05H-E0H) .............................................................................................................. 18
8.1.3 Cache Read Operation (31H/3FH) ............................................................................................................ 18
8.2 PAGE PROGRAM OPERATION ..................................................................................................................... 20
8.2.1 Common Page Program (80H-10H).......................................................................................................... 20
8.2.2 Page Program Operation with Random Data Input (85H-10H)............................................................. 21
8.2.3 Page Re-program (8BH-10H) .................................................................................................................... 21
8.2.4 Cache Program Operation (80H-15H) ...................................................................................................... 22
8.2.5 Copy-Back Program with Random Data Input (00H-35H) ..................................................................... 24
8.3 BLOCK ERASE OPERATION (60H-D0H) ...................................................................................................... 25
8.4 RESET (FFH) ............................................................................................................................................ 25
8.5 READ DEVICE INFORMATION....................................................................................................................... 26
8.5.1 Read ID and ONFI Signature (90H) .......................................................................................................... 26
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GD9Fx1GxF2A
8.5.2 Read Unique ID (EDH) ................................................................................................................................ 30
8.5.3 Read Parameter Page (ECH) .................................................................................................................... 31
8.6 READ STATUS (70H) ................................................................................................................................. 36
8.7 READY/BUSY# (R/B#) ............................................................................................................................... 38
8.8 DATA PROTECTION & POWER ON/OFF SEQUENCE ....................................................................................... 39
ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 40
9.
10.
VALID BLOCKS .......................................................................................................................................... 41
11.
DC CHARACTERISTICS............................................................................................................................ 42
12.
AC CHARACTERISTICS............................................................................................................................ 43
12.1 TEST CONDITION ..................................................................................................................................... 43
12.2 CAPACITANCE (TA=25°C, F=1.0MHZ) ..................................................................................................... 43
12.3 AC TIMING CHARACTERISTICS ................................................................................................................. 44
12.4 PERFORMANCE CHARACTERISTICS ........................................................................................................... 45
13.
PACKAGE INFORMATION ........................................................................................................................ 46
13.1 TSOPI-48 .............................................................................................................................................. 46
13.2 FBGA-63 ............................................................................................................................................... 48
14.
PART NUMBERING INFORMATION ........................................................................................................ 50
15.
REVISION HISTORY................................................................................................................................... 51
3
GD9Fx1GxF2A
1. FEATURES
◆Single
level cell technology
◆Number
of Valid Blocks
- Min 1004 blocks
◆ONFI
1.0 Compatible
◆Power
- Max 1024 blocks
Supply Voltage
◆Operating
Current
- VCC/VCCQ = 1.7 ~ 1.95v(GD9FS)
- Read(25ns cycle): 15mA
- VCC/VCCQ = 2.7 ~ 3.6v (GD9FU)
- Program(Typ): 15mA
- Erase(Typ): 15mA
◆Memory
Cell Organization
- Standby(Max):50uA (CMOS)
- Page size:
X8: 2K + 128bytes
◆Reliability
X16: 1K + 64words
- P/E cycles with ECC: 100K
- Block size:
- Data retention: 10 Years
X8: 128K + 8K bytes
X16: 64K + 4K words
◆ECC
- Plane size: 1024 blocks
Requirement
- 4bit/512 bytes
- Device size: 1024 blocks
◆Operating
◆Page
Read / Program time
Temperature
- Industrial (I): -40C ~ 85C
- Random Read Time (tR): 25us Max.
- Industrial (J): -40C ~ 105C
- Sequential Access Time
3.3v Device: 25ns Min.
◆Chip
1.8v Device:45ns Min.
◆Security
- Page Program(tPROG): 300us Typ.
Enable Don’t Care Option
- OTP area
- Non-volatile protection
◆Block
Erase
◆Package
- Block Erase Time(tBERS): 3ms Typ.
- TSOPI 48 12mm x 20mm
- FBGA63
4
GD9Fx1GxF2A
2. GENERAL DESCRIPTION
GigaDevice GD9Fx1G8F2A and GD9Fx1G6F2A are 1Gbit with spare 64Mbit capacity. A program operation can be
performed in typical tPROG on the 2176-byte page and an erase operation can be performed in typical tBERS on a
128K+8K-bytes block. Data in the data page can be read out at tRC cycle time per byte. The I/O pins serve as the ports
for address and data input/output as well as command input. The on-chip write controller automates all program and erase
functions including pulse repetition, where required, and internal verification and margining of data. GD9Fx1G8F2A and
GD9Fx1G6F2A′s provide extended reliability of 100K program/erase cycles with ECC (Error Correcting Code).
2.1 Product List
PART NUMBER
ORGANIZATION
VCC RANGE
PACKAGE
GD9FU1G8F2AMG
128M x 8bit
2.7v ~ 3.6v
TSOP(I)-48
GD9FU1G6F2AMG
64M x 16bit
2.7v ~ 3.6v
TSOP(I)-48
GD9FU1G8F2ALG
128M x 8bit
2.7v ~ 3.6v
FBGA-63
GD9FU1G6F2ALG
64M x 16bit
2.7v ~ 3.6v
FBGA-63
GD9FS1G8F2AMG
128M x 8bit
1.7v ~ 1.95v
TSOP(I)-48
GD9FS1G6F2AMG
64M x 16bit
1.7v ~ 1.95v
TSOP(I)-48
GD9FS1G8F2ALG
128M x 8bit
1.7v ~ 1.95v
FBGA-63
GD9FS1G6F2ALG
64M x 16bit
1.7v ~ 1.95v
FBGA-63
5
GD9Fx1GxF2A
3. PACKAGE
3.1 TSOPI-48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GD9Fx1G8F2A
NC
NC
NC
NC
NC
NC
NC
NC
IO7
NC
IO6
NC
IO5
R/B#
IO4
RE#
NC
CE#
NC
NC
NC
NC
VCC
VCC
VSS
VSS
NC
NC
NC
NC
NC
CLE
IO3
ALE
IO2
WE#
IO1
WP#
IO0
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 1-a: GD9Fx1G8F2AMG package figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GD9Fx1G6F2A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
NC
NC
VCC
VSS
NC
NC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
VSS
Figure 1-b: GD9Fx1G6F2AMG package figures
3.2 FBGA-63
1
2
A
NC
NC
B
NC
3
4
5
6
7
8
9
10
NC
NC
NC
NC
1
2
A
NC
NC
B
NC
3
4
5
6
7
8
C
WP#
ALE
VSS
CE#
WE#
R/B#
C
WP#
ALE
VSS
CE#
WE#
R/B#
D
NC
RE#
CLE
NC
NC
NC
D
NC
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
NC
VCC
NC
IO13
IO15
NC
G
NC
VCC
NC
NC
NC
NC
H
IO8
IO0
IO10
IO12
IO14
VCC
H
NC
IO0
NC
NC
NC
VCC
J
IO9
IO1
IO11
VCC
IO5
IO7
J
NC
IO1
NC
VCC
IO5
IO7
IO4
IO6
VSS
IO4
IO6
VSS
VSS
K
IO2
IO3
VSS
K
IO2
IO3
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
M
NC
NC
NC
NC
GD9Fx1G6F2A
GD9Fx1G8F2A
Figure 2_a: 63-FBGA x16 device ball location figures
Figure 2_b: 63-FBGA x8 device ball location figures
6
GD9Fx1GxF2A
4. BLOCK DIAGRAM
Vcc
Vss
Status register
to
Column buffer
Address register
I/O0
I/O
Control circuit
I/O7
I/O15
Column decoder
Data register
Command register
Row address buffer
CE#
CLE
ALE
Logic control
Control circuit
WE#
RE#
WP#
RY /BY#
RY /BY#
HV generator
Figure 3: Block Diagram figures
7
Row address decoder
Sense amp
Memory cell array
GD9Fx1GxF2A
4.1 PIN DESCRIPTION
Signal Name
Input/ Output
Description
R/B#
O
Ready/Busy：Open drain output to indicate the target status, low to indicate that
one or more operations are in progress.
RE#
I
Read Enable：Enables serial data output, active low.
CE#
I
Chip Enable：When high and the target is in the ready state, the target goes into
a low-power standby state. When low, the target is selected.
CLE
I
Command Latch Enable：Enable signal to load a command into the target on
the rising edge of WE#, active high.
ALE
I
Address Latch Enable：Enable signal to load an address into the target on the
rising edge of WE#, active high.
WE#
I
Write Enable：Data, Commands, and Addresses are latched on the rising edge
of WE#.
WP#
I
Write Protect：Low to disable Flash array program and erase operations.
IO0 ~ IO7
I/O
I/O Port, bits 0-7：8-bit wide bidirectional port for transferring address, command,
and data to and from the device.
IO8 ~ IO15
I/O
I/O Port, bits 8-15：Upper 8 bits for the 16-bit wide bidirectional port used to
transfer data to and from the device.
VCC
I
Power：Power supply to the device.
VSS
I
Ground：Power supply ground.
NC
-
No Connection：Lead is not internally connected.
VCC
VCC
CE#
CE#
IO0~IO7
IO0~IO15
WE#
RE#
ALE
WE#
Organization
X8
RE#
ALE
R/B#
Organization
X16
R/B#
CLE
CLE
WP#
WP#
VSS
VSS
Figure 4_a: GD9Fx1G8F2A figures
Figure 4_b: GD9Fx1G6F2A figures
8
GD9Fx1GxF2A
5. ARRAY ORGANIZATION
Each device has
Each block has
Each page has
1G
128M+8M
128K+8K
2K+128
bytes
1024 x 64
64
-
pages
1024
-
-
blocks
Cache Register
2048
128
Data Register
2048
128
IO
1 page = (2K + 128 bytes)
1 block = (2K + 128 bytes) x 64 pages
= (128K + 8K) bytes
Per device:
1G: 1024 Blocks
1 device:
For 1G: = (128K +8K) bytes x 1024 blocks
= 1Gb
1 block
Figure 5: Array Organization figures
5.1 Addressing (X8)
Bus Cycle
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1 Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
A11
L
L
L
L
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
4th Cycle
A20
A21
A22
A23
A24
A25
A26
A27
st
A0-A11: column address in the page
A12-A17: page address in the block
A18-A27: block address
5.2 Addressing (X16)
Bus Cycle
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
L
L
L
L
L
3rd Cycle
A11
A12
A13
A14
A15
A16
A17
A18
4th Cycle
A19
A20
A21
A22
A23
A24
A25
A26
A0-A10: column address in the page
A11-A16: page address in the block
A17-A26: block address
9
GD9Fx1GxF2A
5.3 Factory Defect Mapping
The Flash array is not presumed to be pristine, and a number of defects that makes the blocks unusable may be present.
Invalid blocks shall be sorted out from normal blocks by software.
5.3.1. Device Requirements
If a block is defective, the manufacturer shall mark the block as defective by setting the Defective Block Marking, as
shown in Figure of “Area marked in first or last page of block indicating defect”, of the last page of the defective block to a
value of non‐FFh. The Defective Block Marking is located on the first byte of user data area or the first byte of spare data
area in the pages within a block.
Defective Block Marking
1st page 0 1 2
The 1st byte of spare region
Last
page
0 1 2
The 1st byte of spare region
Figure 6. Area marked in first or last page of block indicating defect sequential figures
10
GD9Fx1GxF2A
5.3.2. Host Requirements
The host shall not erase or program blocks marked as defective by the manufacturer, and any attempt to do so yields
indeterminate results.
Figure of “Flow chart to create initial invalid block table” outlines the flow chart how to create an initial invalid block table. It
should be performed by the host to create the initial bad block table prior to performing any erase or programming
operations on the target. The 1st byte of both main and spare region in non‐defective blocks are read FFh with ECC
enabled on the controller. A defective block is indicated by the majority of bits being read non‐FFh in the Defective Block
Marking location of either the first page or last page of the block. The host shall check the Defective Block Marking location
of both the first and last past page of each block to verify the block is valid prior to any erase or program operations on that
block.
NOTE: Over the lifetime use of a NAND device, the Defective Block Marking of defective blocks may encounter read
disturbs that cause bit changes. The initial defect marks by the manufacturer may change value over the lifetime of the
device, and are expected to be read by the host and used to create a bad block table during initial use of the part.
Start
Accessing the 1st block
Check FFh at
1st byte of both main and spare data
of the first page
No
Check FFh at
1st byte of both main and spare data
of the last page
No
Accessing next block
Yes
No
Update a Bad Block table
Last Block
Yes
End
Figure 7: flow chart to create initial invalid block table sequential figures
11
GD9Fx1GxF2A
6.
COMMAND SET
Function
1st
2nd
3rd
4th
During busy
Page read
00H
30H
--
--
no
Read for copy-back
00H
35H
--
--
no
Random data output
05H
E0H
--
--
no
Cache read start
31H
--
--
--
no
Cache read random
00H
31H
--
--
no
Cache read end
3FH
--
--
--
no
Read id
90H
--
--
--
no
Read status register
70H
--
--
--
yes
Page program start / Cache program end
80H
10H
--
--
no
Random data input
85H
--
--
--
no
Copy back program
85H
10H
--
--
no
Cache program start
80H
15H
--
--
no
Block erase
60H
D0H
--
--
no
Reset
FFH
--
--
--
yes
Page re-program
8BH
10H
--
--
no
Read parameter page
ECH
--
--
--
no
Read unique ID
EDH
--
--
--
no
12
GD9Fx1GxF2A
7. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data
Output, Write Protect, and Standby. Typically glitches less than 5ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
CLE
ALE
CE#
WE#
RE#
WP#
MODE
H
L
L
Rising
H
X
Command input for read mode
L
H
L
Rising
H
X
Address input (4 cycles) for read mode
H
L
L
Rising
H
H
Command input for write mode
L
H
L
Rising
H
H
Address input (4 cycles) for write cycle
L
L
L
Rising
H
H
Data input
L
L
L
H
Falling
X
Sequential read and data output
L
L
L
H
H
X
During read(busy)
X
X
X
X
X
H
During program/Erase(busy)
X
X
X
X
X
L
Write protect
X
X
H
X
X
0V / VCC
Standby
Notes:
1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to avert
unintended data out. In this time, only Reset and Read Status can be input to the device.
13
GD9Fx1GxF2A
7.1 Command Input Cycle
Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be
high.
CLE
tCLS
tCLH
tCS
tCH
CE#
tWP
WE#
tALS
tALH
ALE
tDH
Command
IO0-7
R/B#
tWB
Figure 8: Command Input Cycle figures
7.2 Address Input Cycle
Address Input bus operation allows the insertion of the memory address. Addresses are accepted with Chip Enable low,
Address Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write
Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high.
CLE
tCLH
tCLS
tCS
tCH
tWC
CE#
WE#
tWP
tALS
tWH
tALH
ALE
tDS tDH
I/Ox
Col. Add1
Col. Add2
Figure 9: Address Input Cycle figures
14
Row Add1
Row Add2
GD9Fx1GxF2A
7.3 Data Input Cycle
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed
by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch
Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable.
tCLS
tCLH
CLE
tCH
tCS
tCH
CE#
tALS
tALH
tWC
ALE
tWP
tWH
WE#
tDS
tDH
DIN0
I/Ox
DIN1
DINn
Figure 10: Data Input Cycle figures
7.4 Data Output Cycle
Data Output bus operation allows to output data from the device. The data output cycle is serially and timed by the Read
Enable cycles. Data output may be used with CE# don’t care. However, if CE# don’t care is used tCEA and tCOH timing
requirements shall be met by the host.
tCHZ
tCEA
CE#
tCOH
tRP
RE#
tRHOH
tREH
tRR
R/B#
I/Ox
tRHZ
tRC
tREA
tRHZ
DOUT 0
DOUT 1
Figure 11_a: Data Output Cycle figures
15
DOUT n
GD9Fx1GxF2A
If the host side uses a sequential access time (tRC) of less than 30ns, the data can be latched on the next falling edge of
RE# as the waveform of EDO (Extended data output)mode.
tCHZ
CE#
tCOH
tRP
RE#
tRR
tREH
tRC
R/B#
tREA
tRLOH
DOUT 0
I/Ox
tRHZ
tRHOH
DOUT1
DOUT n
tCEA
Figure 11_b: Data Output Cycle figures
7.5 Write Protect
The Erase and Program Operations are automatically reset when WP# goes Low. The operations are enabled and disabled as follows.
WE#
WE#
tWW
tWW
I/Ox
80h
I/Ox
10h
WP#
WP#
R/B#
R/B#
Figure 12_a: Write Protect Disable with program figures
80h
10h
Figure 12_b: Write Protect Enable with program figures
WE#
WE#
tWW
tWW
I/Ox
60h
I/Ox
D0h
60h
D0h
WP#
WP#
R/B#
R/B#
Figure 12_c: Write Protect Disable with erase figures
Figure 12_d: Write Protect Enable with erase figures
16
GD9Fx1GxF2A
8. OPERATION DESCRIPTION
8.1 Page Read Operation
8.1.1 Common Page Read (00H-30H)
Read is initiated by writing 00H-30H to the command register along with four address cycles. After initial power up, 00h
command is latched, and the first page of the first block has been read to cache, ready for random read out. Therefore only
4 address cycles and 30H command initiates that operation after initial power up. The 2176 bytes of data within the selected
page are transferred to the data registers. The system controller can detect the completion of this data transfer (tR) by
analyzing the output of R/B# pin. Once the data in a page is loaded into the data registers, they may be read out in tRC by
sequentially pulsing RE#. The repetitive high to low transitions of the RE# clock make the device output the data starting
from the selected column address up to the last column address.
After the last data has been read out, CE# may be pulled up for some time to end the read operation, while during the RE#
toggle cycle, CE# may be don't care when RE# is high. The CE# Don’t Care feature may simplify the system interface,
which allows controller to directly download the code from flash device, and the CE# transitions will not stop the read
operation during the latency time.
tCS
CE#
tCS
CLE
tCLS
tCH
tCH
tCLR
tCLH
tCLS
tCLH
tWC
WE#
tALS
ALE
tCHZ
tRC
RE#
tCEA
tRR
tWB
tDS tDH
I/Ox
00h
tR
Col. Add1
Col. Add2
Row Add1
Row Add2
30h
tREA
DOUT
DOUT
N
N+1
Data out from
Col.Add .N
Col.Add.N
RY/BY#
Figure 13: Common Page Read figures
17
GD9Fx1GxF2A
8.1.2 Random Data Output (05H-E0H)
The device may output random data in a page instead of the consecutive sequential data by writing random data output
command (05H-E0H). The column address of next data, which is going to be out, may be changed to the address which
follows random data output command. Random data output can be operated multiple times regardless of how many times
it is done in a page Change Read Column shall only be issued when the device is in a read idle condition.
CE#
CLE
tCLR
WE#
tWB
tRHW
tAR
tWHR
ALE
tR
tRC
tREA
RE#
00h
I/Ox
Col.
Col.
Row.
Row.
Add1
Add2
Add1
Add2
30h
tRR
Dout
Dout
N
N+1
Col.
05h
Col.
Add1 Add2
E0h
Dout
Dout
M
M+1
Column Address
R/B#
Busy
Figure 14: Random Data Output figures
8.1.3 Cache Read Operation (31H/3FH)
The Cache Read function permits a page to be read from the page register while another page is simultaneously read from
the Flash array. A Read Page command shall be issued prior to the initial sequential or random Read Cache command in
a read cache sequence. A Read Cache command shall be issued prior to a Read Cache End (3FH) command being issued.
The Cache Read function may be issued after the Read function is complete. The host may enter the address of the next
page to be read from the Flash array. Data output always begins at column address 00H. If the host does not enter an
address to retrieve, the next sequential page is read, when the Read Cache function is issued. After the operation is begun
R/B# is set to one (ready) and the host may begin to read the data from the previous Read or Read Cache function. Issuing
an additional Read Cache function copies the data most recently read from the array into the page register. When no more
pages are to be read, the final page is copied into the page register by issuing the 3FH command.
The host may begin to read data from the page register when R/B# is set to one (ready). When the 31H and 3FH commands
are issued, R/B# shall be cleared to zero (busy) until the page has finished being copied from the Flash array.
18
GD9Fx1GxF2A
A
CE#
CLE
tWC
ALE
WE#
tRC
tWB
tWB
RE#
I/Ox
00h
RB#
Col.
Col.
Row.
Row.
Row.
Add1
Add2
Add1
Add2
Add3
30h
tRR
31h
Column Address Page Address N
00h
Dout
Dout0 Dout1
tR
tCBSYR
①
②
Page Address N
③
A
CE#
CLE
ALE
WE#
tWB
tWC
tWB
RE#
tRR
Dout
I/Ox
31h
tCBSYR
Dout
Page
Buffer
②
③
④
Page N
Page N + 1
Dout
0
1
N
3Fh
Dout0
tCBSYR
Page Address
N+2
⑧
⑦
Page N+1
⑤
⑥
Page N + 1
Dout1
Page Address
N+3
: Don't care
Page N+2
⑧
Page N + 2
Page N + 3
⑦
Page N + 2
Page N + 3
Figure 15: Cache Read Operation figures
Note:
C1-C2 : Column address of the page to retrieve. C1 is the least significant byte.
R1-R2 : Row address of the page to retrieve. R1 is the least significant byte.
D0-Dn : Data bytes/words read from page requested by the original Read or the previous cache operation.
19
⑨
Page N+3
⑨
⑦
⑤
③
Page N
Dout
⑥
Page N
①
tRR
Dout
tCBSYR
⑤
①
Cell
Array
31h
Page Address
N+1
④
Data
Cache
tRC
tRR
Dout0 Dout1
RB#
tWB
tRC
GD9Fx1GxF2A
8.2 Page Program Operation
8.2.1 Common Page Program (80H-10H)
The device is programmed basically on a page basis, but it does allow multiple partial pages programming of a word or
consecutive bytes up to 2,112 in a single page program cycle. The number of consecutive partial page programming
operation within the same page without an intervening erase operation must not exceed 4 times for main array
(1time/512byte) and 4 times for spare array (1time/16byte). The addressing must be done in sequential order in a block. A
page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data
register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle address
inputs and then serial data loading. The words other than those to be programmed do not need to be loaded.
The Page Program Confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process. The internal write state controller automatically executes
the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once
the program process starts, the Read Status Register command may be issued to read the status register.
The command register remains in Read Status command mode until another valid command is written to the command
register.
CE#
CLE
tCS
tCLS
ALE
WE#
tWB
tWC
RE#
tDStDH
Col.
I/Ox
tWHR
80h
Col. Row. Row.
Add1 Add2 Add1 Add2
Din
Din
Din
N
N+1
M
10h
70h
Status
tPROG
R/B#
IO 0 = 0, pass
IO 0 = 1, fail
:Don't care
Figure 16: Common Page Program figures
20
GD9Fx1GxF2A
8.2.2 Page Program Operation with Random Data Input (85H-10H)
The device supports random data input in a page. The column address of next data, which will be entered, may be changed
to the address which follows random data input command (85H). Random data input may be operated multiple times
regardless of how many times it is done in a page.
CE#
CLE
tCS
tCLS
ALE
tWC
WE#
tADL
tWHR
RE#
tDS tCH
I/Ox
80h
Col. Col. Row. Row. Din Din
Add1Add2Add1 Add2
N
N+1
Din
M
85h
Col. Col. Din
Add1 Add2
J
Din
Din
J+1
K
10h
70h
Status
tPROG
R/B#
IO 0 = 0, pass
:Don't care
IO 0 = 1, fail
Figure 17: Page Program Operation with Random Data Input figures
8.2.3 Page Re-program (8BH-10H)
It was also highlighted that page program may result in a fail, which can be detected by Read Status Register. In this event,
it implements the innovative feature of “page re-program”. This command allows the re-programming of the same pattern
of the (failed) page into another memory location. The command sequence initiates with re-program setup (8BH), followed
by the four cycle address inputs of the target page. If the target pattern for the destination page is not changed compared
to the page, the program confirm can be issued (10H) without any data input cycle.
On the other hand, if the pattern bound for the target page is different from that of the previous page, data in cycles can be
issued before program confirm “10H”
21
GD9Fx1GxF2A
As defined for
Page
Program
Cycle Type
A
CMD ADDR ADDR ADDR ADDR
DIN
DIN
DIN
DIN
CMD
D0
D1
…
Dn
10h
CMD DOUT
tADL
I/Ox
80H
C1
C2
R1
R2
70h
E1
tWB
SR[6]
tPROG
Page N
Fail !
A
Cycle Type
CMD ADDR ADDR ADDR ADDR
DIN
DIN
DIN
DIN
CMD
D0
D1
…
Dn
10h
tADL
I/Ox
8BH
C1
C2
R1
R2
tWB
SR[6]
tPROG
Page M
Optional
Figure 18: Page Re-program figures
8.2.4 Cache Program Operation (80H-15H)
Cache Program is an extension of Page Program, which is executed with one page data registers, and is available only
within a block. Since the device has one page of cache memory, serial data input may be executed while data stored in
data register are programmed into memory cell.
After writing the first set of data up to one page into the selected cache registers, Cache Program command (15H) instead
of actual Page Program (10H) is inputted to make cache registers free and to start internal program operation. To transfer
data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSYW) and has
its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data
registers. Read Status command (70H) may be issued to find out when cache registers become ready by polling the CacheBusy status bit (I/O 6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next
set of data is loaded with the Cache Program command, tCBSYW is affected by the progress of pending internal
programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the
data registers are available for the transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may
be polled to identify the completion of internal programming. If the system monitors the progress of programming only with
R/B#, the last page of the target programming sequence must be programmed with actual Page Program command (10H).
22
GD9Fx1GxF2A
CLE
tCLS tCLH
tCS
tCLS
tCH
CE#
WE#
tALH
tALH
tALS
tCBSYW
tWB
tALS
ALE
RE#
tDS tDH
80h
I/O
tDS tDH
Col
Col
Row
Row
Addr1
Addr2
Addr1
Addr2
DINN
DIN
N+1
15h
80h
CA0
DIN2111
RY/BY#
:Do not input data while data is being output
:VIH or VIL
1
Continues to
CLE
1 of next page
tCLS
tCLS tCLH
tCS
tCS
CE#
tCH
WE#
tALH
tALH tALS
tALS
tWB
ALE
RE#
80h
I/O
tDS
tDS tDH
tDStDH
Col
Col
Row
Row
Addr1
Addr2
Addr1
Addr2
DINN
DIN
N+1
10h
DIN4223
tDH
70h
Status
tPROG
RY/BY#
1
:Do not input data while data is being output
:VIH or VIL
Figure 19: Cache Program Operation figures
23
GD9Fx1GxF2A
8.2.5 Copy-Back Program with Random Data Input (00H-35H)
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external
memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is
improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block is also needed
to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution
of page-read without serial access and copying-program with the address of destination page. A read operation with
“35h”command and the address of the source page moves the wholepage bytes data into the internal data buffer. As soon
as the device returns to Ready state, optional data read-out is allowed by toggling RE#, or Copy Back command (85H) with
the address cycles of destination page may be written. The Program Confirm command (10H) is required to actually begin
the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed. When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back
operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction
scheme. Please note that Random Data Input (with/without data) is entered before Program Confirm command (10H) after
Random Data output.
CE#
CLE
ALE
tWC
WE#
tWB
tRC
I/Ox
R/B#
tRHW
tRR
RE#
00h
Col. Col. Row. Row.
Add1Add2Add1 Add2
35h
tWC
tWB
tADL
tCS tCH
Dout
Dout
1
N
85h
Col. Col. Row.Row.
Dout
Dout
Add1Add2Add1Add2
1
N
70h Status
10h
tPROG
tR
:Don't care
Figure 20: Copy-Back Program with Random Data Input figures
24
IO 0 = 0, pass
IO 0 = 1, fail
GD9Fx1GxF2A
8.3 Block Erase Operation (60H-D0H)
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command (60H). Only address Row Address is valid while Column Addresses ignored. The Erase Confirm
command (D0H) following the block address loading initiates the internal erasing process. At the rising edge of WE after
the erase confirm command input, the internal write controller handles erase and erase verify. Once the erase process
starts, the Read Status Register command may be entered to read the status register. The system controller can detect
the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read
Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the
Write Status Bit (I/O 0) may be checked.
Row Add 1.2
Address
I/Ox
60H
(2cycle)
70H
D0H
R/B#
Status
tBERS
Figure 21: Common Block Erase Operation figures
8.4 Reset (FFH)
The device offers a reset feature, executed by writing FFH to the command register. When the device is in busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells
being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to
wait for the next command, and the Status Register is cleared to value C0h when R/B# is high. If the device is already in
reset state a new reset command will be accepted by the command register. The R/B# pin transitions to low for tRST after
the Reset command is written.
CE#
CLE
WE#
tWB
I/Ox
FFH
R/B#
tRST
Figure 22: Reset (FFH) figures
25
GD9Fx1GxF2A
8.5 Read Device Information
8.5.1 Read ID and ONFI Signature (90H)
The device contains a product identification mode, initiated by writing 90H to the command register, followed by an
address input of 00H. Four read cycles sequentially output the manufacturer code, and the device code and other
information, respectively. The command register remains in Read ID mode until further commands are issued to.
CE#
CLE
WE#
tWHR
tAR
ALE
tREA
RE#
I/Ox
90H
MID
00H
DID
DID
DID
DID
Figure 23: Read ID figures
ID Definition Table
Byte
Description
1st Byte
Manufacturer Code (MID)
2nd
Device Code (DID)
Byte
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages,
3rd Byte
Interleaved Program, Write Cache
4th Byte
Page size, Block size, Spare size, Organization
5th
ECC & Plane
Byte
Read ID Data Table
Part Number
VCC
Bus Width
MID(1st)
DID(2nd)
3rd
4th
5th
GD9FU1G8F2A
3.3v
x8
C8
F1H
80H
1DH
42H
GD9FU1G6F2A
3.3v
x16
C8
C1H
80H
5DH
42H
GD9FS1G8F2A
1.8v
x8
C8
A1H
80H
15H
42H
GD9FS1G6F2A
1.8v
x16
C8
B1H
80H
55H
42H
26
GD9Fx1GxF2A
2rd
Byte of Device Code Description
2rd Cycle
Description
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
3.3v 8bits
1
1
1
1
3.3v 16bits
1
1
0
0
1.8v 8bits
1
0
1
0
1.8v 16bits
1
0
1
1
1G
0
0
0
1
2G
0
0
1
0
4G
0
0
1
1
8G
0
1
0
0
16G
0
1
0
1
32G
0
1
1
0
64G
0
1
1
1
256G
1
0
0
0
512G
1
0
0
1
1T
1
0
1
0
2T
1
0
1
1
22G
1
1
0
0
IO3
IO2
IO1
IO0
1
0
0
2
0
1
4
1
0
8
1
1
VCC, Bus Width
Memory density
3rd Byte of Device Identifier Description
3rd Cycle
Description
IO7
IO6
IO5
IO4
Internal Chip Number
2 Level Cell
0
0
4 Level Cell
0
1
8 Level Cell
1
0
16 Level Cell
1
1
Cell Type
Number
of
Simultaneously
Programmed Pages
1
0
0
2
0
1
4
1
0
8
1
1
Not
Interleaved Program Between
Multiple Die
Write Cache
(Cache Programming)
0
Supported
Supported
Not
Supported
Supported
1
0
1
27
GD9Fx1GxF2A
4th
Byte of Device Identifier Description
4th Cycle
Description
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1KB
0
0
2KB
0
1
4KB
1
0
8KB
1
1
Page Size (without Spare Area)
Size of spare area (byte per
512-byte)
16
0
32
1
45ns
0
0
25ns
0
1
Reserved
1
0
Reserved
1
1
Serial Access Time
Block
Size
Area)
(Without
Spare
64KB
0
0
128KB
0
1
256KB
1
0
512KB
1
1
x8
0
x16
1
Organization
28
GD9Fx1GxF2A
5th
Byte of ECC & Plane
5th Cycle
Description
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
1
0
0
2
0
1
4
1
0
8
1
1
ECC Level
1
0
0
2
0
1
4
1
0
8
1
1
Plane Number
64Mb
0
0
0
128Mb
0
0
1
256Mb
0
1
0
512Mb
0
1
1
1Gb
1
0
0
2Gb
1
0
1
4Gb
1
1
0
8Gb
1
1
1
Plane size
ECC
disabled
Internal ECC
ECC
enabled
0
1
To retrieve the ONFI signature, the command 90H together with an address of 20H shall be entered. The ONFI signature
is the ASCII encoding of ‘ONFI’ where ‘O’ = 4FH, ‘N’ = 4EH, ‘F’ = 46H, and ‘I’ = 49H. Reading beyond four bytes yields
indeterminate values.
CLE
WE#
ALE
RE#
tWHR
IO0-7
90H
20H
4FH
4EH
Figure 24: Read ONFI Signature figures
29
46H
49H
GD9Fx1GxF2A
8.5.2 Read Unique ID (EDH)
The Read Unique ID function is used to retrieve the 16 byte unique ID (UID) for the device. The unique ID when combined
with the device manufacturer shall be unique.
The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID
is returned with its complement. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid. To
accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding
complement shall be stored by the target. For example, reading bytes 32-63 returns to the host another copy of the UID
and its complement.
To change the data output location, it is recommended to use the Random Data Out command set (05H-E0H).The Status
Read command (70H) can be used to check the completion. To continue the read operation, a following read command
(00h) to re-enable the data out is necessary.
Bytes
Value
0-15
UID
16-31
UID complement (bit-wise)
CLE
WE#
ALE
RE#
IO0-7
R/B#
EDH
00H
U00
tR
Figure25: Read Unique ID Timing
30
U10
…
U01
U11
…
GD9Fx1GxF2A
8.5.3 Read Parameter Page (ECH)
The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features, timingsand other behavioral parameters. This data structure enables the host processor to automatically recognize the NAND
Flash configuration of a device. The whole data structure is repeated at least three times. The Random Data Read
command (05H-E0H) can be issued during execution of the read parameter page to read specific portion-soft the parameter
page. The Read Status command (70H) may be used to check the status of read parameter page during execution. After
completion of the Read Status command, 00H is issued by the host on the command line to continue with the data output
flow for the Read Parameter Page command.
CLE
WE#
ALE
RE#
IO0-7
R/B#
ECH
00H
P00
tR
Figure 26: Read Parameter Page figures
31
P00
…
P01
P11
…
GD9Fx1GxF2A
Byte
O/M
Description
0-3
M
Parameter page signature
4FH
Byte 0: 4FH, “O”
4EH
Byte 1: 4EH, “N”
46H
Byte 2: 46H, “F”
49H
Byte 3: 49H, “I”
4-5
M
Revision number
02H
2-15 Reserved (0)
00H
1 1 = supports ONFI version 1.0
0 Reserved (0)
6-7
M
Features supported
10H(X8)/
5-15 Reserved (0)
11H(X16)
4 1 = supports odd to even page Copyback
00H
3 1 = supports interleaved operations
2 1 = supports non-sequential page programming
1 1 = supports multiple LUN operations
0 1 = supports 16-bit data bus width
8-9
M
Optional commands supported
33H
6-15 Reserved (0)
00H
5 1 = supports Read Unique ID
4 1 = supports Copy-back
3 1 = supports Read Status Enhanced
2 1 = supports Get Features and Set Features
1 1 = supports Read Cache Integrity
0 1 = supports Page Cache Program command
10-31
Reserved (0)
00H
…
00H
Manufacturer Information block
32-43
M
Device manufacturer (12 ASCII characters)“GIGADEVICE
”
47H
49H
47H
41H
44H
45H
56H
49H
43H
45H
20H
20H
32
GD9Fx1GxF2A
44-63
M
Device model (20 ASCII characters)
47H
Device Model
ORGANIZATION
VCC RANGE
44H
“GD9FS1G8F2A”
128M x 8bit
1.7v ~ 1.95v
39H
“GD9FS1G6F2A”
64M x 16bit
1.7v ~ 1.95v
46H
“GD9FU1G8F2A“
128M x 8bit
2.7v ~ 3.6v
53H/55H
“GD9FU1G6F2A“
64M x 16bit
2.7v ~ 3.6v
31H
47H
38H/36H
46H
32H
41H
20H
20H
20H
20H
20H
20H
20H
20H
20H
64
M
JEDEC manufacturer ID“C8”
C8H
65-66
O
Date code
00H
00H
67-79
Reserved
00H
00H
00H
Memory organization block
80-83
M
Number of data bytes per page
00H
08H
00H
00H
84-85
M
Number of spare bytes per page
80H
00H
86-89
M
Number of data bytes per partial page
00H
02H
00H
00H
90-91
M
Number of spare bytes per partial page
20H
00H
92-95
M
Number of pages per block
40H
00H
00H
00H
33
GD9Fx1GxF2A
96-99
M
Number of blocks per logical unit (LUN)
00H
04H
00H
00H
100
M
Number of logical units (LUNs)
01H
101
M
Number of address cycles
22H
4-7 Column address cycles
0-3 Row address cycles
102
M
Number of bits per cell
01H
103-104
M
Bad blocks maximum per LUN
14H
00H
105-106
M
Block endurance
01H
05H
107
M
Guaranteed valid blocks at beginning of target
01H
108-109
M
Block endurance for guaranteed valid blocks
01H
05H
110
M
Number of programs per page
04H
111
M
Partial programming attributes
00H
5-7 Reserved
4 1 = partial page layout is partial page data followed by partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
112
M
Number of bits ECC correctability
04H
113
M
Number of interleaved address bits
00H
4-7 Reserved (0)
0-3 Number of interleaved address bits
114
O
Interleaved operation attributes
00H
4-7 Reserved (0)
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
115-127
Reserved
00H
…
00H
Electrical parameters block
128
M
I/O capacitance
06H
34
GD9Fx1GxF2A
129-130
M
Timing mode support
07H(3.3V)/
6-1 5Reserved (0)
03H(1.8V)
5 1 = supports timing mode 5
00H
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0, shall be 1
131-132
O
Program cache timing mode support
07H(3.3V)/
6-1 5Reserved (0)
03H(1.8V)
5 1 = supports timing mode 5
00H
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0,
133-134
M
tPROG Maximum page program time (us)
BCH
02H
135-136
M
tBERS Maximum block erase time (us)
10H
27H
137-138
M
tR Maximum page read time (us)
19H
00H
139-140
M
tCCS Minimum Change Column setup time (ns)
3CH
00H
141-163
Reserved
00H
Vendor block
164-165
M
166-253
254-255
M
Vendor specific Revision number
00H
Vendor specific
00H
Integrity CRC
Redundant parameter pages
256-511
M
Value of bytes 0-255
512-767
M
Value of bytes 0-255
768+
O
Additional redundant parameter pages
Notes:
1.
“O” Stands for Optional, “M” for Mandatory
2.
The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were
transferred correctly to the host. Please refer to ONFI 1.0 specifications for details.
The CRC shall be calculated using the following 16-bit generator polynomial: G(X) = X16 + X15 +X2 + 1， This
polynomial in hex may be represented as 8005h.
3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the
final CRC value after it is calculated. There is no reversal of the data bytes or the CRC calculated value.
35
GD9Fx1GxF2A
Parameter page CRC value table
Device Model
ORGANIZATION
VCC RANGE
CRC value
B254/B255
“GD9FS1G8F2A”
128M x 8bit
1.7v ~ 1.95v
D0H/DBH
“GD9FS1G6F2A”
64M x 16bit
1.7v ~ 1.95v
F8H/18H
“GD9FU1G8F2A“
128M x 8bit
2.7v ~ 3.6v
88H/D5H
“GD9FU1G6F2A“
64M x 16bit
2.7v ~ 3.6v
A0H/16H
8.6 Read Status (70H)
The device contains a Status Register which may be read to find out whether an operation is completed and whether the
program or erase operation is completed successfully. After writing 70H command to the command register, a read cycle
outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last. This
allows the system to poll the progress of each device in multiple memory connections even when R/B# pins are commonwired. RE# or CE# does not need to be toggled for updated status. The command register remains in Status Read mode
until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read
command (00h) should be given before starting read cycles.
tCLR
CLE
CE#
WE#
tCLS
tCLR
tCS
tCH
tCEA
tWP
tCHZ
tWHR
tCOH
RE#
tRHZ
IO0-7
tDS
tDH
tRHOH
tIR
70h
tREA
Figure 27: Read Status figures
36
Status
GD9Fx1GxF2A
Status Register Definitions
I/O No.
I/O 0
Page
Block
Cache
Program
Erase
Program
Pass/Fail
Pass/Fail
Pass/Fail(N)
Read
Cache Read
Definition
Not use
Not use
N Page
Pass : 0
I/O 1
Not use
Not use
Pass/Fail(N-
Not use
Not use
1)
Fail : 1
N-1 Page
Pass : 0
Fail : 1
I/O 2
Not use
Not use
Not use
Not use
Not use
“0”
I/O 3
Not use
Not use
Not use
Not use
Not use
Not use
I/O 4
Not use
Not use
Not use
Not use
Not use
0
I/O 5
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
P/E/R controller
Busy : 0
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Data Cache
Busy : 0
I/O 7
Write
Write
Protect
Protect
Write Protect
Write Protect
Write Protect
Ready : 1
Ready : 1
Protected:0
Not Protected:1
Notes:
1. I/O0: This bit is only valid for Program and Erase operations. During Cache Program operations, this bit is only valid
when I/O5 is set to 1.
2. I/O1: This bit is only valid for cache program operations. This bit is not valid until after the second 15h command or
the 10h command has been transferred in a Cache program sequence.
3. I/O5: If set to one, then there is no array operation in progress. If cleared to zero, then there is a command being
processed (I/O6 is cleared to zero) or an array operation in progress.
4. I/O6: When cache operations are in use, then this bit indicates whether another command can be accepted, and
I/O5 indicates whether the operation is complete.
37
GD9Fx1GxF2A
8.7 Ready/Busy# (R/B#)
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copyback and random read completion. The R/B# pin is normally high and goes to low when the device is busy (after a reset,
read, program, and erase operation). It returns to high when the internal controller has finished the operation. The pin is an
open-drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is related to tR
(R/B#), an appropriate value can be obtained with the following reference below chart. Its value can be determined by the
following guidance.
Ready
Rp
Vcc
VOH
VOL : 0.4V, VOH : 2.4V
Vcc
VOL
Busy
tr
tf
R/B#
Open drain output
Fig. Rp vs tr, tf & Rp
@ Vcc = 3.3 V, Ta = 25ºC,CL=50pF
200
182
160
150
GND
108.8
100
Device
69.8
Rp value guidence
Vcc (Max.) – VOL (Max.)
Rp (min) =
IOL + ΣIL
50
=
3.2V
8mA + ΣIL
tr
35
3.84
Where IL is the sum of the input curmts of all devices tied to the R/B# pin.
Rp(max) is determined by maximum permissible limit of tr
1K
Figure 28: Ready/Busy figures
38
tf 3.66
2K
3.22
3.76
3.86
3K
4K
5K
Rp(ohm)
GD9Fx1GxF2A
8.8 Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage
detector disables all functions whenever VCC is below VLKO. WP# pin provides hardware protection and is recommended
to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit
gets ready for any command sequences. The two-step command sequence for program/erase provides additional software
protection.
Vcc(min)
Vcc(min)
Vth
2.5Vth
VCC
0V
don't care
Don't care
CE
VIH
VIL
WP
VIL
5ms max
Operation
don't care
Ready Busy
Figure 29_a: Data protection and Power on/off (3.3V Device)
Vcc(min)
Vcc(min)
Vth
1.5Vth
0V
VCC
don't care
Don't care
CE
WP
VIH
VIL
VIL
Operation
5ms max
don't care
Ready Busy
Figure 29_b: Data protection and Power on/off (1.8V Device)
39
GD9Fx1GxF2A
9. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
VIN/OUT
-0.6 to + 4.6
VCC
-0.6 to + 4.6
Temperature Under Bias
TBIAS
-50 to +125
°C
Storage Temperature
TSTG
-65 to +150
°C
Voltage on any pin relative to VSS
Unit
V
Notes:
1.
Minimum DC voltage is -0.6V on input/output pins.
2.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
40
GD9Fx1GxF2A
10. VALID BLOCKS
Min
Valid Block Number
Typ
1004
Max
Unit
1024
Blocks
Notes:
1.
The 1st block is guaranteed to be a valid block with ECC at the time of shipment.
2.
Invalid blocks are one that contains one or more bits. The device may contain invalid blocks upon shipment.
41
GD9Fx1GxF2A
11. DC CHARACTERISTICS
Parameter
Power on reset current
Page Read with
Symbol
ICC0
ICC1
Test Conditions
1.7v ~ 1.95v / 2.7v ~ 3.6v
Min
Typ.
FFh command after power on
tRC=Min, CE#=VIL,
Max
50
-
15
30
-
-
15
30
ICC3
-
-
15
30
Standby Current (CMOS)
ISB
CE#=VCC-0.2, WP#=0V/VCC
-
10
50
Input Leakage Current
ILI
VIN=0 to Vcc(max)
-
-
±10
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
-
-
±10
Input High Voltage
VIH
-
0.8xVCC
-
VCC+0.3
Input Low Voltage
VIL
-
-0.3
-
0.2xVCC
Output High Voltage Level
VOH
IOH=-400μA
VCC-0.3
-
-
Output Low Voltage Level
VOL
IOL=2.1mA
-
-
0.4
Output Low Current(R/B#)
IOL(R/B#)
VOL=0.45V
3/8
4/10
-
Operating
Serial Access
Current
Program
ICC2
Erase
erase/program lockout voltage
IOUT=0mA
VLKO
1.5/1.9
42
Unit
mA
mA
μA
V
mA
V
GD9Fx1GxF2A
12. AC CHARACTERISTICS
12.1 Test Condition
(TA=-40 to 85°CVcc=1.7V~1.95V /2.7V~3.6V)
Parameter
GD9FS1G8F2A/GD9FU1G8F2A
Input Pulse Levels
0V to VCC
Input Rise and Fall Times
5ns
Input and Output Timing Levels
VCC/2
Output Load
1 TTL GATE and CL=30fF
12.2 Capacitance (TA=25°C, F=1.0MHz)
Parameter
Symbol
Test condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
6
pF
Input Capacitance
CIN
VIN=0V
-
8
pF
Notes: Capacitance is periodically sampled and not 100% tested.
43
GD9Fx1GxF2A
12.3 AC Timing Characteristics
3.3V
Parameter
1.8V
Symbol
Min
Max
Min
Max
CE# setup time
tCS
15
-
15
-
ns
CE# hold time
tCH
5
-
5
-
ns
CLE setup time
tCLS
12
-
12
-
ns
CLE Hold time
tCLH
5
-
5
-
ns
ALE setup time
tALS
12
-
12
-
ns
ALE hold time
tALH
5
-
5
-
ns
Data setup time
tDS
12
-
12
-
ns
Data hold time
tDH
5
-
5
-
ns
Write cycle time
tWC
25
-
45
-
ns
WE# pulse width
tWP
12
-
22
-
ns
WE# high hold time
tWH
10
-
15
-
ns
Address to data loading time
tADL
70
-
70
-
ns
WE# high to busy
tWB
-
100
-
100
ns
Ready to WE# low
tRW
20
-
20
-
ns
Ready to RE# low
tRR
20
-
20
-
ns
CLE to RE# delay
tCLR
10
-
10
-
ns
ALE to RE# delay
tAR
10
-
10
-
ns
Read cycle time
tRC
25
-
45
-
ns
RE# pulse width
tRP
12
-
22
-
ns
RE# high hold time
tREH
10
-
15
-
ns
RE# access time
tREA
-
20
-
30
ns
CE# access time
tCEA
-
25
-
45
ns
RE# high to output high Z
tRHZ
-
100
-
100
ns
CE# high to output high Z
tCHZ
-
50
-
50
ns
CE# high to ALE or CLE Don’t care
tCSD
10
-
10
-
ns
CE# high to output hold
tCOH
15
-
15
-
ns
RE# high to output hold
tRHOH
15
-
15
-
ns
RE# low to output hold
tRLOH
3
-
3
-
ns
Output Hi-Z to RE# Low
tIR
0
-
0
-
ns
CE# low to RE# low
tCR
10
-
10
-
ns
RE# high to WE# low
tRHW
100
-
100
-
ns
WE# high to RE# low
tWHR
60
-
60
-
ns
Write protect time
tWW
100
-
100
-
ns
44
GD9Fx1GxF2A
12.4 Performance Characteristics
Parameter
Symbol
Data transfer from cell to register
Min
Typ.
Max
Unit
25
us
300
700
μs
tR
Program Time
tPROG
Read Cache busy time
tCBSYR
5
tR
μs
Cache Program short busy time
tCBSYW
5
700
μs
Number of Partial Program Cycles in the Same Page
Block Erase Time
NOP
-
-
4
cycles
tBERS
-
3
10
ms
10
us
20
us
500
us
Read
Device resetting time
-
Program
tRST
Erase
Note: Typical value is measured at Vcc=3.3V, TA=25℃(3.3V Device) or Vcc=1.8 V, TA=25℃(1.8V Device).
45
GD9Fx1GxF2A
13. PACKAGE INFORMATION
13.1 TSOPI-48
c
0.08
M
Hd
Pin48
Pin24
Pin25
0.10
SEATINGPLANE
e
E
E1
b
Pin1
“A”
A1
D
A3
0.254
Θ
L
SEATING PLANE
L1
DETAIL “A”
Hd
Pin24
Pin25
Pin1
Pin48
Figure 30: TSOPI-48 figures
46
A
A2
GAUGE PLANE
GD9Fx1GxF2A
Symbol/unit
Mm
A
A1
A2
A3
b
C
Hd
D
e
E
E1
L
L1
ɵ
1.2 Max
0.10±0.05
1.0±0.1
0.145±0.055
0.22±0.08
0.125 TYP
20.0±0.2
18.4±0.1
0.5 TYP
12.0±0.1
12.4 Max
0.525±0.100
0.8±0.2
0 degree ~7 degree
Note：
1. Tolerance of the dimension should be ±0.1 unless otherwise specified.
2. Corner radius should be less than ±0.1R unless otherwise specified (excluding outer lead).
3. Tolerance of the angles should be ±0.5 degree unless otherwise specified.
4. The mold surface should have a finish 8±2S without luster.
Trace of knockout pin and the ahaded portion of detail “A” should be polish surface.
5. Discrepancies between upper and lower molding cavity should be less than 0.05 of the package.
6. Mold flush should be less than 0.2mm.
47
GD9Fx1GxF2A
13.2 FBGA-63
TOP VIEW
BOTTOM VIEW
A1 INDEX
A1 INDEX
A
2 3 4 5 6 7 8 9 10
9 8 7 6 5 4 3 2
1
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
e
D1
D
SD
1
10
E
B
e
DETAIL B
E1
0.15 (4X)
SE
DETAIL A
C
A
A2
0.20
SEATING PLANE
A1
C
0.10
DETAIL A
SIDE VIEW
SOLDER BALL
b(63x PLACES)
0.15 M
0.08 M
C
A
B
C
DETAIL B
Figure 31: FBGA-63 figures
48
C
GD9Fx1GxF2A
SYM
MIN
DIMENSION
DIMENSION
(mm)
(inch)
NOM
A
MAX
MIN
NOM
1.05
MAX
0.041
A1
0.25
0.30
0.35
0.010
0.012
0.014
A2
0.61
0.66
0.71
0.024
0.026
0.028
b
0.40
0.45
0.50
0.016
0.018
0.020
D
10.90
11.00
11.10
0.429
0.433
0.437
D1
E
8.80 BSC
8.90
9.00
0.346 BSC
9.10
0.350
0.354
E1
7.20 BSC
0.283 BSC
SE
0.90 TYP
0.035 TYP
SD
1.10 TYP
0.043 TYP
e
0.80 BSC
0.031 BSC
Note：
1. Controlling dimension: millimeter.
2. Reference document: JEDEC MO-207
3. The diameter of pre-reflow solder ball is ø0.42mm (0.40mm SMO).
49
0.358
GD9Fx1GxF2A
14. Part Numbering Information
GD 9F U 1G 8 F 2 A M G I
1
2
3
4
5 6 7 8
9 10 11
1. GD
7. Function Mode:
2: Sequential Row Read Disable;
2. Memory Type
9F: Parallel NAND
8. Process Generation:
A: 1st
B: 2nd
3. Power Supply
VCCQ
VCC
U
2.7v ~ 3.6v
2.7v ~ 3.6v
S
1.7v ~ 1.95v
1.7v ~ 1.95v
9.
M:
L:
W:
4. Density:
12: 128Mb
25: 256Mb
51: 512Mb
1G: 1Gb
2G: 2Gb
4G: 4Gb
8G: 8Gb
AG: 16Gb
BG: 32Gb
CG: 64Gb
DG: 128Gb
EG: 256Gb
FG: 512Gb
HG: 1Tb
10. Package Material & Packing
G: Lead & Halogen Free
W: Wafer
11.
I:
F:
J:
Temperature Grade
Industrial (-40C ~ 85C)
Industrial+ (-40C ~ 85C)
Industrial (-40C ~ 105C)
Note: (1) F: Industrial+, Full Function Test for Automotive
application and No AECQ
5. Organization
8: x8
6: x16
6.
F:
T:
U:
V:
Package
TSOPI-48
FBGA-63
Wafer
NAND Type:
SLC, 1Die, 1nCE, 1Rnb
TLC; 1Die, 1nCE, 1Rnb
TLC; 2Die, 1nCE, 1Rnb
TLC; 4Die, 1nCE, 1Rnb
50
SLC NAND FLASH
GD9Fx1GxF2A
15. Revision History
Version No.
History Description
Date
1.0
Update parameter page value
2016-6-2
Update package FBGA-63 information
1.1
Change page size from 2K+64 to 2K+128
2016-7-12
1.2
Add CRC value in parameter page
2016-11-01
Remove tFEAT parameter
Change Device resetting time for read from 5us to 10us
Change Device resetting time for read from 10us to 20us
Add parameter page CRC value table
1.3
Add parameter page CRC arithmetic related description
2016-11-15
Update CRC table value
Update Package information according Package vendor final file.
1.4
Update R/B# Resistance figure with Trise and Tfall
2016-12-14
Update some figure with RD review.
1.5
Update Part Numbering Information
2017-02-27
Add F code at field “Temperature Grade” for Full Function Test for Automotive
application and No AECQ
1.6
Remove last three code from part number
2017-06-26
1.7
Change VOL Max. from 0.1 to 0.4
2017-10-31
Change ISB Max. from 30 to 50
Change IOL(R/B#) test condition VOL from 0.4V to 0.45V
Change description with “The addressing must be done in sequential order in a block”
for page program
1.8
Add a note of P/E cycles with ECC
2017-11-14
Delete Commercial Temperature Grade. And add Industrial(J) (-40C ~ 105C)
Temperature Grade
1.9
Change P/E cycles with ECC from 50k to 100k, and delete note.
2017-11-27
Delete Industrial+(F):-40C~85C
2.0
Change Operating Current Standby (Max.) from 30uA to 50uA
2018-4-4
Change VOH min from VCC-0.1 to VCC-0.3V
Change Parameter page table Byte 105-106 ,108-109,and change CRC Value
Change 1.8V tWP and tRP from 12 to 22, Change 1.8V tWH and tREH from 10 to 15
Change tCBSYW and tCBSYR from 3us to 5us
Add the figure for Read Unique ID Timing.
2.1
Update the tf and tr value in Figure26 :Ready/Busy figures
2018-5-2
Modify the typo of reliability of program/erase cycles with ECC in chapter 2
Add part numbers of GD9FU1G6F2AMG and GD9FS1G6F2AMG in chapter2.1
2.2
Modify the description of Write Protect
2018-05-17
Add the chapter of 5.3 Factory Defect Mapping
51
SLC NAND FLASH
GD9Fx1GxF2A
Important Notice
This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property
of their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product,
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to
properly design, program, and test the functionality and safety of any application made of this information and any resulting
product. Except for customized products which has been expressly identified in the applicable agreement, the Products are
designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only.
The Products are not designed, intended, or authorized for use as components in systems designed or intended for the
operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control
instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical
devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or Product could cause personal injury, death, property or
environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and
customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,
or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the
Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Information in this document is provided solely in connection with the Products. The Company reserves the right to
make changes, corrections, modifications or improvements to this document and the Products and services described
herein at any time, without notice.
52
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