IS31FL3743A
18 × 11 DOTS MATRIX LED DRIVER
August 2018
GENERAL DESCRIPTION
FEATURES
The IS31FL3743A is a general purpose 18×n (n=1~11)
LED Matrix programmed via 1MHz I2C compatible
interface. Each LED can be dimmed individually with
8-bit PWM data and 8-bit DC scaling data which
allowing 256 steps of linear PWM dimming and 256
steps of DC current adjustable level.
Additionally each LED open and short state can be
detected, IS31FL3743A store the open or short
information in Open-Short Registers. The Open-Short
Registers allowing MCU to read out via I2C
compatible interface, inform MCU whether there are
LEDs open or short and the locations of open or short
LEDs.
The IS31FL3743A operates from 2.7V to 5.5V and
features a very low shutdown and operational current.
IS31FL3743A is available in UQFN-40 (5mm×5mm)
package. It operates from 2.7V to 5.5V over the
temperature range of -40°C to +125°C.
Supply voltage range: 2.7V to 5.5V
18 current sinks
Support 18×n (n=1~11) LED matrix configurations
Individual 256 PWM control steps
Individual 256 DC current steps
Global 256 DC current steps
SDB rising edge reset I2C module
Programmable H/L logic: 1.4V/0.4V, 2.4V/0.6V
24kHz PWM frequency
1MHz I2C-compatible interface
State lookup registers
Individual open and short error detect function
180 degree phase delay operation to reduce
power noise
De-Ghost
Cascade for synchronization of chips
UQFN-40 (5mm×5mm) package
APPLICATIONS
Hand-held devices for LED display
Gaming device (Keyboard, Mouse etc.)
LED in white goods application
TYPICAL APPLICATION CIRCUIT
5V
5
1 F
22
1 F
PVCC
SW11
0.1 F
SW10
VCC
11
40
SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11
0.1 F
51R
CS18
VIO/MCU
2k
SW2
2k
28
27
Micro
Controller
26
SW1
SDA
SCL
CS18
29
24
RISET
10k
25
23
6
20R
CS17
20R
CS16
IS31FL3743A
SDB
0.1 F 100k
30
4
CS17
12
13
SYNC
51R
CS3
20R
CS2
ISET
20R
ADDR 2
CS2
ADDR 1
CS1
38
CS1
39
GND
Figure 1 Typical Application Circuit: 66 RGBs
Note 1: For the mobile applications the IC should be placed far away from the mobile antenna in order to prevent the EMI.
Note 2: PVCC and VCC should use same power supply to avoid the additional ISD, it is OK to use PVCC=VCC=5V and VIO=3.3V.
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1
IS31FL3743A
TYPICAL APPLICATION CIRCUIT (CONTINUED)
5V
5
1 F
22
1 F
PVCC
SW11
0.1 F
SW10
VCC
11
40
SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11
0.1 F
20R
CS18
VIO/MCU
2k
SW2
2k
28
27
Micro
Controller
26
SW1
SDA
SCL
CS18
29
24
RISET
10k
25
23
20R
CS17
6
20R
CS16
IS31FL3743A
SDB
0.1 F 100k
30
4
CS17
12
13
SYNC
20R
CS3
20R
CS2
ISET
20R
ADDR 2
CS2
ADDR 1
CS1
38
CS1
39
GND
Figure 2 Typical Application Circuit: 198 Mono Color LEDs
VCC
VIO
2k
ADDR1
ADDR2
ADDR2
SDA
ADDR1
SCL
ADDR2
ADDR1
ADDR2
2k
SDA
Micro
Controller
ADDR1
SCL
SDB
SDA
SDA
SDA
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SDB
SDB
SDB
SDB
SDB
SDB
SDB
100k
SYNC
SYNC
Master
SYNC
SYNC
Slave 1
SYNC
VCC
SYNC
Slave 2
SYNC
VCC
SYNC
VCC
ADDR2
ADDR2
ADDR1
ADDR1
VCC
ADDR2
SDA
ADDR2
ADDR1
SCL
ADDR1
SDA
SDA
SDA
SDA
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SDB
SDB
SDB
SDB
SDB
SDB
SDB
SDB
Slave 4
Slave 5
Slave 3
Slave 6
Slave 7
Figure 3 Typical Application Circuit (Eight Parts Synchronization-Work)
Note 3: The 20R and 50R between LED and IC is only for thermal reduction, for mono red LED, if PVCC=VCC=3.3V, don’t need these resistors.
Note 4: One part is configured as master mode, all the other 7 parts configured as slave mode. Work as master mode or slave mode specified
by Configuration Register (SYNC bits, register 25h, Page 2). Master part output master clock, and all the other parts which work as slave input
this master clock.
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IS31FL3743A
PIN CONFIGURATION
40 SW10
39 CS1
38 CS2
37 CS3
36 CS4
35 CS5
34 CS6
33 CS7
32 CS8
31 CS9
CS18 12
CS17 13
CS16 14
CS15 15
PGND 16
CS14 17
CS13 18
CS12 19
CS11 20
Pin Configuration (Top View)
SW11 11
Package
UQFN-40
PIN DESCRIPTION
No.
Pin
Description
1~4
SW8,SW6,SW4,SW2
Power SW.
5
PVCC
Power for current source SW.
6~11
SW1,SW3,SW5,
SW7,SW9,SW11
Power SW.
12~15
CS18~CS15
Current sink pin for LED matrix.
16
PGND
Power GND.
17~21
CS14~CS10
Current sink pin for LED matrix.
22
VCC
Analog and digital circuits.
23
GND
Analog GND.
24
ADDR2
I2C address select pin 2.
25
ADDR1
I2C address select pin 1.
26
SDB
Shutdown pin.
27
SCL
I2C compatible serial clock.
28
SDA
I2C compatible serial data.
29
ISET
Set the maximum IOUT current.
30
SYNC
Synchronization.
31~39
CS9~CS1
Current sink pin for LED matrix.
40
SW10
Power SW.
Thermal Pad
Connect to GND.
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IS31FL3743A
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS31FL3743A-QULS4-TR
UQFN-40, Lead-free
2500
Copyright © 2018 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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4
IS31FL3743A
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at any input pin
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Package thermal resistance, junction to ambient (4 layer standard
test PCB based on JESD 51-2A), θJA
ESD (HBM)
ESD (CDM)
-0.3V ~+6.0V
-0.3V ~ VCC+0.3V
+150°C
-65°C ~+150°C
-40°C ~ +125°C
41.6°C/W
±7kV
±1kV
Note 5: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
The following specifications apply for VCC = 3.6V, TA= 25°C, unless otherwise noted.
Symbol
Parameter
VCC
Supply voltage
ICC
Quiescent power supply current
Conditions
Min.
Typ.
2.7
VSDB=VCC, all LEDs off
1.8
VSDB=0V
1.3
1.3
ISD
Shutdown current
VSDB= VCC, Configuration Register
written “0000 0000
IOUT
Maximum constant current of
CSx
RISET=10kΩ, GCC=0xFF
SL=0xFF
ILED
Average current on each LED
ILED = IOUT(PEAK)/Duty(11.275)
RISET=10kΩ, GCC=0xFF
SL=0xFF
3.03
Current switch headroom voltage
SWx
ISWITCH=612mA RISET=10kΩ,
GCC=0xFF, SL=0xFF
550
Current sink headroom voltage
CSx
ISINK=34mA, RISET=10kΩ,
GCC=0xFF, SL=0xFF
450
VHR
tSCAN
Period of scanning
tNOL1
tNOL2
32.09
34.5
Max.
Unit
5.5
V
mA
μA
36.91
mA
mA
mV
33
µs
Non-overlap blanking time during
scan, the SWx and CSy are all
off during this time
0.83
µs
Delay total time for CS1 to CS
18, during this time, the SWx is
on but CSx is not all turned on
0.3
µs
Logic Electrical Characteristics (SDA, SCL, ADDRx, SDB)
VIL
Logic “0” input voltage
VCC=2.7V~5.5V, LGC=0
VIH
Logic “1” input voltage
VCC=2.7V~5.5V, LGC=0
Input schmitt trigger hysteresis
VCC=3.6V, LGC=0
VIL
Logic “0” input voltage
VCC=2.7V~5.5V, LGC=1
VIH
Logic “1” input voltage
VCC=2.7V~5.5V, LGC=1
Input schmitt trigger hysteresis
VCC=3.6V, LGC=1
IIL
Logic “0” input current
IIH
Logic “1” input current
VHYS
VHYS
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0.4
1.4
V
V
0.2
V
0.6
2.4
V
V
0.2
V
SDB=L, VINPUT = L (Note 6)
5
nA
SDB=L, VINPUT = H (Note 6)
5
nA
5
IS31FL3743A
DIGITAL INPUT I2C SWITCHING CHARACTERISTICS (NOTE 6)
Fast Mode
Symbol
Parameter
Min.
Typ. Max.
fSCL
Serial-clock frequency
tBUF
Fast Mode Plus
Min.
Typ.
Max.
Units
-
400
-
1000
kHz
Bus free time between a STOP and a
START condition
1.3
-
0.5
-
μs
tHD, STA
Hold time (repeated) START condition
0.6
-
0.26
-
μs
tSU, STA
Repeated START condition setup time
0.6
-
0.26
-
μs
tSU, STO
STOP condition setup time
0.6
-
0.26
-
μs
tHD, DAT
Data hold time
-
-
-
-
μs
tSU, DAT
Data setup time
100
-
50
-
ns
tLOW
SCL clock low period
1.3
-
0.5
-
μs
tHIGH
SCL clock high period
0.7
-
0.26
-
μs
tR
Rise time of both SDA and SCL signals,
receiving
-
300
-
120
ns
tF
Fall time of both SDA and SCL signals,
receiving
-
300
-
120
ns
Note 6: Guaranteed by design.
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IS31FL3743A
FUNCTIONAL BLOCK DIAGRAM
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IS31FL3743A
DETAILED DESCRIPTION
I2C INTERFACE
IS31FL3743A uses a serial bus, which conforms to the
I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31FL3743A has a 7-bit
slave address (A7:A1), followed by the R/W bit, A0.
Set A0 to “0” for a write command and set A0 to “1” for
a read command. The value of bits A1 and A2 are
decided by the connection of the ADDRx pin.
Table 1 Slave Address:
ADDR2 ADDR1
A7:A5
A4:A3
A2:A1
A0
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the
master checks for the IS31FL3743A’s acknowledge.
The master releases the SDA line high (through a
pull-up resistor). Then the master sends an SCL pulse.
If the IS31FL3743A has received the address correctly,
then it holds the SDA line low during the SCL pulse. If
the SDA line is not low, then the master should send a
“STOP” signal (discussed later) and abort the transfer.
Following acknowledge of IS31FL3743A, the register
address byte is sent, most significant bit first.
IS31FL3743A must generate another acknowledge
indicating that the register address has been received.
GND
GND
00
00
GND
SCL
00
01
GND
SDA
00
10
GND
VCC
00
11
SCL
GND
01
00
SCL
SCL
01
01
SCL
SDA
01
10
SCL
VCC
01
11
SDA
GND
10
00
SDA
SCL
10
01
ADDRESS AUTO INCREMENT
SDA
SDA
10
10
SDA
VCC
10
11
VCC
GND
11
00
VCC
SCL
11
01
VCC
SDA
11
10
VCC
VCC
11
11
To write multiple bytes of data into IS31FL3743A, load
the address of the data register that the first data byte
is intended for. During the IS31FL3743A acknowledge
of receiving the data byte, the internal address pointer
will increment by one. The next data byte sent to
IS31FL3743A will be placed in the new address, and
so on. The auto increment of the address will continue
as long as data continues to be written to
IS31FL3743A (Figure 7).
010
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31FL3743A must generate another acknowledge to
indicate that the data was received.
0/1
ADDR1/2 connected to GND, (A2:A1)/(A4:A3)=00;
ADDR1/2 connected to VCC, (A2:A1)/(A4:A3)=11;
ADDR1/2 connected to SCL, (A2:A1)/(A4:A3)=01;
ADDR1/2 connected to SDA, (A2:A1)/(A4:A3)=10;
The SCL line is uni-directional. The SDA line is bidirectional (open-collector) with a pull-up resistor
(typically 400kHz I2C with 4.7kΩ, 1MHz I2C with 2kΩ).
The maximum clock frequency specified by the I2C
standard is 1MHz. In this discussion, the master is the
microcontroller and the slave is the IS31FL3743A.
The timing diagram for the I2C is shown in Figure 4.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
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The “STOP” signal ends the transfer. To signal
“STOP”, the SDA signal goes high while the SCL
signal is high.
READING OPERATION
Most of the registers can be read.
To read the FCh, FEh, after I2C start condition, the
bus master must send the IS31FL3743A device
____
address with the R/W bit set to “0”, followed by the
register address (FEh or F1h) which determines which
register is accessed. Then restart I2C, the bus master
should send the IS31FL3743A device address with
____
the R/W bit set to “1”. Data from the register defined
by the command byte is then sent from the
IS31FL3743A to the master (Figure 8).
To read the registers of Page 0 thru Page 3, the FDh
should write with 00h before follow the Figure 8
sequence to read the data. That means, when you
want to read registers of Page 0, the FDh should point
to Page 0 first and you can read the Page 0 data.
8
IS31FL3743A
Figure 4 I2C Interface Timing
Figure 5 I2C Bit Transfer
Figure 6 I2C Writing to IS31FL3743A (Typical)
Figure 7 I2C Writing to IS31FL3743A (Automatic Address Increment)
Figure 8 I2C Reading from IS31FL3743A
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IS31FL3743A
Table 2 Command Register Definition
Address
Name
Function
Table
R/W
Default
FEh
Command Register Write Lock
To unlock Command Register
4
R/W
0000 0000
FDh
Command Register
Available Page 0 to Page 2 Registers
3
W
xxxx xxxx
FCh
ID Register
For read the product ID only
Read result is the slave address
-
R
Slave
Address
REGISTER CONTROL
Table 3 FDh Command Register
Data
Function
0000 0000
Point to Page 0 (PG0, PWM Register is available)
0000 0001
Point to Page 1 (PG1, White balance Scaling Register is available)
0000 0010
Point to Page 2 (PG2, Function Register is available)
Others
Reserved
Note: FDh is locked when power up, need to unlock this register before write command to it. See Table 4 for detail.
The Command Register should be configured first after writing in the slave address to choose the available register. Then write data in the
choosing register. Power up default state is “0000 0000”.
For example, when write “0000 0001” in the Command Register (FDh), the data which writing after will be stored in the White balance Scaling
Register. Write new data can configure other registers.
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IS31FL3743A
Table 4 FEh Command Register Write Lock (Read/Write)
Bit
D7:D0
Name
CRWL
Default
0000 0000 (FDh write disable)
To select the PG0~PG2, need to unlock this register first, with the purpose to avoid mis-operation of this register.
When FEh is written with 0xC5, FDh is allowed to modify once, after the FDh is modified the FEh will reset to be
0x00 at once.
Table 5 Register Definition
Address
Name
Function
Table
R/W
Default
Set PWM for each LED
6
R/W
0000 0000
Set Scaling for each LED
7
R/W
0000 0000
PG0 (0x00): PWM Register
01h~C6h
PWM Register
PG1 (0x01): LED Scaling
01h~C6h
Scaling Register
PG2 (0x02): Function Register
00h
Configuration Register
Configure the operation mode
9
R/W
0000 0000
01h
Global Current Control
Register
Set the global current
10
R/W
0000 0000
02h
Pull Down/Up Resistor
Selection Register
Set the pull down resistor for SWx and
pull up resistor for CSy
11
R/W
0011 0011
03h~23h
Open/Short Register
Store the open or short information
12
R
0000 0000
24h
Temperature Status
Store the temperature point of the IC
13
R/W
0000 0000
25h
Spread Spectrum Register
Spread spectrum function enable
14
R/W
0000 0000
2Fh
Reset Register
Reset all register to POR state
-
W
0000 0000
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IS31FL3743A
Page 0 (PG0, FDh= 0x00): PWM Register
PWM PWM PWM
PWM PWM PWM
Figure 9 PWM Register
Table 6 PG0: 01h ~ C6h PWM Register
Bit
D7:D0
Name
PWM
Default
0000 0000
Duty
PWM
I OUT ( PEAK ) Duty
256
PWM
(1)
7
D [n ] 2
(2)
IOUT is the output current of CSy (y=1~18),
Each dot has a byte to modulate the PWM duty in
256 steps.
The value of the PWM Registers decides the
average current of each LED noted ILED.
ILED computed by Formula (1):
I LED
33s
1
1
33s 0.83s 0.3s 11 11.377
n
n 0
IOUT( PEAK)
343 GCC SL
RISET 256 256
(3)
GCC is the Global Current Control register (PG2,
01h) value, SL is the Scaling Register value as Table
9 and RISET is the external resistor of ISET pin. D[n]
stands for the individual bit value, 1 or 0, in location
n.
For example: if D7:D0=1011 0101 (0xB5, 181),
GCC=1111 1111, RISET=10kΩ, SL=1111 1111:
343
255 255
1
181
I LED
10 k 256 256 11 . 377
256
Where Duty is the duty cycle of SWx, see SCANING
TIMING section for more information.
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IS31FL3743A
Page 1 (PG1, FDh= 0x01): Scaling Register
T01
T02
SW1
T03
SW2
T04
SW3
T05
SW4
T06
SW5
T07
T08
SW7
SW6
T09
SW8
T10
T11
SW10 SW11
SW9
PWM PWM PWM
CS18
12
24
36
48
5A 6C
7E
90
A2
B4
C6
CS17
11
23
35
47
59
6B
7D
8F
A1
B3
C5
CS16
10
22
34
46
58
6A 7C
8E
A0
B2
C4
PVCC
PAGE 1
Y
X
PWM PWM PWM
CS03
CS02
CS01
03
15
27
39
4B
5D
6F
81
93
A5
B7
02
14
26
38
4A 5C
6E
80
92
A4
B6
01
13
25
37
49
6D
7F
91
A3
B5
5B
Figure 10 Scaling Register
IOUT is the output current of CSy (y=1~18), GCC is
the Global Current Control Register (PG2, 01h)
value and RISET is the external resistor of ISET pin.
D[n] stands for the individual bit value, 1 or 0, in
location n.
Table 7 PG1: 01h ~ C6h Scaling Register
Bit
D7:D0
Name
SL
Default
0000 0000
Scaling register control the DC output current of
each dot. Each dot has a byte to modulate the
scaling in 256 steps.
The value of the Scaling Register decides the peak
current of each LED noted IOUT(PEAK).
343 GCC SL
RISET 256 256
SL
SL
(3)
7
D[n] 2
n
127
n0
I OUT
IOUT(PEAK) computed by Formula (3):
IOUT( PEAK)
For example: if RISET=10kΩ, GCC=1111 1111,
SL=0111 1111:
343
255 127
16 . 8 mA
10 k 256 256
I LED 16 .8 mA
1
PWM
11 .377
256
7
D[n] 2
n
n0
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IS31FL3743A
Table 8 Page 2 (PG2, FDh= 0x02): Function Register
Register
Name
Function
Table
R/W
Default
00h
Configuration Register
Configure the operation mode
10
R/W
0000 0000
01h
Global Current Control
Register
Set the global current
11
R/W
0000 0000
02h
Pull Down/Up Resistor
Selection Register
Set the pull down resistor for SWx
and pull up resistor for CSy
12
R/W
0011 0011
03h~23h
Open/Short Register
Store the open or short information
13
R
0000 0000
24h
Temperature Status
Store the temperature point of the IC
14
R/W
0000 0000
25h
Spread Spectrum Register
Spread spectrum function enable
15
R/W
0000 0000
2Fh
Reset Register
Reset all register to POR state
-
W
0000 0000
Table 9 00h Configuration Register
Bit
D7:D4
D3
D2:D1
D0
Name
SWS
LGC
OSDE
SSD
Default
0000
0
00
0
The Configuration Register sets operating mode of
IS31FL3743A.
When OSDE set to “01”, open detection will be trigger
once, the user could trigger open detection again by
set OSDE from “00” to “01”.
Before set OSDE, the GCC should set to 0x0F, please
check OPEN/SHORT DETECT FUNCTION section for
more information.
When SSD is “0”, IS31FL3743A works in software
shutdown mode and to normal operate the SSD bit
should set to “1”. SWS control the duty cycle of the SW,
default mode is 1/11.
SSD
0
1
0111
1000
1001
1010
Others
SW1~SW4, 1/4, SW5~SW11 no-active
SW1~SW3, 1/3, SW4~SW11 no-active
SW1~SW2, 1/2, SW3~SW11 no-active
All CSx work as current sinks only, no scan
Not allowed
Table 10 01h Global Current Control Register
Bit
D7:D0
Name
GCC
Default
0000 0000
The Global Current Control Register modulates all
CSy (x=1~18) DC current which is noted as IOUT in
256 steps.
IOUT is computed by the Formula (3):
IOUT( PEAK)
Software Shutdown Control
Software shutdown
Normal operation
LGC
0
1
H/L Logic
1.4V/0.4V
2.4V/0.6V
OSDE
00/11
01
10
Open Detection Enable
Disable open/short detection
Enable open detection
Enable short detection
SWS
0000
0001
0010
0011
0100
0101
0110
SWx Setting
SW1~SW11, 1/11
SW1~SW10, 1/10, SW11 no-active
SW1~SW9, 1/9, SW10~SW11 no-active
SW1~SW8, 1/8, SW9~SW11 no-active
SW1~SW7, 1/7, SW8~SW11 no-active
SW1~SW6, 1/6, SW7~SW11 no-active
SW1~SW5, 1/5, SW6~SW11 no-active
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Rev. A, 08/06/2018
343 GCC SL
RISET 256 256
GCC
(3)
7
D[ n ] 2
n
n0
Where D[n] stands for the individual bit value, 1 or 0,
in location n.
Table 11 02h Pull Down/Up Resistor Selection
Register
Bit
D7
D6:D4
D3
D2:D0
Name
PHC
SWPDR
-
CSPUR
Default
0
011
0
011
Set pull down resistor for SWx and pull up resistor for
CSy.
Please check DE-GHOST FUNCTION section for
more information.
PHC
0
1
Phase choice
0 degree phase delay
180 degree phase delay
14
IS31FL3743A
SWPDR
SWx Pull down Resistor Selection Bit
000
No pull down resistor
001
0.5kΩ only in SWx off time
010
1.0kΩ only in SWx off time
011
2.0kΩ only in SWx off time
100
1.0kΩ all the time
101
2.0kΩ all the time
110
4.0kΩ all the time
111
8.0kΩ all the time
CSPUR
CSy Pull up Resistor Selection Bit
000
No pull up resistor
001
0.5kΩ only in CSx off time
010
1.0kΩ only in CSx off time
011
2.0kΩ only in CSx off time
100
1.0kΩ all the time
101
2.0kΩ all the time
110
4.0kΩ all the time
111
8.0kΩ all the time
Table 12 Open/Short Register (Read Only)
03h~23h Open/Short Information
Bit
D7:D6
D5:D0
Name
-
CS18:CS13,
CS12:CS07,CS06:CS01
Default
00
00 0000
When OSDE (PG2, 00h) is set to “01”, open detection
will be trigger once, and the open information will be
stored at 03h~23h.
When OSDE (PG2, 00h) set to “10”, short detection
will be trigger once, and the short information will be
stored at 03h~23h.
Before set OSDE, the GCC should set to 0x0F, please
check OPEN/SHORT DETECT FUNCTION section for
more information.
Figure 11 Open/Short Register
Table 13 24h Temperature Status
Bit
D7:D4
D3:D2
D1:D0
Name
-
TS
TROF
Default
0000
00
00
TS store the temperature point of the IC. If the IC
temperature reaches the temperature point the IC will
trigger the thermal roll off and will decrease the
current as TROF set percentage.
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Rev. A, 08/06/2018
TROF
00
01
10
11
percentage of output current
100%
75%
55%
30%
TS
00
01
10
11
Temperature Point, Thermal roll off start point
140°C
120°C
100°C
90°C
15
IS31FL3743A
Table 14 25h Spread Spectrum Register
Bit
D7:D6
D4
D3:D2
D1:D0
Name
SYNC
SSP
RNG
CLT
Default
00
0
00
00
When SYNC bits are set to “11”, the IS31FL3745 is
configured as the master clock source and the SYNC
pin will generate a clock signal distributed to the clock
slave devices. To be configured as a clock slave
device and accept an external clock input the slave
device’s SYNC bits must be set to “10’”.
When SSP enable, the spread spectrum function will
be enabled and the RNG & CLT bits will adjust the
range and cycle time of spread spectrum function.
SYNC
0x
10
11
Enable of SYNC function
Disable SYNC function, 30kOhm pull-low
Slave, clock input
Master, clock output
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SSP
0
1
Spread spectrum function enable
Disable
Enable
RNG
00
01
10
11
Spread spectrum range
±5%
±15%
±24%
±34%
CLT
00
01
10
11
Spread spectrum cycle time
1980μs
1200μs
820μs
660μs
2Fh Reset Register
Once user writes the Reset Register with 0xAE,
IS31FL3743A will reset all the IS31FL3743A registers
to their default value. On initial power-up, the
IS31FL3743A registers are reset to their default
values for a blank display.
16
IS31FL3743A
APPLICATION INFORMATION
I OUT
343 GCC SL
RISET 256 256
Figure 12 Scanning Timing
SCANING TIMING
As shown in Figure 12 above, the SW1~SW11 is
turned on by serial, LED is driven 11 by 11 within the
SWx (x=1~11) on time (SWx, x=1~11 is source and it
is high when LED on) , including the non-overlap
blanking time during scan, the duty cycle of SWx
(active high, x=1~11) is:
Duty
33s
1
1
33s 0.83s 0.3s 11 11.377
(2)
Where 33μs is tSCAN, the period of scanning and
0.83μs is tNOL, the non-overlap time and 0.3μs is the
CSx delay time.
PWM CONTROL
After setting the IOUT and GCC, the brightness of each
LEDs (LED average current (ILED)) can be modulated
with 256 steps by PWM Register, as described in
Formula (1).
I LED
PWM
I OUT ( PEAK ) Duty (1)
256
Where PWM is PWM Registers (PG0, 00h~B3h /PG1,
01h~C6h) data showing in Table 7.
For example, in Figure 1, if RISET= 10kΩ, PWM= 255,
and GCC= 255, Scaling= 255, then
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Rev. A, 08/06/2018
I OUT ( PEAK )
343
255 255
34 mA
10 k 256 256
I LED 34 mA
1
PWM
11.377
256
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
GAMMA CORRECTION
In order to perform a better visual LED breathing
effect we recommend using a gamma corrected PWM
value to set the LED intensity. This results in a
reduced number of steps for the LED intensity setting,
but causes the change in intensity to appear more
linear to the human eye.
Gamma correction, also known as gamma
compression or encoding, is used to encode linear
luminance to match the non-linear characteristics of
display. Since the IS31FL3743A can modulate the
brightness of the LEDs with 256 steps, a gamma
correction function can be applied when computing
each subsequent LED intensity setting such that the
changes in brightness matches the human eye's
brightness curve.
17
IS31FL3743A
256
Table 15 32 Gamma Steps with 256 PWM Steps
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
0
1
2
4
6
10
13
18
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
22
28
33
39
46
53
61
69
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
78
86
96
106
116
126
138
149
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
C(31)
161
173
186
199
212
226
240
255
256
224
192
PWM Data
C(0)
160
128
96
64
32
224
0
0
8
16
PWM Data
192
32
40
48
56
64
Intensity Steps
160
Figure 14 Gamma Correction (64 Steps)
128
Note: The data of 32 gamma steps is the standard value and the
data of 64 gamma steps is the recommended value.
96
OPERATING MODE
64
32
0
0
4
8
12
16
20
24
28
32
Intensity Steps
Figure 13 Gamma Correction (32 Steps)
Choosing more gamma steps provides for a more
continuous looking breathing effect. This is useful for
very long breathing cycles. The recommended
configuration is defined by the breath cycle T. When
T=1s, choose 32 gamma steps, when T=2s, choose 64
gamma steps. The user must decide the final number
of gamma steps not only by the LED itself, but also
based on the visual performance of the finished
product.
Table 16 64 Gamma Steps with 256 PWM Steps
C(0)
24
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
0
1
2
3
4
5
6
7
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
8
10
12
14
16
18
20
22
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
24
26
29
32
35
38
41
44
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
C(31)
47
50
53
57
61
65
69
73
C(32)
C(33)
C(34)
C(35)
C(36)
C(37)
C(38)
C(39)
77
81
85
89
94
99
104
109
C(40)
C(41)
C(42)
C(43)
C(44)
C(45)
C(46)
C(47)
114
119
124
129
134
140
146
152
C(48)
C(49)
C(50)
C(51)
C(52)
C(53)
C(54)
C(55)
158
164
170
176
182
188
195
202
C(56)
C(57)
C(58)
C(59)
C(60)
C(61)
C(62)
C(63)
209
216
223
230
237
244
251
255
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Rev. A, 08/06/2018
IS31FL3743Acan only operate in PWM Mode. The
brightness of each LED can be modulated with 256
steps by PWM registers. For example, if the data in
PWM Register is “0000 0100”, then the PWM is the
fourth step.
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
OPEN/SHORT DETECT FUNCTION
IS31FL3743A has open and short detect bit for each
LED.
By setting the OSD bits of the Configuration Register
(PG2, 00h) from “00” to “01” or ’10’, the LED
Open/short Register will start to store the open/short
information and after at least 2 scanning cycles and
the MCU can get the open/short information by
reading the 03h~23h, for those dots are turned off via
LED On/Off Registers (PG0, 00h~17h), the
open/short data will not get refreshed when setting the
OSD bit of the Configuration Register.
The two configurations need to set before setting the
OSD bits:
1
2
0x0F≤GCC≤0x40, 02h=0x00
0x01≤GCC≤0x40, 02h=0x30
Where GCC is the Global Current Control Register
(PG2, 01h) and both case 1 or two can get the correct
open and short information. 02h is the Pull Down/UP
Resistor Selection Register and 0x30 is to enable the
SWx pull-up function.
The detect action is one-off event and each time
before reading out the open/short information, the
OSD bit of the Configuration Register (PG3, 00h)
need to be set from “0” to “1” (clear before set
operation).
18
IS31FL3743A
DE-GHOST FUNCTION
Hardware Shutdown
The “ghost” term is used to describe the behavior of an
LED that should be OFF but instead glows dimly when
another LED is turned ON. A ghosting effect typically
can occur when multiplexing LEDs. In matrix
architecture any parasitic capacitance found in the
constant-current outputs or the PCB traces to the
LEDs may provide sufficient current to dimly light an
LED to create a ghosting effect.
The chip enters hardware shutdown when the SDB
pin is pulled low. All analog circuits are disabled
during hardware shutdown, typical the current
consume is 1.3μA.
To prevent this LED ghost effect, the IS31FL3743A
has integrated Pull down resistors for each SWx
(x=1~11) and Pull up resistors for each CSy (y=1~18).
Select the right SWx Pull down resistor (PG2, 02h)
and CSy Pull up resistor (PG2, 02h) which eliminates
the ghost LED for a particular matrix layout
configuration.
Typically, selecting the 2kΩ will be sufficient to
eliminate the LED ghost phenomenon.
The SWx Pull down resistors and CSy Pull up resistors
are active only when the CSy/SWx output working the
OFF state and therefore no power is lost through these
resistors.
SHUTDOWN MODE
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
Software Shutdown
By setting SSD bit of the Configuration Register (PG2,
00h) to “0”, the IS31FL3743A will operate in software
shutdown mode. When the IS31FL3743A is in
software shutdown, all current sources are switched
off, so that the matrix is blanked. All registers can be
operated. Typical current consume is 1.3μA.
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The chip releases hardware shutdown when the SDB
pin is pulled high. During hardware shutdown state
Function Register can be operated.
If VCC has risk drop below 1.75V but above 0.1V
during SDB pulled low, please re-initialize all Function
Registers before SDB pulled high.
LAYOUT
As described in external resistor (RISET), the chip
consumes lots of power. Please consider below
factors when layout the PCB.
1. The VCC (PVCC, AVCC) capacitors need to close to
the chip and the ground side should well connected to
the GND of the chip.
2. RISET should be close to the chip and the ground
side should well connect to the GND of the chip.
3. The thermal pad should connect to ground pins and
the PCB should have the thermal pad too, usually this
pad should have 16 or 25 via thru the PCB to other
side’s ground area to help radiate the heat. About the
thermal pad size, please refer to the land pattern of
each package.
4. The CSy pins maximum current is 34mA
(RISET=10kΩ), and the SWx pins maximum current is
larger, the width of the trace, SWx should have wider
trace then CSy.
19
IS31FL3743A
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 15 Classification Profile
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20
IS31FL3743A
PACKAGE INFORMATION
UQFN-40
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Rev. A, 08/06/2018
21
IS31FL3743A
RECOMMENDED LAND PATTERN
UQFN-40
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. User’s board manufacturing specs), user must determine suitability for use.
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Rev. A, 08/06/2018
22
IS31FL3743A
REVISION HISTORY
Revision
A
Detail Information
Initial release
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Rev. A, 08/06/2018
Date
2018.08.06
23
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