IS31FL3728
AUDIO MODULATED MATRIX LED DRIVER
June 2017
GENERAL DESCRIPTION
FEATURES
IS31FL3728 is a general purpose 8×8 LED matrix
driver which features an audio frequency equalizer
(EQ) mode or a general LED dot matrix display mode.
The general LED matrix display defaults to an 8×8
configuration, however, it can be configured for a 5×11,
6×10, 7×9 dot matrix display. The m atrix picture
brightness can be modulated by audio. In either the
audio EQ mode or matrix display mode, the array is
internally scanned, and requires only one-time
programming, thus eliminating the need for real time
system resource utilization.
It programs the LED array through I2C interface. In
the general purpose display mode, each dot of the
LED array is independently programmed on or off over
time. In the audio EQ mode, the X axis (column)
represents the frequency bands while the Y axis (row)
represents the strength of the input audio signal in
each band. The number of LEDs lit in a column is
proportional to the strength of the audio signal in the
corresponding band in a thermometer-coded manner.
IS31FL3728 is available in 24-pin QFN (4mm × 4mm).
It operates from 2.7V to 5.5V over the temperature
range of -40°C to +85°C (IS31FL3728-QFLS2-TR),
-40°C to +105°C (IS31FL3728-QFLS3-TR).
5~8 current source outputs for row control
8~11 outputs for column scan control
Programmable 8×8, 7×9, 6×10, 5×11 matrix
One-time programming, internal scan
Full scale LED current controlled by internal
register setting or audio signal
Audio frequency EQ display with programmable
input gain
LED matrix brightness can be modulated with
audio Signal
One address pin with 4 logic levels to allow four
I2C slave addresses
I2C interface
2.7V to 5.5V supply
Over-temperature protection
QFN-24 (4mm × 4mm) package
APPLICATIONS
Mobile phones and other hand-held devices for
LED displays.
Audio frequency equalizer display
TYPICAL APPLICATION CIRCUIT
Figure 1
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
Typical Application Circuit
1
IS31FL3728
PIN CONFIGURATION
Package
Pin Configuration (Top View)
QFN-24
PIN DESCRIPTION
No.
Pin
Description
1
SDA
Serial data.
2
SCL
Serial clock.
3
SDB
Shutdown the chip when pull to low.
4
IN
Audio input.
5
C_FILT
Low pass filter cap for audio control.
6
AD
I2C Address setting.
7~10, 12
R1~R5
Current source outputs.
11
VCC
Power supply.
13~15
R6/C11, R7/C10, R8/C9
CMOS outputs.
16~19,21~24
C8~C1
Current sink outputs.
20
GND
Ground.
Thermal Pad
Connect to GND.
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
2
IS31FL3728
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Order Part No.
Package
QTY/Reel
IS31FL3728-QFLS2-TR
QFN-24, Lead-free
2500
Industrial Range: -40°C to +105°C
Order Part No.
Package
QTY/Reel
IS31FL3728-QFLS3-TR
QFN-24, Lead-free
2500
Copyright © 2017 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
3
IS31FL3728
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at any input pin
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
150°C
-65°C ~ +150°C
-40°C ~ +85°C, IS31FL3728-QFLS2-TR
-40°C ~ +105°C, IS31FL3728-QFLS3-TR
32.9°C/W
±2kV
±1kV
Operating temperature range, TA = TJ
Junction to ambient, θJA
ESD (HBM) for all pins except C5
ESD (CDM)
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
The following specifications apply for VCC = 5V, TA = 25°C, unless otherwise noted.
Symbol
Parameter
VCC
Supply voltage
ICC
Quiescent power supply
current
ISD
Shutdown current
IOUT
VHR
Output current of R1~R8
Condition
Min.
Typ.
2.7
Max.
Unit
5.5
V
VIN = 0V, register CD1:CD11 = 0
dot matrix display mode without
audio modulation
4.1
5.0
mA
VSDB = 0V
1.7
5.0
μA
VSDB = 5V
Software Shutdown
1.7
5.0
μA
Dot matrix display mode without
audio modulation
42.8
(Note 1)
mA
Dot matrix display mode with
audio modulation
VIN = 1.5Vp-p, 1kHz square wave,
audio gain = 0dB
42.3
(Note 1)
mA
Current sink (ISINK, C1:C8)
ISINK = 320mA (Note 2)
headroom voltage and
current source (IOUT, R1:R8)
IOUT = 40mA
headroom voltage
300
mV
200
Logic Electrical Characteristics
VIN(0)
Logic “0” input voltage
VCC = 2.7V
VIN(1)
Logic “1” input voltage
VCC = 5.5V
IIN(0)
Logic “0” input current
VIN = 0V (Note 3)
5
nA
IIN(1)
Logic “1” input current
VIN = VCC (Note 3)
5
nA
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
0.4
1.4
V
V
4
IS31FL3728
DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 3)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
400
kHz
fSCL
Serial-clock frequency
tBUF
Bus free time between a STOP and a
START condition
1.3
μs
tHD, STA
Hold time (repeated) START condition
0.6
μs
tSU, STA
Repeated START condition setup time
0.6
μs
tSU, STO
STOP condition setup time
0.6
μs
tHD, DAT
Data hold time
tSU, DAT
Data setup time
100
ns
tLOW
SCL clock low period
1.3
μs
tHIGH
SCL clock high period
0.7
μs
0.9
μs
tR
Rise time of both SDA and SCL signals,
receiving
(Note 4)
20 + 0.1Cb
300
ns
tF
Fall time of both SDA and SCL signals,
receiving
(Note 4)
20 + 0.1Cb
300
ns
Note 1: Current of Single LED in Rx(x=1~8) is IOUT/8.
Note 2: All Row Drivers are ON.
Note 3: Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC.
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
5
IS31FL3728
DETAILED DESCRIPTION
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
I2C INTERFACE
The IS31FL3728 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with
two wires: SCL and SDA. The IS31FL3728 has a 7-bit
slave address (A6:A0). The bit A1 and bit A0 are
decided by the connection of AD pin.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the
master checks for the IS31FL3728’s acknowledge.
The master releases the SDA line high (through a
pull-up resistor). Then the master sends an SCL pulse.
If the IS31FL3728 has received the address correctly,
then it holds the SDA line low during the SCL pulse. If
the SDA line is not low, then the master should send a
“stop” signal (discussed later) and abort the transfer.
The complete slave address is:
Table 1 Slave Address (Write only)
AD Connects to
A6:A2
GND
VCC
SCL
SDA
11000
A1
A0
0
0
1
1
0
1
1
0
____
R/W
0
(write only)
Following acknowledge of IS31FL3728, the register
address byte is sent, most significant bit first.
IS31FL3728 must generate another acknowledge
indicating that the register address has been received.
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency
specified by the I2C standard is 400 kHz. In this
discussion, the master is the microcontroller and the
slave is the IS31FL3728.
Then 8 bits of data byte is sent, most significant bit
first. Each data bit should be valid while the SCL level
is stable high. After the data byte is sent, the
IS31FL3728 must generate another acknowledge
indicating that the data has been received.
The timing diagram for the I2C is shown in Figure 3.
The SDA is latched in on the stable high level of the
SCL and the SDA line should be held high when not in
use.
If the master has more data bytes to send to the
IS31FL3728, then the master can repeat the previous
two steps until all data bytes have been sent.
The “start” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
Figure 2
Writing to IS31FL3728
Figure 3
Interface Timing
Figure 4
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
The “stop” signal ends the transfer. To signal “stop”,
the SDA signal goes high while the SCL signal is high.
Bit Transfer
6
IS31FL3728
REGISTERS DEFINITION
00h Configuration Register
Bit
D7
D6:D3
D2
D1:D0
Name
SSD
-
Audio_EN
ADM
Default
0
0000
0
00
The Configuration Register sets operation mode of
IS31FL3728.
SSD
0
1
Software Shutdown Enable
Normal operation
Software shutdown mode
Audio_EN
Audio Input Enable
0
Matrix intensity is controlled by the current
setting in the Lighting Effect Register (0Dh)
1
Enable audio signal to modulate the
intensity of the matrix in dot matrix display mode
ADM
00
01
10
11
Array Mode Selection
8×8 dot matrix display mode
7×9 dot matrix display mode
6×10 dot matrix display mode
5×11 dot matrix display mode
01h~0Bh Column Data Register (C1~C11)
Bit
D7:D0
Name
R8:R1
Default
0000 0000
The column data registers store the on or off state of
each LED in the array.
Rx
0
1
LED State
LED off
LED on
The data in the column data registers is valid only
when the chip is configured in general purpose dot
matrix display mode. 11 registers are assigned to
CD1~CD11 columns respectively; the LED at a
particular (row, column) location will be turned on
when the respective data is set to 1. When configured
to other than 8×8 dot matrix display mode operation,
only the required number of LSBs is used in each
column register. For example, in 5×11 dot matrix
display mode, only bits R5 through R1 are used, and
bits R8 through R6 are ignored.
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
0Ch Update Column Register
The data sent to the column data registers will be
stored in temporary registers. A write operation of
“0000 0000” value to the Update Column Register is
required to update the Column Data Registers (01h:
0Bh).
0Dh Lighting Effect Register
Bit
D7
D6:D4
D3:D0
Name
-
AGS
CS
Default
0
000
0000
The Lighting Effect Register stores the intensity
control settings for all of the LEDs in the array
AGS
000
001
010
011
100
101
110
111
Audio Input Gain Selection
0dB
+3dB
+6dB
+9dB
+12dB
+15dB
+18dB
-6dB
CS
0000
0001
... ...
0111
1000
1001
... ...
1110
Full Current Setting For Each Row Output
40mA
45mA
75mA
5mA
10mA
35mA
0Fh Audio_EQ Register
Bit
D7
D6
D5:D0
Name
-
AE_EN
-
Default
0
0
000000
The Audio_EQ Register enables the audio frequency
equalizer (audio EQ) mode
AE_EN
0
1
Audio EQ Mode
Disable
Enable
7
IS31FL3728
APPLICATION INFORMATION
AUDIO FREQUENCY EQUALIZER (AUDIO EQ)
MODE
The IS31FL3728 features audio frequency equalizer
mode, or audio EQ mode.
The current of the matrix is adjusted by Lighting Effect
Register as dot matrix display mode.
In the audio EQ mode, only 8 columns are valid and
display the three bands of the audio signal. When the
IS31FL3728 is configured as 7×9, 6×10 or 5×11, only
columns C1 thru C8 will be used, and the remaining
columns will always be off.
Load Column data at each rising edge
32us
1us
C1
C2
C3
Cn
n=8~11
Row output
Column
data 1
Column
data 2
Figure 6
Column
data 3
Column
data n
Column
data 1
Dot Matrix Display Timing Diagram
8×8 DOT MATRIX DISPLAY MODE
Signal Strength
The application example in Figure 1 shows the
IS31FL3728 in the 8×8 LED dot matrix display mode.
The LED columns have common cathodes and are
connected to the C1:C8 outputs. The rows are
connected to the row drivers. Each of the 64 LEDs
can be addressed separately. The columns are
selected via the registers 01h~08h as described in the
registers definition section.
5×11 DOT MATRIX DISPLAY MODE
By setting D1&D0 of the Configuration Register to 11,
the IS31FL3728 will operate in the 5×11 LED dot
matrix display mode.
Figure 5
Audio EQ Mode
GENERAL PURPOSE DOT MATRIX DISPLAY MODE
The general purpose dot matrix display timing diagram
is shown in Figure 6. The IS31FL3728 is configured as
general purpose 8×8 dot matrix display mode at initial
power up. Column controls C[8:1] scans the eight
columns at a rate of 3.79KHz, or 264us per frame.
Each column is effective for 32us. The non-overlap
interval between adjacent columns is 1us.
The IS31FL3728 also can be configured as 7×9, 6×10
or 5×11 dot matrix display mode. The frame period is
changed slightly depending on the number of columns
required to scan by an additional time of 33us per
column. For example, when in 7×9 dot matrix display
mode, the column data registers’ MSB will be invalid
and column controls C[9:1] scans the nine columns
297us per frame.
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
The LED columns have common cathodes and are
connected to the C1:C11 outputs. The rows are
connected to the row drivers. Each of the 55 LEDs
can be addressed separately. The three MSBs of
each register, R8~R6, are ignored. The columns are
selected via the registers as described in the registers
definition section.
DOT MATRIX
MODULATION
DISPLAY
MODE
WITH
AUDIO
When the IS31FL3728 operates in any of the Dot
Matrix modes, if the bit Audio_EN in Configuration
register is set to 1, the panel will get the effect of
audio modulation
INITIAL POWER-UP
On initial power-up, the IS31FL3728 registers are
reset to their default values for a blank display. At this
time, all registers should be programmed for the
desired operation.
8
IS31FL3728
SOFTWARE SHUTDOWN MODE
The IS31FL3728 devices feature a software shutdown
mode, wherein they consume only 1.7μA (typ.) current.
Shutdown mode is entered via a write to the
Configuration Register. When the IS31FL3728 is in
shutdown mode, all current sources and digital drivers
are switched off, so that the array is blanked.
Shutdown mode can either be used as a means of
reducing power consumption or generating a flashing
display (repeatedly entering and leaving shutdown
mode).
Note, during shutdown mode all registers retain their
data.
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
9
IS31FL3728
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 7
Classification Profile
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
10
IS31FL3728
PACKAGE INFORMATION
QFN-24
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
11
IS31FL3728
RECOMMENDED LAND PATTERN
QFN-24
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use.
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
12
IS31FL3728
REVISION HISTORY
Revision
Detail Information
Date
A
Initial release
2011.12.19
B
1. Add S3 temperature parameters.
2. Add ESD (HBM/CDM) value and θJA.
3. Update POD.
4. Add Land pattern.
5. Deleted tape and reel information.
6. IOUT test condition changes from VIN = 1.0Vp-p to VIN = 1.5Vp-p.
7. ISD Typ. changes from 0.2 to 1.7.
8. ISD Max. changes from 1.0 to 5.0.
2016.11.15
C
1. Update θJA to 32.9°C/W
2. Update ESD (HBM) from 4kV to 2kV
2017.05.15
Lumissil Microsystems – www.lumissil.com
Rev. C, 05/15/2017
13
工商网监
湘ICP备2023018690号
