IS31FL3746A-QFLS4-TR

IS31FL3746A 24-RGB MATRIX LED DRIVER April 2021 GENERAL DESCRIPTION FEATURES The IS31FL3746A is a general purpose 18×n (n=1~4) LED Matrix programmed via 1MHz I2C compatible interface. Each LED can be dimmed individually with 8bit PWM data and 8-bit DC scaling (Color Calibration) data which allowing 256 steps of linear PWM dimming and 256 steps of DC current adjustable level.     Additionally each LED open and short state can be detected, IS31FL3746A store the open or short information in Open-Short Registers. The Open-Short Registers allowing MCU to read out via I2C compatible interface. Inform MCU whether there are LEDs open or short and the locations of open or short LEDs. Supply voltage range: 2.7V to 5.5V 18 current sinks Support 18×n (n=1~4) LED matrix configurations Accurate color rendition - 8-bit PWM - 8-bit dot correction - 8-bit global current adjust SDB rising edge reset I2C module 29kHz PWM frequency 1MHz I2C-compatible interface Individual open and short error detect function 180 degree phase delay operation to reduce power noise Spread spectrum De-ghost QFN-32 (4mm×4mm) package      The IS31FL3746A operates from 2.7V to 5.5V and features a very low shutdown and operational current.    IS31FL3746A is available in QFN-32 (4mm×4mm) package. It operates from 2.7V to 5.5V over the temperature range of -40°C to +125°C. APPLICATIONS    Hand-held devices for LED display Gaming device (Mouse, Mouse MAT etc.) IOT device (AI speaker etc.)  TYPICAL APPLICATION CIRCUIT 5V 29 VCC SW4 1μF 0.1μF *Note 3 3.3V SW3 19 SW2 VIO SW1 25 26 SW1 SW2 SW3 SW4 *Note 2 27 51Ω 28 CS18 0.1μF *Note 3 20Ω CS17 3.3V 20Ω *Note 3 3.3V CS16 2kΩ 2kΩ 23 21 Micro Controller 20 IS31FL3746A SDA SCL SDB CS18 CS17 18 51Ω 17 CS3 20Ω 100kΩ 31 22 RISET 10kΩ CS2 0.1μF 24 9 30 20Ω ISET ADDR1 CS2 ADDR2 CS1 1 CS1 32 GND Figure 1 Typical Application Circuit: 18×4, 24 RGBs Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 1 IS31FL3746A TYPICAL APPLICATION CIRCUIT (CONTINUED) 5V 29 VCC SW4 1μF 0.1μF *Note 3 3.3V SW3 19 SW2 VIO SW1 25 26 SW1 SW2 SW3 SW4 *Note 2 27 20Ω 28 CS18 0.1μF 20Ω CS17 *Note 3 3.3V *Note 3 3.3V 2kΩ 20Ω CS16 2kΩ IS31FL3746A 23 SDA 21 Micro Controller SCL 20 SDB CS18 CS17 18 20Ω 17 CS3 20Ω 100kΩ 31 22 RISET 10kΩ CS2 0.1μF 24 9 30 20Ω ISET ADDR1 CS2 ADDR2 CS1 1 CS1 32 GND Figure 2 Typical Application Circuit: 72 Mono Color LEDs Note 1: IC should be placed far away from the antenna in order to prevent the EMI. Note 2: The 20Ω or 51Ω resistors between LED and IC are only for thermal reduction, for mono red LED, if VCC=3.3V, don’t need these resistors. Note 3: The VIH of I2C bus should be same as VIO pin. VIO pin need to connect to a reference voltage and usually it is same as the VCC of MCU. If VCC of MCU is 1.8V, VIO=1.8V, if VCC of MCU is 5V, VIO=5V. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 2 IS31FL3746A PIN CONFIGURATION 25 SW4 26 SW3 27 SW2 28 SW1 29 VCC 30 GND 21 SCL CS6 5 20 SDB CS7 6 19 VIO CS8 7 18 CS18 CS9 8 17 CS17 CS16 16 CS5 4 CS15 15 22 ADDR1 CS14 14 CS4 3 CS13 13 23 SDA CS12 12 CS3 2 CS11 11 24 ADDR2 CS10 10 CS2 1 GND 9 QFN-32 31 ISET Pin Configuration (Top View) 32 CS1 Package PIN DESCRIPTION No. Pin Description 1~8, 10~18 CS2~CS18 Current sink pin for LED matrix. 9,30 GND Ground. 19 VIO Input logic reference voltage, can’t be floated. 20 SDB Shutdown pin. 21 SCL I2C compatible serial clock. 22 ADDR1 I2C address select. 23 SDA I2C compatible serial data. 24 ADDR2 I2C address select. 25~28 SW4~SW1 Power SW. 29 VCC Power for current source SW and analog. 31 ISET Set the maximum IOUT current. 32 CS1 Current sink pin for LED matrix. Thermal Pad Connect to GND. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 3 IS31FL3746A ORDERING INFORMATION Industrial Range: -40°C to +125°C Order Part No. Package QTY/Reel IS31FL3746A-QFLS4-TR QFN-32, Lead-free 2500 Copyright © 2021 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 4 IS31FL3746A ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at any input pin Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA=TJ Package thermal resistance, junction to ambient (4 layer standard test PCB based on JESD 51-2A), θJA ESD (HBM) ESD (CDM) -0.3V ~+6.0V -0.3V ~ VCC+0.3V +150°C -65°C ~+150°C -40°C ~ +125°C 52°C/W ±8kV ±750V Note 4: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS The following specifications apply for VCC= 5V, TA= 25°C, unless otherwise noted. Symbol Parameter VCC Supply voltage ICC Quiescent power supply current Conditions Min. Typ. 2.7 VSDB=VCC, all LEDs off 2.3 VSDB=0V 2.8 Max. Unit 5.5 V mA μA ISD Shutdown current VSDB= VCC, Configuration Register written “0000 0000 2.8 IOUT Maximum constant current of CSy RISET =10kΩ, GCC=0xFF SL=0xFF 34.5 mA ILED Average current on each LED ILED = IOUT(PEAK)/Duty (4.14) RISET =10kΩ, GCC=0xFF SL=0xFF 8.33 mA Current switch headroom voltage SWx ISWITCH=612mA RISET =10kΩ, GCC=0xFF, SL=0xFF 450 Current sink headroom voltage CSy ISINK=34mA, RISET =10kΩ, GCC=0xFF, SL=0xFF 250 tSCAN Period of scanning PF= “000/111” (29kHz) 33 µs tNOL1 Non-overlap blanking time during scan, the SWx and CSy are all off PF= “000/111” (29kHz) during this time 0.83 µs tNOL2 Delay total time for CS1 to CS 18, during this time, the SWx is on but CSy is not all turned on 0.3 µs VHR mV PF= “000/111” (29kHz) (Note 5) Logic Electrical Characteristics (SDA, SCL, ADDRx, SDB) VIL Logic “0” input voltage VIH Logic “1” input voltage VHYS VIO=1.8V; VIO=3.3V VIO=1.8V; VIO=3.3V 0.2VIO V 0.75VIO VIO V 0.2 V VINPUT = 0V (Note 5) 5 nA VINPUT = VIO (Note 5) 5 nA Input Schmitt trigger hysteresis VIO=3.3V IIL Logic “0” input current IIH Logic “1” input current Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 GND 5 IS31FL3746A DIGITAL INPUT I2C SWITCHING CHARACTERISTICS (NOTE 5) Fast Mode Symbol Parameter Min. Typ. Max. fSCL Serial-clock frequency tBUF Fast Mode Plus Min. Typ. Max. Units - 400 - 1000 kHz Bus free time between a STOP and a START condition 1.3 - 0.5 - μs tHD, STA Hold time (repeated) START condition 0.6 - 0.26 - μs tSU, STA Repeated START condition setup time 0.6 - 0.26 - μs tSU, STO STOP condition setup time 0.6 - 0.26 - μs tHD, DAT Data hold time - - - - μs tSU, DAT Data setup time 100 - 50 - ns tLOW SCL clock low period 1.3 - 0.5 - μs tHIGH SCL clock high period 0.7 - 0.26 - μs tR Rise time of both SDA and SCL signals, receiving - 300 - 120 ns tF Fall time of both SDA and SCL signals, receiving - 300 - 120 ns Note 5: Guaranteed by design. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 6 IS31FL3746A FUNCTIONAL BLOCK DIAGRAM  ISET SDB VCC Global Current 256 Steps VIO Bias Trim Spread Spectrum Bandgap OSC SSD Config SWX Sequence SDA SCL ADDR1 Level Shift I2C Interface PWM Counter 1 Pointer PWM PWM Counter 2 ADDR2 Scan Switch & Current Sink SW1~SW4 CS1~CS18 Scaling Pull-down Resister Selection Open/Short Ghost Eliminating GND  Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 7 IS31FL3746A DETAILED DESCRIPTION I2C INTERFACE IS31FL3746A uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS31FL3746A has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Set A0 to “0” for a write command and set A0 to “1” for a read command. The value of bits A1 and A2 are decided by the connection of the ADDRx pin. Table 1 Slave Address: ADDR2 ADDR1 GND GND GND GND SCL SCL SCL SCL SDA SDA SDA SDA VCC VCC VCC VCC GND SCL SDA VCC GND SCL SDA VCC GND SCL SDA VCC GND SCL SDA VCC A7:A5 A4:A3 A2:A1 110 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 A0 After the last bit of the chip address is sent, the master checks for the IS31FL3746A’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3746A has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. Following acknowledge of IS31FL3746A, the register address byte is sent, most significant bit first. IS31FL3746A must generate another acknowledge indicating that the register address has been received. Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3746A must generate another acknowledge to indicate that the data was received. The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. 0/1 ADDRESS AUTO INCREMENT To write multiple bytes of data into IS31FL3746A, load the address of the data register that the first data byte is intended for. During the IS31FL3746A acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS31FL3746A will be placed in the new address, and so on. The auto increment of the address will continue as long as data continues to be written to IS31FL3746A (Figure 6). ADDR1/2 connected to GND, (A2:A1)/(A4:A3)=00; ADDR1/2 connected to VCC, (A2:A1)/(A4:A3)=11; ADDR1/2 connected to SCL, (A2:A1)/(A4:A3)=01; ADDR1/2 connected to SDA, (A2:A1)/(A4:A3)=10; READING OPERATION The SCL line is uni-directional. The SDA line is bidirectional (open-drain) with a pull-up resistor (typically 400kHz I2C with 4.7kΩ, 1MHz I2C with 2kΩ). The maximum clock frequency specified by the I2C standard is 1MHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3746A. with the R/ W bit set to “0”, followed by the register address (FEh or F1h) which determines which register is accessed. Then restart I2C, the bus master should The timing diagram for the I2C is shown in Figure 3. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. Most of the registers can be read. To read the FCh, FEh, after I2C start condition, the bus master must send the IS31FL3746A device address ____ ____ send the IS31FL3746A device address with the R/ W bit set to “1”. Data from the register defined by the command byte is then sent from the IS31FL3746A to the master (Figure 7). To read the registers of Page 0 thru Page 1, the FDh should write with 00h before follow the Figure 7 sequence to read the data. That means, when you want to read registers of Page 0, the FDh should point to Page 0 first and you can read the Page 0 data. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 8 IS31FL3746A SDA tSU,DAT tLOW SCL tHD,DAT S tSU,STA tHD,STA tHIGH tSU,STO tBUF R P tHD,STA tR tF Start Condition Restart Condition Stop Condition Start Condition Figure 3 I2C Interface Timing SDA SCL Data Line Stable Data Valid Change of Data Allowed Figure 4 I2C Bit Transfer 1 2 3 A7 A6 A5 SDA SCL 4 5 6 7 8 A4 A3 A2 A1 A0 9 A 1 2 3 4 5 A7 A6 A5 A4 A3 6 7 8 A2 A1 A0 9 A 1 2 D7 D6 3 4 5 6 7 D5 D4 D3 D2 D1 8 D0 9 A P S Ack by Slave Slave Address Byte Ack by Slave Register Address Byte Ack by Slave Data Byte Stop by Master Figure 5 I2C Writing to IS31FL3746A (Typical) 1 2 3 A7 A6 A5 SDA SCL 4 5 6 7 8 A4 A3 A2 A1 A0 9 A 1 2 3 4 5 A7 A6 A5 A4 A3 6 7 8 A2 A1 A0 9 A 1 2 D7 D6 3 4 5 6 7 D5 D4 D3 D2 D1 8 D0 9 A S Start by Master Ack by Slave Slave Address Byte 9 A Ack by Slave Register Address Byte 1 2 3 4 5 D7 D6 D5 D4 D3 6 7 8 D2 D1 D0 9 A 1 2 D7 D6 Ack by Slave Data 1 Byte 3 4 5 6 7 D5 D4 D3 D2 D1 8 D0 9 A P Ack by Slave Ack by Slave Data (n-1) Byte Ack by Slave Data n Byte Stop by Master Figure 6 I2C Writing to IS31FL3746A (Automatic Address Increment) SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 Acknowledge From Slave SDA S A7 A6 S = Start Condition P = Stop Condition A5 A4 A3 A2 A1 0 6 7 8 1 2 3 4 5 Acknowledge From Slave A Register Address Byte 6 7 8 1 P S A7 A6 A5 A4 A3 A2 W A1 1 3 4 5 6 7 8 Micro Controller Acknowledge From Slave A 2 No Acknowledge From Master A Register Data Byte 1 P R Figure 7 I2C Reading from IS31FL3746A Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 9 IS31FL3746A Table 2 Command Register Definition Address Name Function Table R/W Default FEh Command Register Write Lock To unlock Command Register 4 R/W 0000 0000 FDh Command Register Available Page 0 to Page 1 registers 3 W xxxx xxxx FCh ID Register For read the product ID only; Read result is related with ADDR1/2 connection - R 101x xxx0 (Note 6) Note 6: The read result of FCh is related with ADDR1/ADDR2 connection as below table: ADDR2 ADDR1 GND GND GND D7:D5 D4:D3 D2:D1 GND 00 00 SCL 00 01 SDA 00 10 GND VCC 00 11 SCL GND 01 00 SCL SCL 01 01 SCL SDA 01 10 SCL VCC 01 11 SDA GND 10 00 101 SDA SCL 10 01 SDA SDA 10 10 SDA VCC 10 11 VCC GND 11 00 VCC SCL 11 01 VCC SDA 11 10 VCC VCC 11 11 D0 0 ADDR1/2 connected to GND, (D2:D1)/(D4:D3)=00; ADDR1/2 connected to VCC, (D2:D1)/(D4:D3)=11; ADDR1/2 connected to SCL, (D2:D1)/(D4:D3)=01; ADDR1/2 connected to SDA, (D2:D1)/(D4:D3)=10; Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 10 IS31FL3746A REGISTER CONTROL Configure Command Register (FDh) Configure Other Register (FEh, FCh) Select Response Register 0x00 0x01 Page 0 PWM Register Page 1 Scaling Register Function Register Configure Page Register Configure Page Register Configuration Register (50h-6Fh) PWM Register (Page 0, 01h~48h) Scaling Register (01h~48h) Table 3 FDh Command Register Function Data 0000 0000 Point to Page 0 (PG0, PWM Register is available) 0000 0001 Point to Page 1 (PG1, White Balance Scaling and Function Register is available) Others Reserved Note: FDh is locked when power up, need to unlock this register before write command to it. See Table 4 for detail. The Command Register should be configured first after writing in the slave address to choose the available register. Then write data in the choosing register. Power up default state is “0000 0000”. For example, when write “0000 0001” in the Command Register (FDh), the data which writing after will be stored in PG1 registers. Write new data can configure other registers. Table 4 FEh Command Register Write Lock (Read/Write) Bit D7:D0 Name CRWL Default 0000 0000 (FDh write disable) To select the PG0~PG1, need to unlock this register first, with the purpose to avoid mis-operation of this register. When FEh is written with 0xC5, FDh is allowed to modify once, after the FDh is modified the FEh will reset to be 0x00 at once. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 11 IS31FL3746A Table 5 Register Definition Address Name Function Table R/W Default 6 R/W 0000 0000 PG0 (0x00): PWM Registers 01h~48h PWM Register Set PWM for each LED PG1 (0x01): LED Scaling & Function Registers Scaling Register Set Scaling for each LED 7 R/W 0000 0000 50h Configuration Register Configure the operation mode 9 R/W 0000 0000 51h Global Current Control Register Set the global current 10 R/W 0000 0000 52h Pull Down/Up Resistor Selection Register Set the pull down resistor for SWx and pull up resistor for CSy 11 R/W 0011 0011 53h~5Eh Open/Short Register Store the open or short information 12 R 0000 0000 5Fh Temperature Status Store the temperature point of the IC 13 R/W 0000 0000 60h Spread Spectrum Register Spread spectrum function enable 14 R/W 0000 0000 8Fh Reset Register Reset all register to POR state - W 0000 0000 E0h PWM Frequency Enable Register Enable PWM frequency setting 15 W 0000 0000 E2h PWM Frequency Setting Register Set the PWM frequency 16 W 000x xxxx 01h~48h Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 12 IS31FL3746A Page 0 (PG0, FDh= 0x00): PWM Register T01 T02 T03 T04 PVCC SW1 SW2 SW3 SW4 PWM PWM PWM CS18 12 24 36 48 CS17 11 23 35 47 CS16 10 22 34 46 PAGE 0 Y X PWM PWM PWM CS03 03 15 27 39 CS02 02 14 26 38 CS01 01 13 25 37 Figure 8 PWM Register Table 6 PG0: 01h ~ 48h PWM Register Bit D7:D0 Name PWM Default 0000 0000 Duty  PWM  I OUT ( PEAK )  Duty 256 PWM  7  D[n ]  2 (2) IOUT is the output current of CSy (y=1~18), Each dot has a byte to modulate the PWM duty in 256 steps. The value of the PWM Registers decides the average current of each LED noted ILED. ILED computed by Formula (1): I LED  33s 1 1   33s  0.83  0.3s  4 4.14 n n 0 (1) I OUT ( PEAK )  343 GCC SL   RISET 256 256 (3) GCC is the Global Current Control Register (PG1, 51h) value, SL is the Scaling Register value as Table 9 and RISET is the external resistor of ISET pin. D[n] stands for the individual bit value, 1 or 0, in location n. For example: if D7:D0=1011 0101 (0xB5, 181), GCC=1111 1111, RISET =10kΩ, SL=1111 1111: I LED  343 255 255 1 181     10k 256 256 4.14 256 Where Duty is the duty cycle of SWx, Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 13 IS31FL3746A Page 1 (PG1, FDh= 0x01): Scaling Register T01 T02 T03 T04 PVCC SW1 SW2 SW3 SW4 PWM PWM PWM CS18 12 24 36 48 CS17 11 23 35 47 CS16 10 22 34 46 PAGE 1 Y X PWM PWM PWM CS03 03 15 27 39 CS02 02 14 26 38 CS01 01 13 25 37 Figure 9 Scaling Register Table 7 PG1: 01h ~ 48h Scaling Register Bit D7:D0 Name SL Default 0000 0000 IOUT is the output current of CSy (y=1~18), GCC is the Global Current Control Register (PG1, 51h) value and RISET is the external resistor of RISET pin. D[n] stands for the individual bit value, 1 or 0, in location n. Scaling register control the DC output current of each dot. Each dot has a byte to modulate the scaling in 256 steps. The value of the Scaling Register decides the peak current of each LED noted IOUT(PEAK). IOUT(PEAK) computed by Formula (3): I OUT ( PEAK )  343 GCC SL   RISET 256 256 (3) For example: if RISET=10kΩ, GCC=1111 1111, SL=0111 1111: 7 SL   D[n]  2 n  127 n 0 I OUT  343 255 127    16.8mA 10k 256 256 I LED  16.8mA  1 PWM  4.14 256 7 SL   D[n]  2 n n 0 Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 14 IS31FL3746A Table 8 Page 1 (PG1, FDh= 0x01): Function Register Name Register Function Table R/W Default 50h Configuration Register Configure the operation mode 9 R/W 0000 0000 51h Global Current Control Register Set the global current 10 R/W 0000 0000 52h Pull Down/Up Resistor Selection Register Set the pull down resistor for SWx and pull up resistor for CSy 11 R/W 0011 0011 53h~5Eh Open/Short Register Store the open or short information 12 R 0000 0000 5Fh Temperature Status Store the temperature point of the IC 13 R/W 0000 0000 60h Spread Spectrum Register Spread spectrum function enable 14 R/W 0000 0000 8Fh Reset Register Reset all register to POR state - W 0000 0000 E0h PWM Frequency Enable Register Enable PWM frequency setting 15 W 0000 0000 E2h PWM Frequency Setting Register Set the PWM frequency 16 W 000x xxxx Table 9 50h Configuration Register Bit D7:D4 D3 D2:D1 D0 Name SWS - OSDE SSD Default 0000 0 00 0 SWS control the duty cycle of the SWx, default mode is 1/4. Table 10 51h Global Current Control Register The Configuration Register sets operating mode of IS31FL3746A. SWS 0000 0001 0010 0011 Others SWx Setting SW1~SW4, 1/4 SW1~SW3, 1/3, SW4 no-active SW1~SW2, 1/2, SW3~SW4 no-active All CSy work as current sinks only, no scan SW1~SW4, 1/4 Bit D7:D0 Name GCC Default 0000 0000 The Global Current Control Register modulates all CSy (y=1~18) DC current which is noted as IOUT in 256 steps. IOUT is computed by the Formula (3): I OUT ( PEAK )  343 GCC SL   R ISET 256 256 (3) 7 OSDE 00 01/11 10 Open Short Detection Enable Disable open/short detection Enable open detection Enable short detection SSD 0 1 Software Shutdown Control Software shutdown Normal operation When OSDE set to “01”, open detection will be trigger once, the user could trigger open detection again by set OSDE from “00” to “01”. When OSDE set “10”, short detection will be trigger once, the user could trigger short detection again by set OSDE from “00” to “10”. When SSD is “0”, IS31FL3746A works in software shutdown mode and to normal operate the SSD bit should set to “1”. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 GCC   D[n]  2 n n 0 Where D[n] stands for the individual bit value, 1 or 0, in location n. Table 11 52h Pull Down/Up Resistor Selection Register Bit D7 D6:D4 D3 D2:D0 Name PHC - CSPUR Default 0 SWPD R 011 0 011 Set pull down resistor for SWx and pull up resistor for CSy. PHC 0 1 Phase Choice 0 degree phase delay 180 degree phase delay 15 IS31FL3746A 58 5B 5E 5A 5D 59 5C PWM CS01 57 PWM CS02 SW4 56 PWM CS03 SW3 55 CS04 SW2 T04 54 CS05 T03 53 CS06 PWM When OSDE (PG1, 50h) is set to “01”, open detection will be trigger once, and the open information will be stored at 53h~5Eh. When OSDE (PG1, 50h) set to “10”, short detection will be trigger once, and the short information will be stored at 53h~5Eh. Before set OSDE, the GCC should set to 0x0F~0x40 and the 52h should set to 0x00. CS07 PWM 00 0000 CS08 PWM 00 CS09 PWM Default CS10 PWM CS18:CS13, CS12:CS07,CS06:CS01 CS11 PWM - CS12 PWM Name CS13 PWM D5:D0 CS14 PWM D7:D6 CS15 PWM Bit CS16 PWM Table 12 53h~5Eh Open/Short Register (Read Only) CS17 PWM CSy Pull up Resistor Selection Bit No pull up resistor 0.5kΩ only in CSy off time 1.0kΩ only in CSy off time 2.0kΩ only in CSy off time 1.0kΩ all the time 2.0kΩ all the time 4.0kΩ all the time 8.0kΩ all the time T02 SW1 CS18 PWM CSPUR 000 001 010 011 100 101 110 111 T01 PWM SWx Pull Down Resistor Selection Bit No pull down resistor 0.5kΩ only in SWx off time 1.0kΩ only in SWx off time 2.0kΩ only in SWx off time 1.0kΩ all the time 2.0kΩ all the time 4.0kΩ all the time 8.0kΩ all the time PWM SWPDR 000 001 010 011 100 101 110 111 PVCC Figure 10 Open/Short Register Table 13 5Fh Temperature Status Bit D7:D4 D3:D2 D1:D0 Name - TS TROF Default 0000 00 00 TS store the temperature point of the IC. If the IC temperature reaches the temperature point the IC will trigger the thermal roll off and will decrease the current as TROF set percentage. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 TS Point) 00 01 10 11 Temperature Point (Thermal Roll Off Start TROF 00 01 10 11 Percentage Of Output Current 100% 75% 55% 30% 140°C 120°C 100°C 90°C 16 IS31FL3746A Table 15 E0h PWM Frequency Enable Register Table 14 60h Spread Spectrum Register Bit D7:D6 D4 D3:D2 D1:D0 Bit D7:D1 D0 Name - SSP RNG CLT Name - PFEN Default 00 0 00 00 Default 0000 000 0 When SSP enable, the spread spectrum function will be enabled and the RNG & CLT bits will adjust the range and cycle time of spread spectrum function. The PWM Frequency Enable Register enables or disables to change the PWM frequency. If PFEN= “1”, user can change the PWM frequency by modifying the E2h register. SSP 0 1 Spread Spectrum Function Enable Disable Enable PFEN PWM Frequency Enable 0 Disable 1 Enable RNG 00 01 10 11 Spread Spectrum Range ±5% ±15% ±24% ±34% Table 16 E2h PWM Frequency Setting Register CLT 00 01 10 11 Spread Spectrum Cycle Time 1980μs 1200μs 820μs 660μs 8Fh Reset Register Once user writes the Reset Register with 0xAE, IS31FL3746A will reset all the IS31FL3746A registers to their default value. On initial power-up, the IS31FL3746A registers are reset to their default values for a blank display. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 Bit D7:D5 D4:D0 Name PF - Default 000 x xxxx PWM Frequency Setting Register is used to set the PWM frequency. PF 000/111 001 010 011 100 101 110 PWM Frequency 29kHz 14.5kHz 7.25kHz 3.63kHz 1.81kHz 906Hz 453Hz 17 IS31FL3746A APPLICATION INFORMATION SW1 SW2 SW3 SW4 CS18 tNOL1=0.83µs tNOL2=0.3µs CS1 tSCAN=33µs T=136.52µs((33+0.83+0.3)×4) De-Ghost time PWM Duty is variable from 0/256~255/256 I OUT  3 4 3 GCC SL   R ISET 256 256 Figure 11 Scanning Timing SCANING TIMING As shown in Figure 11, the SW1~SW4 is turned on by serial, LED is driven 4 by 4 within the SWx (x=1~4) on time (SWx, x=1~4 is source and it is high when LED on), including the non-overlap blanking time during scan, the duty cycle of SWx (active high, x=1~4) is: Duty  33s 1 1   33s  0.83s  0.3s  4 4.14 (2) Where 33μs is tSCAN, the period of scanning, 0.83μs is tNOL1, 0.3μs is tNOL2, the non-overlap time and CSy(y=1~18) delay time. PWM CONTROL After setting the IOUT and GCC, the brightness of each LEDs (LED average current (ILED)) can be modulated with 256 steps by PWM Register, as described in Formula (1). I LED  PWM  I OUT ( PEAK )  Duty 256 (1) Where PWM is PWM Registers (PG0, 01h~48h /PG0) data showing in Table 6. For example, in Figure 1, if RISET= 10kΩ, PWM= 255, and GCC= 255, SL= 255, then 243 255 255 I OUT ( PEAK )     34mA 10k 256 256 1 PWM I LED  I OUT ( PEAK )   4.14 256 Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing effect. GAMMA CORRECTION In order to perform a better visual LED breathing effect we recommend using a gamma corrected PWM value to set the LED intensity. This results in a reduced number of steps for the LED intensity setting, but causes the change in intensity to appear more linear to the human eye. Gamma correction, also known as gamma compression or encoding, is used to encode linear luminance to match the non-linear characteristics of display. Since the IS31FL3746A can modulate the brightness of the LEDs with 256 steps, a gamma correction function can be applied when computing each subsequent LED intensity setting such that the changes in brightness matches the human eye's brightness curve. Table 17 32 Gamma Steps with 256 PWM Steps C(0) C(1) 0 1 C(8) C(9) 22 28 C(2) C(3) C(4) C(5) C(6) 2 4 6 10 13 C(10) C(11) C(12) C(13) C(14) 33 39 46 53 61 C(16) C(17) C(18) C(19) C(20) C(21) C(22) 78 86 96 106 116 126 138 C(24) C(25) C(26) C(27) C(28) C(29) C(30) 161 173 186 199 212 226 240 C(7) 18 C(15) 69 C(23) 149 C(31) 255 18 256 256 224 224 192 192 PWM Data PWM Data IS31FL3746A 160 128 96 160 128 96 64 64 32 32 0 0 4 8 12 16 20 24 28 32 0 0 8 16 Intensity Steps Figure 12 Gamma Correction (32 Steps) 0 1 C(8) C(9) 8 10 C(2) C(3) C(4) C(5) C(6) C(7) 2 3 4 5 6 7 C(10) C(11) C(12) C(13) C(14) C(15) 12 14 16 18 20 22 C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23) 24 26 29 32 35 38 41 44 C(24) C(25) C(26) C(27) C(28) C(29) C(30) C(31) 47 50 53 57 61 65 69 73 C(32) C(33) C(34) C(35) C(36) C(37) C(38) C(39) 77 81 85 89 94 99 104 109 C(40) C(41) C(42) C(43) C(44) C(45) C(46) C(47) 114 119 124 129 134 140 146 152 C(48) C(49) C(50) C(51) C(52) C(53) C(54) C(55) 158 164 170 176 182 188 195 202 C(56) C(57) C(58) C(59) C(60) C(61) C(62) C(63) 209 216 223 230 237 244 40 48 56 64 Figure 13 Gamma Correction (64 Steps) Table 18 64 Gamma Steps with 256 PWM Steps C(1) 32 Intensity Steps Choosing more gamma steps provides for a more continuous looking breathing effect. This is useful for very long breathing cycles. The recommended configuration is defined by the breath cycle T. When T=1s, choose 32 gamma steps, when T=2s, choose 64 gamma steps. The user must decide the final number of gamma steps not only by the LED itself, but also based on the visual performance of the finished product. C(0) 24 251 255 Note: The data of 32 gamma steps is the standard value and the data of 64 gamma steps is the recommended value. OPERATING MODE IS31FL3746A can only operate in PWM Mode. The brightness of each LED can be modulated with 256 steps by PWM registers. For example, if the data in PWM Register is “0000 0100”, then the PWM is the fourth step. Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing effect. OPEN/SHORT DETECT FUNCTION IS31FL3746A has open and short detect bit for each LED. By setting the OSD bits of the Configuration Register (PG1, 50h) from “00” to “01” or “10”, the LED Open/short Register will start to store the open/short information and after at least 2 scanning cycles and the MCU can get the open/short information by reading the 53h~5Eh, for those dots are turned off via LED Scaling Registers (PG1, 01h~48h), the open/short data will not get refreshed when setting the OSD bit of the Configuration Register. To get the correct open and short information, two configurations need to set before setting the OSD bits: 1 0x0F≤ GCC≤ 0x40 2 52h= 0x00 Where GCC is the Global Current Control Register (PG1, 51h) and 52h is the Pull Down/UP Resistor Selection Register and set to 0x00 is to disable the SWx pull-down and CSy pull-up function. The detect action is one-off event and each time before reading out the open/short information, the OSDE bit of the Configuration Register (PG1, 50h) need to be set from “00” to “01”/ “10” (clear before set operation). Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 19 IS31FL3746A DE-GHOST FUNCTION Hardware Shutdown The “ghost” term is used to describe the behavior of an LED that should be OFF but instead glows dimly when another LED is turned ON. A ghosting effect typically can occur when multiplexing LEDs. In matrix architecture any parasitic capacitance found in the constant-current outputs or the PCB traces to the LEDs may provide sufficient current to dimly light an LED to create a ghosting effect. The chip enters hardware shutdown when the SDB pin is pulled low. All analog circuits are disabled during hardware shutdown, typical the current consume is 2.8μA. To prevent this LED ghost effect, the IS31FL3746A has integrated Pull down resistors for each SWx (x=1~4) and Pull up resistors for each CSy (y=1~18). Select the right SWx Pull down resistor (PG1, 52h) and CSy Pull up resistor (PG1, 52h) which eliminates the ghost LED for a particular matrix layout configuration. Typically, selecting the 8kΩ will be sufficient to eliminate the LED ghost phenomenon. The SWx pull down resistors and CSy pull up resistors are active only when the CSy/SWx output working the OFF state and therefore no power is lost through these resistors. When IS31FL3746A works in hardware shutdown mode, the de-ghost function should be disabled, otherwise it will be extra about 1μA shutdown current. I2C RESET The I2C will be reset if the SDB pin is pull-high from 0V to logic high, at the operating SDB rising edge, the I2C operation is not allowed. SHUTDOWN MODE Shutdown mode can be used as a means of reducing power consumption. During shutdown mode all registers retain their data. Software Shutdown By setting SSD bit of the Configuration Register (PG1, 50h) to “0”, the IS31FL3746A will operate in software shutdown mode. When the IS31FL3746A is in software shutdown, all current sources are switched off, so that the matrix is blanked. All registers can be operated. Typical current consume is 2.8μA. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 The chip releases hardware shutdown when the SDB pin is pulled high. During hardware shutdown state Function Register can be operated. If VCC has risk drop below 1.75V but above 0.1V during SDB pulled low, please re-initialize all Function Registers before SDB pulled high. LAYOUT The IS31FL3746A consumes lots of power so good PCB layout will help improve the reliability of the chip. Please consider below factors when layout the PCB. Power Supply Lines When designing the PCB layout pattern, the first step should consider about the supply line and GND connection, especially those traces with high current, also the digital and analog blocks’ supply line and GND should be separated to avoid the noise from digital block affect the analog block. At least one 0.1μF capacitor, if possible with a 0.47μF or 1μF capacitor is recommended to connected to the ground at each power supply pins of the chip, and it needs to close to the chip and the ground net of the capacitor should be well connected to the GND plane. RISET RISET should be close to the chip and the ground side should well connect to the GND plane. Thermal Consideration The over temperature of the chip may result in deterioration of the properties of the chip. IS31FL3746A has thermal pad but the chip could be very hot if power is very large. So do consider the ground area connects to the GND pins and thermal pad. Other traces should keep away and ensure the ground area below the package is integrated, and the back layer should be connected to the thermal pad thru 9 or 16 vias to be maximized the area size of ground plane. 20 IS31FL3746A Current Rating Example For a RISET=10kΩ application, the current rating for each net is as follows: • VCC and SWx pins= 34mA ×18=612mA, recommend trace width: 0.2032mm~0.5mm. • CSy pins= 34mA, recommend trace width: 0.1016mm~0.254mm. • All other pins< 3mA, recommend trace width: 0.1016mm~0.254mm. Figure 14 Layout Example Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 21 IS31FL3746A CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 15 Classification Profile Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 22 IS31FL3746A PACKAGE INFORMATION QFN-32  Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 23 IS31FL3746A RECOMMENDED LAND PATTERN QFN-32 Note: 1. Land pattern complies to IPC-7351. 2. All dimensions in MM. 3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since land pattern design depends on many factors unknown (eg. User’s board manufacturing specs), user must determine suitability for use. Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 24 IS31FL3746A REVISION HISTORY Revision Detail Information Date 0A Initial release 2018.08.16 A Update to final version 2018.10.22 B Update Land pattern and functional block 2018.12.19 C 1. Add test condition in EC table 2. Revise Figure 11 3. Add Note 6 2021.04.08 Lumissil Microsystems – www.lumissil.com Rev. C, 04/08/2021 25