IS31FL3194-CLS2-TR

IS31FL3194 3-CHANNEL LED DRIVER WITH PROGRAMMABLE PATTERN SEQUENCING August 2017 GENERAL DESCRIPTION FEATURES IS31FL3194 is a 3-channel LED driver which features two-dimensional auto breathing mode. It has Pattern Mode and Current Level Mode for RGB lighting effects. The maximum output current can be adjusted in 4 levels (40mA Max.).   In Current Level Mode, the current level of each output can be independently programmed and controlled in 256 steps to simplify color mixing. In Pattern Mode, the timing characteristics for output current - current rising (T1), holding (T2), falling (T3) and off time (TS, TP, T4), can be adjusted individually so that each output can independently maintain a pre-established pattern achieving mixing color breathing or a single color breathing without requiring any additional interface activity, thus saving valuable system resources.  IS31FL3194 is available in WLCSP-8 (1.0mm×1.6mm) package. It operates from 2.7V to 5.5V over the temperature range of -40°C to +85°C. APPLICATIONS         2.7V to 5.5V supply voltage One group RGB/RG+W, or 3 single color LED breathing system-free pre-established pattern Each output has own independent TS~T4 and own start command (Update register) I2C interface, automatic address increment function 4 band programmable output current for each output, each band has 256 current levels Selectable gamma value for automatic breathing for each output Each pattern have 3 pre-established color Over-temperature protection Operating temperature: -40°C ~ +85°C Mobile phones and other hand-held devices for LED display LED in home appliances TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit Note: The IC should be placed far away from the mobile antenna in order to prevent the EMI. Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 1 IS31FL3194 PIN CONFIGURATION Package Pin Configuration (Top View) WLCSP-8 SDB VCC A1 A2 SDA OUT1 B1 B2 SCL OUT2 C1 C2 GND OUT3 D1 D2 PIN DESCRIPTION No. Pin Description A1 SDB Shutdown the chip when pulled to low. A2 VCC Power supply. B1 SDA I2C serial data. B2, C2, D2 OUT1~OUT3 Current source outputs. C1 SCL I2C serial clock. D1 GND Ground. Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 2 IS31FL3194 ORDERING INFORMATION Industrial Range: -40°C to +85°C Order Part No. Package QTY/Reel IS31FL3194-CLS2-TR WLCSP-8, Lead-free 3000 Copyright  ©  2017  Lumissil  Microsystems.  All  rights  reserved.  Lumissil Microsystems reserves  the  right  to  make  changes  to  this  specification  and  its  products  at  any  time  without  notice.  Lumissil  Microsystems  assumes  no  liability  arising  out  of  the  application  or  use  of  any  information,  products  or  services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and  before placing orders for products.  Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use  in such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:  a.) the risk of injury or damage has been minimized;  b.) the user assume all such risks; and  c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances  Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 3 IS31FL3194 ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at any input pin Maximum junction temperature, TJMAX Operating temperature range, TA=TJ Storage temperature range, TSTG Package thermal resistance (Mounted on JEDEC standard 4 layer (2s2p) PCB test board), θJA ESD (HBM) ESD (CDM) -0.3V ~ +6.0V -0.3V ~ VCC+0.3V +150°C -40°C ~ +85°C -65°C ~ +150°C 79.34°C/W ±2kV ±1kV Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA = -40°C ~ +85°C, VCC = 5V, unless otherwise noted. Typical value are TA = 25°C. Symbol Parameter VCC Supply voltage ICC Quiescent power supply current ISD Shutdown current IOUT VHR Condition Min. Typ. 2.7 Max. Unit 5.5 V VSDB = VCC 0.8 mA VSDB = 0V 1 2.5 VSDB = VCC, software shutdown 1 3.5 Output current Current Level mode, VDS= 0.4V CL Register= 0xFF Current band: 40mA 40 mA Current sink headroom voltage IOUT = 20mA 150 mV μA Logic Electrical Characteristics (SDA, SCL, SDB) VIL Logic “0” input voltage VCC = 2.7V VIH Logic “1” input voltage VCC = 5.5V IIL Logic “0” input current (Note 1) 5 nA IIH Logic “1” input current (Note 1) 5 nA Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 0.4 1.4 V V 4 IS31FL3194 DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 1) Symbol Parameter Condition Min. Typ. Max. Unit 400 kHz fSCL Serial-Clock frequency tBUF Bus free time between a STOP and a START condition 1.3 μs tHD, STA Hold time (repeated) START condition 0.6 μs tSU, STA Repeated START condition setup time 0.6 μs tSU, STO STOP condition setup time 0.6 μs tHD, DAT Data hold time tSU, DAT Data setup time 100 ns tLOW SCL clock low period 1.3 μs tHIGH SCL clock high period 0.7 μs tR tF Rise time of both SDA and SCL signals, receiving Fall time of both SDA and SCL signals, receiving 0.9 μs (Note 2) 20+0.1Cb 300 ns (Note 2) 20+0.1Cb 300 ns Note 1: Guaranteed by design. Note 2: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC. Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 5 IS31FL3194 DETAILED DESCRIPTION Following acknowledge of IS31FL3194, the register address byte is sent, most significant bit first. IS31FL3194 must generate another acknowledge indicating that the register address has been received. I2C INTERFACE The IS31FL3194 uses a serial bus, which conforms to the I2C protocol, to control the chip’s functions with two wires: SCL and SDA. The IS31FL3194 has a constant 7-bit slave address “101 0011” (A7:A1), followed by the R/W bit, A0. Set A0 to “0” for a write command and set A0 to “1” for a read command. Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3194 must generate another acknowledge to indicate that the data was received. The SCL line is uni-directional. The SDA line is bi-directional (open-collector) with a pull-up resistor (typically 4.7kΩ). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3194. The “STOP” signal ends the transfer. To signal “STOP”, the SDA signal goes high while the SCL signal is high. The timing diagram for the I2C is shown in Figure 2. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high. The “START” signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address. The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high. After the last bit of the chip address is sent, the master checks for the IS31FL3194’s acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3194 has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a “STOP” signal (discussed later) and abort the transfer. Figure 2 READING PORT REGISTERS To read the device data, the bus master must first ____ send the IS31FL3194 address with the R/W bit set to “0”, followed by the command byte, which determines which register is accessed. After a restart, the bus master must then send the IS31FL3194 address with ____ the R/W bit set to “1”. Data from the register defined by the command byte is then sent from the IS31FL3194 to the master (Figure 6). Interface Timing Figure 3 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 ADDRESS AUTO INCREMENT To write multiple bytes of data into IS31FL3194, load the address of the data register that the first data byte is intended for. During the IS31FL3194 acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS31FL3194 will be placed in the new address, and so on (Figure 5). Bit Transfer 6 IS31FL3194 Figure 4 Figure 5 Writing to IS31FL3194 (Typical) Writing to IS31FL3194 (Automatic Address Increment) Figure 6 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 Reading from IS31FL3194 7 IS31FL3194 Table 1 Registers Definitions Address Name Function R/W Table Default 00h Product ID For read only, read result is 0xCE R - 1100 1110 01h Operating Configure Register Set software shutdown mode and operation mode W 2 0000 0000 02h Output Enable Register Output enable bit W 3 0000 0111 03h Current Band Register Set current band of each Output W 4 0001 0101 04h Hold Function Register Set the hold function of each Output W 5 0000 0000 For reading the pattern running state R 6 0000 0000 OUT1/OUT2/OUT3 Current Level Register Output current level data register W 7 0000 0000 10h~12h/ 20h~22h/ 30h~32h Color 1 Setting Register of P1/P2/P3 Output current level data register-Color 1 W 8 0000 0000 13h~15h/ 23h~25h/ 33h~35h Color 2 Setting Register of P1/P2/P3 Output current level data register-Color 2 W 9 0000 0000 16h~18h/ 26h~28h/ 36h~38h Color 3 Setting Register of P1/P2/P3 Output current level data register-Color 3 W 10 0000 0000 19h/29h/39h P1/P2/P3 TS &T1 Setting Register Set the TS~T1 time W 11 0000 0000 1Ah/2Ah/3Ah P1/P2/P3 T2 &T3 Setting Register Set the T2~T3 time W 12 0000 0000 1Bh/2Bh/3Bh P1/P2/P3 TP &T4 Setting Register Set the TP~T4 time W 13 0000 0000 1Ch/2Ch/3Ch P1/P2/P3 Color Enable Register Set the color enable/disable W 14 0000 0001 W 15 0000 0000 0Dh/0Eh/0Fh P1/P2/P3 State Register 10h/21h/32h 1Dh/2Dh/3Dh P1/P2/P3 Color Cycle Times Register Set color repeat time 1Eh/2Eh/3Eh P1/P2/P3 NXT Register Set next step and Gamma of each pattern W 1Fh/2Fh/3Fh P1/P2/P3 Loop Times Register Set the loop time of P1~P3 W Update color data W Update the time data and start to run pattern W Reset the registers value to default W 40h Color Update Register 41h/42h/43h P1/P2/P3 Update Register 4Fh Reset Register 16~18 0000 0001 19 0000 0000 - - Note: When T1 or T3= 0.03s, GAM will be set to 10 (Linearity). Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 8 IS31FL3194 Table 5 04h Hold Function Register Table 2 01h Operating Configure Register Bit D7 D6:D4 D3 D2:D1 D0 Bit D7:D6 Name - OUT3:OUT1 - RGB SSD Name - Default - 000 - 00 0 Default 00 D5 D4 D3 D2 D1 D0 HF3 HT3 HF2 HT2 HF1 HT1 0 0 0 0 0 0 The Operating Configure Register sets software shutdown and operation modes of IS31FL3194. The Hold Function Register configures hold time for each output in Pattern Mode. SSD 0 1 Software Shutdown Enable Software shutdown mode Normal operation RGB 00/11 01 10 LED Mode Single mode RG+W mode, OUT1 and OUT2 work together, OUT3 work independent RGB mode, three outputs work together HTx Hold Time Selection 0 Hold at end of T4 when pattern loop done (always off) 1 Hold at end of T2 when pattern loop done (always on) OUTx 0 1 Output Operating Mode Current Level Mode Pattern Mode Bit D7:D3 D2:D0 Name - EN3:EN1 Default 00000 111 Output Enable Control Output disable Output enable Table 4 03h Current Band Register Bit D7:D6 D5:D4 D3:D2 D1:D0 Name - CB3 CB2 CB1 Default 00 01 01 01 The Current Setting Register stores the current band of each LED output. Current Band Setting Band 1: 0mA~10mA, IMAX=10mA Band 2: 0mA~20mA, IMAX=20mA Band 3: 0mA~30mA, IMAX=30mA Band 4: 0mA~40mA, IMAX=40mA Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 Bit D7 Name PSx Default 0 D6 P1/P2/P3 State Register D5 D4 CS3x CS2x CS1x 0 0 0 D3 D2:D0 - TXx 0 000 ODh is the state of Pattern 1, PS is the pattern enable or not, CSX is the color enable or not, TX will show the running position of Pattern 1. OEh and OFh store the state of Pattern 2 and 3. The Output Enable Register enables/disables the outputs independently. CBx 00 01 10 11 Hold Function Enable Hold function disable Hold function enable Table 6 0Dh/0Eh/0Fh (Read Only) Table 3 02h Output Enable Register ENx 0 1 HFx 0 1 TXx 000 001 010 011 100 101 Time state Running at TS Running at T1 Running at T2 Running at T3 Running at TP Running at T4 CSXx 0 1 Color State Running at Color x Running at Color x PSx 0 1 Pattern State Running at Pattern x Running at Pattern x 9 IS31FL3194 Table 7 10h/21h/32h OUT1/OUT2/OUT3 Current Level Register Bit D7:D0 Name CL Default 0000 0000 When IS31FL3194 operates in Current Level Mode, the value of Current Level Registers will decide the output current of OUTx in 256 levels. The output current may be computed using the Formula (1): I OUT 7 I  MAX   D[n] * 2 n 256 n0 (1) Where D[n] stands for the individual bit value, 1 or 0, in location n. For example: if D7:D0 = 10110101, IOUT = IMAX (27+25+24+22+20)/256 IMAX is set by Current Band Register. 26h~28h Color 3 Setting Register of P2 D7:D0 Name P1COL1_Ox Default 0000 0000 13h~15h Color 2 Setting Register of P1 Bit D7:D0 Name P1COL2_Ox Default 0000 0000 16h~18h Color 3 Setting Register of P1 D7:D0 Name P2COL3_Ox Default 0000 0000 Table 10 30h~32h Color 1 Setting Register of P3 Bit D7:D0 Name P3COL1_Ox Default 0000 0000 33h~35h Color 2 Setting Register of P3 Bit D7:D0 Name P3COL2_Ox Default 0000 0000 36h~38h Color 3 Setting Register of P3 Table 8 10h~12h Color 1 Setting Register of P1 Bit Bit Bit D7:D0 Name P3COL3_Ox Default 0000 0000 Color Setting Registers store the color setting for each output in Pattern Mode. Check Pattern Color Setting section for more information about the color setting registers. Need to write Color Update Register (40h) to update the data. Table 11 19h/29h/39h P1/P2/P3 TS &T1 Setting Register Bit D7:D3 D4:D0 P1COL3_Ox Name T1 TS 0000 0000 Default 0000 0000 Bit D7:D0 Name Default Table 9 20h~22h Color 1 Setting Register of P2 Bit D7:D0 Name P2COL1_Ox Default 0000 0000 23h~25h Color 2 Setting Register of P2 Bit D7:D0 Name P2COL2_Ox Default 0000 0000 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 The TS & T1 Setting Registers set the TS and T1 time in Pattern Mode. TS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Pattern Start Time Selection 0.03s 0.13s 0.26s 0.38s 0.51s 0.77s 1.04s 1.60s 2.10s 2.60s 3.10s 4.20s 10 IS31FL3194 1100 1101 1110 1111 5.20s 6.20s 7.30s 8.30s T1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Rise Time Selection 0.03s 0.13s 0.26s 0.38s 0.51s 0.77s 1.04s 1.60s 2.10s 2.60s 3.10s 4.20s 5.20s 6.20s 7.30s 8.30s T3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 13 1Bh/2Bh/3Bh P1/P2/P3 TP &T4 Setting Register Table 12 1Ah/2Ah/3Ah P1/P2/P3 T2 &T3 Setting Register Bit D7:D3 D4:D0 Name T3 T2 Default 0000 0000 The T2 & T3 Setting Registers set the T2 and T3 time in Pattern Mode. T2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Fall Time Selection 0.03s 0.13s 0.26s 0.38s 0.51s 0.77s 1.04s 1.60s 2.10s 2.60s 3.10s 4.20s 5.20s 6.20s 7.30s 8.30s Hold Time Selection 0.03s 0.13s 0.26s 0.38s 0.51s 0.77s 1.04s 1.60s 2.10s 2.60s 3.10s 4.20s 5.20s 6.20s 7.30s 8.30s Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 Bit D7:D3 D4:D0 Name T4 TP Default 0000 0000 The TP & T4 Setting Registers set the TP and T4 time in Pattern Mode. TP 0000 0001 0010 0011 0100 0101 0110 0111 (1000 1001 1010 1011 1100 1101 1110 1111 Time between Pulses 0.03s 0.13s 0.26s 0.38s 0.51s 0.77s 1.04s 1.60s 2.10s 2.60s 3.10s 4.20s 5.20s 6.20s 7.30s 8.30s 11 IS31FL3194 T4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 16 1Eh P1 NXT Register Off Time Selection 0.03s 0.13s 0.26s 0.38s 0.51s 0.77s 1.04s 1.60s 2.10s 2.60s 3.10s 4.20s 5.20s 6.20s 7.30s 8.30s D3:D2 D1:D0 Name MTPLT1 GAM1 NXT1 Default 0000 00 01 NXT1 Pattern 1 Next 00/10/11 Just stop 01 Go to Pattern 2 (Only effective in RGB & RG+W Mode) Bit D7:D3 D2 D1 D0 Name - CE3 CE2 CE1 Default 00000 0 0 1 Color Enable Register enables the color function for each color in Pattern Mode. Color Enable Selection Color x disable Color x enable Table 15 1Dh/2Dh/3Dh P1/P2/P3 Color Cycle Times Register Bit D7:D6 D5:D4 D3:D2 D1:D0 Name - CCT3 CCT2 CCT1 Default 00 00 00 00 Color Cycle Times Register sets Color loop times for each color. CCTx 00 01 10 11 D7:D4 NXT1 defines next operation when Pattern 1 is done. GAM1 controls the gamma of Pattern 1. MTPLT1 controls the loop of Pattern 1. Table 14 1Ch/2Ch/3Ch P1/P2/P3 Color Enable Register CEx 0 1 Bit Color Cycle Times Selection Endless 1 time 2 times 3 times Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 GAM1 00/11 01 10 Gamma Selection Gamma=2.4 Gamma=3.5 Linearity MTPLT1 0000 0001 … 1111 Multy-Pulse loop time endless 1 time 15 times Table 17 2Eh P2 NXT Register Bit D7:D4 D3:D2 D1:D0 Name MTPLT2 GAM2 NXT2 Default 0000 00 01 NXT2 defines next operation when Pattern 2 is done. GAM2 controls the gamma of Pattern 2. MTPLT2 controls the loop of Pattern 2. NXT 2 Pattern 2 Next 00/11 Just stop 01 Go to Pattern 1 (Only effective in RGB & RG+W Mode) 10 Go to Pattern 3 (Only effective in RGB Mode) GAM2 00/11 01 10 Gamma Selection Gamma=2.4 Gamma=3.5 Linearity 12 IS31FL3194 MTPLT2 0000 0001 … 1111 Table 19 1Fh/2Fh/3Fh P1/P2/P3 Loop Times Register Multy-Pulse loop time endless 1 time 15 times Table 18 3Eh P3 NXT Register Bit D7:D4 D3:D2 D1:D0 Name MTPLT3 GAM3 NXT3 Bit D7 D6:D0 Name PLTx_H PLTx_L Default 0 000 0000 If PLTx_H(D7)=0, PLTx_L!=0 Pattern loop times 6 Default 0000 00 01 NXT3 defines next operation when Pattern 3 is done. GAM3 controls the gamma of Pattern 3. MTPLT3 controls the loop of Pattern 3. LoopTime   D[n] * 2n (2) (3) n 0 If PLTx_H(D7)=0, PLTx_L=0, endless If PLTx_H(D7)=1, PLTx_L!=0 Pattern loop times 6 LoopTime  16   D[n] * 2n (3) NXT 3 00/11 01 Mode) 10 Mode) Pattern 3 Next Just stop Go to Pattern 1 (Only effective in RGB GAM3 00/11 01 10 Gamma Selection Gamma=2.4 Gamma=3.5 Linearity MTPLT3 0000 0001 … 1111 Multy-Pulse loop time endless 1 time Write 0xC5 to these registers will update the time parameters of Pattern x, and start to run Pattern x. Note, for RG+W Mode, when write 0xC5 to P3 Update Register (43h), all the P1, P2 and P3 time parameters will be updated. 15 times 4Fh Reset Register Go to Pattern 2 (Only effective in RGB n0 If PLTx_H(D7)=1, PLTx_L=0, endless Where D[n] stands for the individual bit value. 40h Color Update Register Write 0xC5 to 40h will update the data of 10h~18h/20h~28h/30h~38h 41h/42h/43h P1/P2/P3 Update Register Once user writes “0xC5” to the Reset Register, IS31FL3194 will reset all registers to their default value. On initial power-up, the IS31FL3194 registers are reset to their default values for a blank display. Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 13 IS31FL3194 TYPICAL APPLICATION INFORMATION GENERAL DESCRIPTION IS31FL3194 is a 3-channel LED driver which features two-dimensional auto breathing mode. It has Pattern Mode and Current Lever Mode for RGB lighting effects. POWER ON SEQUENCE IS31FL3194 provides a power-on reset feature that is controlled by VBAT supply voltage. When the VBAT supply voltage exceeds 2.4V (TBD), the internal circuit starts to work. The reset signal will be generated to perform a power-on reset (POR) operation, which will reset all control circuits and configuration registers until the internal power voltage become stable. Before SDB pull high, the I2C operation is allowed. The SDB rising edge will reset the I2C bus. steps independently. For example, if the data in Current Lever Register is “0000 0100”, then the current lever is the fourth step, with a current level of 4/256. In Current Lever Mode, user doesn’t need to turn on the CEx of 1Ch/2Ch/3Ch, a new value must be written to the Current Lever registers to change the output current. Writing new data continuously to the registers can modulate the brightness of the LEDs to achieve a breathing, blinking, or any other effects that the user defines. PATTERN MODE By setting the OUTx bits of the Operating Configure Register (01h) to “1”, the corresponding OUTx will operate in Pattern Mode. In Pattern Mode, the timing characteristics for output current – current rising (T1), holding (T2), falling (T3) and off time (TS, TP, T4), can be adjusted individually so that each output can independently maintain a pre-established pattern achieving mixing color breathing or a single color breathing without requiring any additional interface activity, thus saving valuable system resources. PATTERN COLOR SETTING Figure 7 SDB Pin Sequence Note 1: I2C operation is allowed when SDB is low. Note 2: There should be no I2C operation 10µs before and after SDB rinsing edge. In some case, like a mouse, when plug-out and quickly plug-in back the USB power, the LED will flicker for a very short time. The reason is the power is not lower than the POR voltage point (usually lower than 2.2V), and the device still stores the previous setting data, if user pull-up the SDB high when power up, following with the initial operation, the LED will be ON between SDB rising edge and Current Level initial effective, to avoid this, as above figure, a writing to 01h is recommended to shutdown the chip before pull-high the SDB pin. CURRENT LEVEL MODE There are four programmed current bands can be set by the Current Band Register (03h). It is used to set the global maximum of each output current, IMAX. By setting the OUTx bits of the Operating Configure Register (01h) to “0”, the corresponding OUTx will operate in Current Lever Mode. The Current Lever Registers (10h, 21h, 32h) are active and can modulate LED brightness of each output with 256 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 In Pattern Mode, the LED color is defined by PxCOLy_Oz (x,y,z= 1,2,3) bits in Color Setting Registers (10h~18h, 20h~28h, 30h~38h). There are 3 RGB current combinations to generate 3 pre-defined colors for display. More than one of the 3 pre-defined colors can be chosen by setting Cex bits in Color Enable Register (1Ch/2Ch/3Ch). When Cex is set, the color x is allow to be displayed in current pattern. Table 20~22 show the registers for each mode, for example, in the Current Level Mode, the current lever register is 10H for OUT1, 21H for OUT2, 32H for OUT3, in Single mode and pattern mode, Pattern 1 has 3 current level registers and enabled/disabled by Cex. Table 20 Color Register Of Single Mode Color P1 P2 P3 Mode Enable OUT1 OUT2 OUT3 Single Mode CE1 10H 21H 32H Pattern Mode CE2 13H 24H 35H CE3 16H 27H 38H Current Level Mode - 10H 21H 32H 14 IS31FL3194 GAMMA CORRECTION Table 21 Color Register Of RG+W Mode RG+W Mode Pattern 1 Pattern 2 Color Enable OUT1 OUT2 CE1(1Ch) 10H 11H CE2(1Ch) 13H 14H CE3(1Ch) 16H 17H CE1(2Ch) 20H 21H CE2(2Ch) 23H 24H CE3(2Ch) 26H 27H RG+W Mode Pattern Mode Color Enable P3 OUT3 CE1(3Ch) 32H CE2(3Ch) 35H CE3(3Ch) 38H - 32H Current Level Mode Table 22 Color Register of RGB Mode RGB Color OUT1 OUT2 Mode Enable Pattern 1 Pattern 2 Pattern 3 In order to perform a better visual LED breathing effect, the device integrates gamma correction to the Pattern Mode. The gamma correction causes the change in intensity to appear more linear to the human eye. Gamma correction, also known as gamma compression or encoding, is used to encode linear luminance to match the non-linear characteristics of display. Since the IS31FL3194 can modulate the brightness of the LEDs with 256 steps, a gamma correction function can be applied when computing each subsequent LED intensity setting such that the changes in brightness matches the human eye’s brightness curve. The IS31FL3194 provides three gamma corrections which can be set by GAM bits of NXT Registers (1Eh/2Eh/3Eh) for each pattern. The gamma correction is shown as below. OUT3 CE1(1Ch) 10H 11H 12H CE2(1Ch) 13H 14H 15H CE3(1Ch) 16H 17H 18H CE1(2Ch) 20H 21H 22H CE2(2Ch) 23H 24H 25H CE3(2Ch) 26H 27H 28H CE1(3Ch) 30H 31H 32H CE2(3Ch) 33H 34H 35H CE3(3Ch) 36H 37H 38H Figure 8 Gamma Correction PATTERN TIME SETTING User should configure the related pattern time setting registers according to actual timing requirements via I2C interface before starting pattern. There are three groups of pattern time can be set for P1~P3, which including TS, T1~T4 and TP. And each pattern has three continue lighting cycle as Color 1~Color 3. Please check the LED OPERATING MODE section for more about the time setting. Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 15 IS31FL3194 LED OPERATING MODE The IS31FL3194 has three operating modes which can be chosen by the RGB bits of Operating Configure Register (01h). Pattern Mode Run Pattern 1 Current Level Mode 256 Steps Pattern Mode Run Pattern 2 Current Level Mode 256 Steps Pattern Mode Run Pattern 3 Current Level Mode 256 Steps Pattern Mode Run Pattern 1 & Pattern 2 Pattern Mode Run Pattern 3 Current Level Mode 256 Steps Pattern Mode Run Pattern 1 & Pattern 2 & Pattern 3 OUT1 Single Mode OUT2 OUT3 OUT1 & OUT2 Device Operation RG+W Mode OUT3 RGB Mode Figure 9 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 OUT1 & OUT2 & OUT3 Three Operating Mode Map 16 IS31FL3194 Single Mode: If RGB=00/11 (Single Mode), OUTx runs Px independently in Pattern Mode or operates in Current Level Mode. Figure 10 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 Single Mode 17 IS31FL3194 RG+W Mode: If RGB=01 (RG+W Mode), OUT1 and OUT2 can operate in Pattern Mode only and run in the same pattern (P1~P2). OUT3 can be both mode and run in Pattern 3 independently. OUT1 and OUT2 bits can’t be set. Figure 11 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 RG+W Mode 18 IS31FL3194 RGB Mode: If RGB=10 (RGB Mode), OUT1~OUT3 can operate in Pattern Mode only and run in the same pattern (P1~P3). OUTx bit can’t be set. RGB Mode OUT1 OUT2 OUT3 TS PLT1 PLT2 PLT3 Pattern1 T1 T4 Pattern2 T1 T4 Pattern3 T1 T4 TS STOP TS STOP STOP Pattern3 PLT3 MTPLT3 TS T1 CCT1 CCT2 CCT3 Color1 Color2 Color3 TP T1 TP T1 TP T4 STOP Color 3 Gamma 1.0 (Linearity) Gamma 2.4 Gamma 3.5 T1 T2 T3 TP CCT3 Figure 12 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 RGB Mode 19 IS31FL3194 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 13 Classification Profile Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 20 IS31FL3194 PACKAGE INFORMATION WLCSP-8 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 21 IS31FL3194 RECOMMENDED LAND PATTERN Note: 1. Land pattern complies to IPC-7351. 2. All dimensions in MM. 3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since land pattern design depends on many factors unknown (eg. User’s board manufacturing specs), user must determine suitability for use. Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 22 IS31FL3194 REVISION HISTORY Revision Detail Information Date 0A Initial release 2017.03.02 A Update to final version 2017.07.04 B 1. Update title 2. Add package size 3. Add description for 43h register 2017.08.04 Lumissil Microsystems – www.lumissil.com Rev. B, 08/04/2017 23