FT24C1024A-USR-T

Fremont Micro Devices FT24C1024A Two-Wire Serial EEPROM 1024K ( 8-bit wide ) FEATURES              Low voltage and low power operations:  FT24C1024A: VCC = 1.8V to 5.5V 256 bytes page write mode. Partial page write operation allowed. Internally organized: 131,072 X 8 (1024K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed programming cycle (5ms maximum). Automatic erase before write operation. Write protect pin for hardware data protection. High reliability: typically 1,000,000 cycles endurance. 40 years data retention. Industrial temperature range (-40o C to 85o C). Standard 8-pin DIP/SOP Pb-free packages. DESCRIPTION The FT24C1024A series are 1,048,576 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 131,072 words of 8 bits (one byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, and 8-lead SOP packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. PIN CONFIGURATION Pin Name A2, A1 SDA SCL WP NC Pin Function Device Address Inputs Serial Data Input / Open Drain Output Serial Clock Input Write Protect No-Connect © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page1 Fremont Micro Devices FT24C1024A All three packaging types come in Pb-free certified. NC A1 A2 GND 1 8 2 7 3 6 4 5 VCC WP SCL SDA 8L DIP 8L SOP ABSOLUTE MAXIMUM RATINGS Industrial operating temperature: Storage temperature: Input voltage on any pin relative to ground: Maximum voltage: ESD Protection on all pins -40oC to 85oC -50oC to 125oC -0.3V to VCC + 0.3V 8V >2000V * Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page2 Fremont Micro Devices FT24C1024A PIN DESCRIPTIONS (A) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (B) DEVICE / CHIP SELECT ADDRESSES (A2, A1) These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL. (C) SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP) The FT24C1024A device has a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level. MEMORY ORGANIZATION The FT24C1024A devices have 512 pages respectively. Since each page has 256 bytes, random word addressing to FT24C1024A will require 17 bits data word addresses. DEVICE OPERATION (A) SERIAL CLOCK AND DATA TRANSITIONS The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITION With SCL VIH, a SDA transition from high to low is interpreted as a START condition. commands must begin with a START condition. All valid (C) STOP CONDITION With SCL VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish (see Figure 1). (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page3 Fremont Micro Devices FT24C1024A (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation. Figure 1: Timing diagram for START and STOP conditions SCL SDA START Condition Data Valid Data Transition STOP Condition Figure 2: Timing diagram for output ACKNOWLEDGE START Condition SCL Data in Data out ACK DEVICE ADDRESSING The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next two bits are device address bits. These two device address bits (5th and 6th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th and 6th ) as noted below. The seventh bit of the device address (P0) is a memory page address bit. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page4 Fremont Micro Devices FT24C1024A WRITE OPERATIONS (A) BYTE WRITE A write operation requires the seventh bit of the device address (P0) and two 8-bit data word address following the device address word and ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters into an internallytimed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (figure 3). (B) PAGE WRITE The 1024K EEPROM are capable of 256-byte page write. A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition after the first data word is clocked in. The microcontroller can transmit up to 255 more data words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is received. The microcontroller must terminate the page write sequence with a STOP condition (see Figure 4). The lower 8 bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be overwritten. (C) ACKNOWLEDGE POLLING ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle. READ OPERATIONS The read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) CURRENT ADDRESS READ The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the microcontroller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode (see Figure 5). (B) SEQUENTIAL READ The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page5 Fremont Micro Devices FT24C1024A Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the microcontroller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead (figure 6). (C) RANDOM READ Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send two address words. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address (figure 7). Figure 3: Byte Write S T A R T DEVICE ADDRESS W R I T E FIRST WORD ADDRESS SECOND WORD ADDRESS S T O P DATA SDA LINE RA P / C 0 WK M S B M S B A C K LA SC BK A C K Figure 4: Page Write S T A R T DEVICE ADDRESS W R I T E FIRST WORD ADDRESS(N) SECOND WORD ADDRESS(N) S T O DATA(N+X) P DATA(N) ... SDA LINE M S B RA P / C 0 WK © 2012 Fremont Micro Devices Inc. M S B A C K LA SC BK A C K A C K DS24C1024-A0--page6 Fremont Micro Devices FT24C1024A Figure 5: Current Address Read S T A R T R E A D DEVICE ADDRESS S T O P DATA LRA S / C B WK M S B N O A C K Figure 6: Sequential Read DEVICE ADDRESS R E A D DATA (N) DATA (N+1) DATA (N+2) S T O P DATA (N+3) SDA LINE RA / C WK A C K A C K N O A C K A C K Figure 7: Random Read S T A R T DEVICE ADDRESS W R I T E FIRST WORD ADDRESS(N) SECOND WORD ADDRESS(N) S T A R T DEVICE ADDRESS R E A D S T O P DATA (N) SDA LINE M S B RA P / C 0 WK A C K L A S C B K M S B LRA S / C B WK N O A C K © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page7 Fremont Micro Devices FT24C1024A Figure 8: SCL and SDA Bus Timing t HIGH tF tR tLOW SCL t SU,STA tLOW t HD.STA t HD.DAT t SU.STO t SU.DAT SDA IN t AA t DH t BUF SDA OUT AC CHARACTERISTICS Symbol FT24C 1024A FT24C 1024A FT24C 1024A 1.8 V 2.5 V 5.5 V Parameter Min fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Clock frequency, SCL Max Min 400 Max Min 400 Unit Max 400 kHz Clock pulse width low Clock pulse width high Noise suppression time Clock low to data out valid Time the bus must be free before a new transmission can start START hold time 1.3 1.3 1.3 µs 0.6 0.6 0.6 µs START set-up time Data in hold time Data in set-up time 100 0.1 0.9 50 0.1 0.9 0.1 50 ns 0.9 µs 1.3 1.3 1.3 µs 0.6 0.6 0.6 µs 0.6 0.6 0.6 µs 0 0 0 µs 100 100 100 ns Input rise time 0.3 0.3 0.3 µs Input fall time 300 300 300 ns STOP set-up time 0.6 0.6 0.6 µs Date out hold time 50 50 50 ns Write cycle time © 2012 Fremont Micro Devices Inc. 5 5 5 ms DS24C1024-A0--page8 Fremont Micro Devices FT24C1024A DC CHARACTERISTICS Symbol Parameter VCC1 ICC1 ICC2 supply VCC Supply read current Supply write current ISB1 Supply current ISB2 Supply current ISB3 Supply current Test Conditions Min Max Units 0.5 2.0 5.5 1.0 3.0 V mA mA 1.8 VCC @ 5.0V SCL = 400 kHz VCC @ 5.0V SCL = 400 kHz VCC @ 1.8V, VIN = VCC or VSS VCC @ 2.5V, VIN = VCC or VSS VCC @ 5.0V, VIN = VCC or VSS ILO Input leakage current Output leakage current VIL Input low level -0.6 VIH Input high level VCC × 0.7 VOL2 VOL1 Output low level Output low level IIL Typical < 1.0 µA < 1.0 µA < 1.0 µA VIN = VCC or VSS 3.0 µA VIN = VCC or VSS 3.0 µA VCC × 0.3 V VCC @ 3.0V, IOL = 2.1 mA VCC @ 1.8V, IOL = 0.15 mA © 2012 Fremont Micro Devices Inc. VCC + 0.5 0.4 0.2 V V V DS24C1024-A0--page9 Fremont Micro Devices FT24C1024A ORDER INFORMATION FT24C1024A - X X X - X Circuit Type Packaging B: Tube T: Tape and Reel Temp. Range U: -40℃-85℃ HSF R: RoHS G: Green Package D: DIP8 S: SOP8 Density 1024 kbits Package Temperature Range Vcc HSF Packaging Ordering Code DIP8 -40℃-85℃ 1.8V-5.5V RoHS Green Tube Tube Tube Tape and Reel Tube Tape and Reel FT24C1024A-UDR-B FT24C1024A-UDG-B FT24C1024A-USR-B FT24C1024A-USR-T FT24C1024A-USG-B FT24C1024A-USG-T RoHS SOP8 -40℃-85℃ 1.8V-5.5V Green © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page10 Fremont Micro Devices FT24C1024A DIP8 PACKAGE OUTLINE DIMENSIONS Symbol A A1 A2 B B1 C D E E1 e L E2 Dimensions In Millimeters Dimensions In Inches Min Max Min Max 3.710 0.510 3.200 0.380 4.310 0.146 0.020 0.126 0.015 0.170 3.600 0.570 1.524（BSC） 0.204 0.360 9.000 9.400 6.200 6.600 7.320 7.920 2.540 (BSC) 3.000 3.600 8.400 9.000 © 2012 Fremont Micro Devices Inc. 0.142 0.022 0.060（BSC） 0.008 0.014 0.354 0.370 0.244 0.260 0.288 0.312 0.100（BSC） 0.118 0.142 0.331 0.354 DS24C1024-A0--page11 Fremont Micro Devices FT24C1024A SOP8 PACKAGE OUTLINE DIMENSIONS Symbol A A1 A2 b c D E E1 e L  Dimensions In Millimeters Min Max 1.350 0.100 1.350 0.330 0.170 4.700 3.800 5.800 1.750 0.250 1.550 0.510 0.250 5.100 4.000 6.200 1.270(BSC) 0.400 1.270 0° 8° © 2012 Fremont Micro Devices Inc. Dimensions In Inches Min Max 0.053 0.069 0.004 0.010 0.053 0.061 0.013 0.020 0.006 0.010 0.185 0.200 0.150 0.157 0.228 0.244 0.050(BSC) 0.016 0.050 0° 8° DS24C1024-A0--page12 Fremont Micro Devices FT24C1024A Fremont Micro Devices (SZ) Limited #5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, Shenzhen Tel: (86 755) 86117811 Fax: (86 755) 86117810 Fremont Micro Devices (Hong Kong) Limited #16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong Kong Tel: (852) 27811186 Fax: (852) 27811144 Web Site: http://www.fremontmicro.com/ * Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners. © 2012 Fremont Micro Devices Inc. DS24C1024-A0--page13