SPI(x1/x2/x4) NAND Flash
GD5F1GQ4xFxIG
DATASHEET
1
1G
SPI(x1/x2/x4) NAND Flash
1G
Contents
1
FEATURE ........................................................................................................................................................... 4
2
GENERAL DESCRIPTION ............................................................................................................................... 5
2.1 PRODUCT LIST ............................................................................................................................................................... 6
2.2 CONNECTION DIAGRAM .................................................................................................................................................. 7
2.3 PIN DESCRIPTION ........................................................................................................................................................... 7
2.4 BLOCK DIAGRAM ........................................................................................................................................................... 8
3
ARRAY ORGANIZATION ................................................................................................................................. 9
4
MEMORY MAPPING ....................................................................................................................................... 10
5
DEVICE OPERATION ..................................................................................................................................... 11
5.1 SPI MODES ................................................................................................................................................................ 11
5.2 HOLD MODE ............................................................................................................................................................. 12
5.3 WRITE PROTECTION ..................................................................................................................................................... 12
6
COMMANDS DESCRIPTION ......................................................................................................................... 13
7
WRITE OPERATIONS .................................................................................................................................... 14
7.1 WRITE ENABLE (WREN) (06H) ..................................................................................................................................... 14
7.2 WRITE DISABLE (WRDI) (04H) ..................................................................................................................................... 14
FEATURE OPERATIONS ............................................................................................................................... 15
8
8.1 GET FEATURES (0FH) AND SET FEATURES (1FH) ............................................................................................................... 15
READ OPERATIONS ...................................................................................................................................... 17
9
9.1 PAGE READ................................................................................................................................................................. 17
9.2 PAGE READ TO CACHE (13H) ......................................................................................................................................... 17
9.3 READ FROM CACHE (03H) ............................................................................................................................................ 18
9.4 FAST READ FROM CACHE (0BH) ..................................................................................................................................... 18
9.5 READ FROM CACHE X2 (3BH) ........................................................................................................................................ 19
9.6 READ FROM CACHE X4 (6BH) ........................................................................................................................................ 19
9.7 READ FROM CACHE DUAL IO (BBH) ............................................................................................................................... 20
9.8 READ FROM CACHE QUAD IO (EBH)............................................................................................................................... 21
10
READ ID (9FH) ............................................................................................................................................ 22
11
PROGRAM OPERATIONS ......................................................................................................................... 23
11.1 PAGE PROGRAM ........................................................................................................................................................ 23
11.2 PROGRAM LOAD (PL) (02H) ....................................................................................................................................... 24
11.3 PROGRAM LOAD X4 (PL X4) (32H) ............................................................................................................................... 25
11.4 PROGRAM EXECUTE (PE) (10H) ................................................................................................................................... 26
11.5 INTERNAL DATA MOVE ............................................................................................................................................... 27
11.6 PROGRAM LOAD RANDOM DATA (84H) ........................................................................................................................ 27
11.7 PROGRAM LOAD RANDOM DATA X4 (C4H/34H) ............................................................................................................ 28
2
SPI(x1/x2/x4) NAND Flash
12
1G
ERASE OPERATIONS ............................................................................................................................... 29
12.1 BLOCK ERASE (D8H) .................................................................................................................................................. 29
13
RESET OPERATIONS ................................................................................................................................ 30
13.1 SOFT RESET (FFH) ..................................................................................................................................................... 30
14
ADVANCED FEATURES ............................................................................................................................ 31
14.1 OTP REGION ............................................................................................................................................................ 31
14.2 BLOCK PROTECTION ................................................................................................................................................... 32
14.3 STATUS REGISTER AND DRIVER REGISTER ........................................................................................................................ 33
14.4 ASSISTANT BAD BLOCK MANAGEMENT .......................................................................................................................... 34
14.5 INTERNAL ECC .......................................................................................................................................................... 35
15
POWER ON TIMING ................................................................................................................................... 36
16
ABSOLUTE MAXIMUM RATINGS ............................................................................................................ 37
17
CAPACITANCE MEASUREMENT CONDITIONS .................................................................................... 38
18
DC CHARACTERISTIC .............................................................................................................................. 39
19
AC CHARACTERISTICS............................................................................................................................ 40
20
PERFORMANCE TIMING .......................................................................................................................... 41
21
ORDERING INFORMATION ...................................................................................................................... 43
22
PACKAGE INFORMATION ........................................................................................................................ 44
23
REVISION HISTORY................................................................................................................................... 48
3
SPI(x1/x2/x4) NAND Flash
1
1G
FEATURE
◆1Gb
◆Program/Erase/Read Speed
SLC NAND Flash
- Page Program time: 400us typical
◆Page
Size
- Block Erase time: 3ms typical
- 2048 bytes + 128 bytes with ECC disabled
- Page read time: 80us maximum(w/I ECC)
- 2048 bytes + 64 bytes with ECC enabled
◆Reliability
◆Standard,
Dual, Quad SPI
- Endurance: 100K program/erase cycles
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Data retention: 10 Years
- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
◆Low
Power Consumption
- 40mA maximum active current
◆High
- 90uA(1) maximum standby current
Speed Clock Frequency
- 120MHz for fast read with 30PF load
- Quad I/O Data transfer up to 480Mbits/s
◆Enhanced
access performance
- 2kbyte cache for fast random read
◆
Software/Hardware Write Protection
- Cache read and cache program
- Write protect all/portion of memory via software
- Register protection with WP# Pin
◆Advanced
- Top or Bottom, Block selection combination
Feature for NAND
- Internal ECC option, per 528bytes
- Internal data move by page with ECC
◆Advanced
security Features
- 8K-Byte OTP Region (4 page OTP)
◆The
first block(Block0) is guaranteed to be a valid block
at the time of shipment.
◆Single
Power Supply Voltage
- Full voltage range for 1.8V: 1.7V ~ 2.0V
- Full voltage range for 3.3V: 2.7V ~ 3.6V
Note 1: When Temperature is 105℃, the maximum standby current is 200uA
4
SPI(x1/x2/x4) NAND Flash
1G
2 GENERAL DESCRIPTION
SPI (Serial Peripheral Interface) NAND Flash provides an ultra cost-effective while high density non-volatile memory
storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive
alternative to SPI-NOR and standard parallel NAND Flash, with advanced features:
• Total pin count is 8, including VCC and GND
• Density is 1Gbit
• Superior write performance and cost per bit over SPI-NOR
• Significant low cost than parallel NAND
This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the
same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to
handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash
memory, with specified designed features to ease host management:
• User-selectable internal ECC. ECC code is generated internally during a page program operation. When a page
is read to the cache register, the ECC code is detect and correct the errors when necessary. The 64-bytes spare area
is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status.
• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage
collection task, without need of shift in and out of data.
•Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power
on, then host can directly read data from cache for easy boot. Also the data is promised correctly by internal ECC.
It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or
from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest
to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as
a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable
page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports
the status of device operation.
5
SPI(x1/x2/x4) NAND Flash
1G
2.1 Product List
Product Number
Density
Voltage
Package Type
GD5F1GQ4RFFIG
Temperature
-40℃ to 85℃
GD5F1GQ4RFFJG
SOP16 300mil
-40℃ to 105℃
GD5F1GQ4RFFFG
-40℃ to 85℃
GD5F1GQ4RFZIG
-40℃ to 85℃
GD5F1GQ4RFZJG
1.7V to 2.0V
TFBGA24(6*4 Ball Array)
-40℃ to 105℃
GD5F1GQ4RFZFG
-40℃ to 85℃
GD5F1GQ4RF9IG
-40℃ to 85℃
GD5F1GQ4RF9JG
GD5F1GQ4RF9FG
GD5F1GQ4UFYIG
LGA8(6*8mm)
-40℃ to 105℃
-40℃ to 85℃
1Gbit
-40℃ to 85℃
GD5F1GQ4UFYJG
WSON8(8*6mm)
-40℃ to 105℃
GD5F1GQ4UFYFG
-40℃ to 85℃
GD5F1GQ4UFFIG
-40℃ to 85℃
GD5F1GQ4UFFJG
2.7V to 3.6V
SOP16 300mil
-40℃ to 105℃
GD5F1GQ4UFFFG
-40℃ to 85℃
GD5F1GQ4UFZIG
-40℃ to 85℃
GD5F1GQ4UFZJG
Page Size
TFBGA24(6*4 Ball Array)
GD5F1GQ4UFZFG
-40℃ to 105℃
-40℃ to 85℃
6
2Kbyte + 128Byte
SPI(x1/x2/x4) NAND Flash
1G
2.2 Connection Diagram
HOLD#
1
16
SCLK
VCC
2
15
SI
NC
3
14
NC
NC
4
13
NC
CS# 1
SO
8 VCC
2
7
HOLD#
Top View
WP# 3
6 SCLK
VSS 4
5 SI
Top View
NC
5
12
NC
NC
6
11
NC
CS#
7
10
VSS
SO
8
9
WP#
8–LEAD WSON
16-LEAD SOP
Top View
4
NC
VCC
WP# HOLD# NC
NC
NC
VSS
NC
SI
NC
NC
NC
SCLK
CS#
SO
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
3
2
1
24-BALL TFBGA
Figure2-1 Connection Diagram
2.3 Pin Description
Pin Name
I/O
Description
CS#
I
Chip Select input, active low
SO/SIO1
I/O
Serial Data Output / Serial Data Input Output 1
WP#/SIO2
I/O
Write Protect, active low / Serial Data Input Output 2
VSS
Ground
Ground
SI/SIO0
I/O
Serial Data Input / Serial Data Input Output 0
SCLK
I
Serial Clock input
HOLD#/SIO3
I/O
Hold input, active low / Serial Data Input Output3
VCC
Supply
Power Supply
7
SPI(x1/x2/x4) NAND Flash
1G
2.4 Block Diagram
SCLK
SI/SIO0
SO/SIO1
CS#
HOLD#/ WP#/
RESET#/ SIO2
SIO3
Serial NAND controler
Vcc
Vss
Cache
memory
ECC and status register
Figure2-2 Block Diagram
8
NAND
memory
core
SPI(x1/x2/x4) NAND Flash
1G
3 ARRAY ORGANIZATION
Each device has
Each block has
Each page has
128M+8M
128K+8K
2K+128
bytes
1024 x 64
64
-
pages
1024
-
-
blocks
1G
Figure3-1. Array Organization
SO
Cache Register
2048
128
Data Register
2048
128
SI
1 page = (2K + 128 bytes)
1 block = (2K + 128 bytes) x 64 pages
= (128K + 8K) bytes
Per device:
1Gb: 1024Blocks
1 device:
For 1G: = (128K +8K) bytes x 1024 blocks
= 1Gb
1 block
9
SPI(x1/x2/x4) NAND Flash
1G
4 MEMORY MAPPING
<
6
7
8
Blocks
RA
0
1
2
Pages
RA
0
1
Bytes
CA
0
1
15 >
1023
63
2
2175
Note:
1.
CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0
through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device,
and cannot be addressed.
2.
RA: Row Address. RA selects a page inside a block, and RA selects a block:
10
SPI(x1/x2/x4) NAND Flash
1G
5 DEVICE OPERATION
5.1 SPI Modes
SPI NAND supports two SPI modes:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing
diagrams shown in this data sheet are mode 0. See Figure5-1 for more details.
Figure5-1. SPI Modes Sequence Diagram
CPOL CPHA
0
0 SCLK
1
1
SCLK
SI
MSB
LSB
SO
MSB
LSB
CS#
Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3).
Standard SPI
SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO).
Dual SPI
SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow
data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.
Quad SPI
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow
data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3.
11
SPI(x1/x2/x4) NAND Flash
1G
5.2 HOLD Mode
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated
data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low
(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of
HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure5-2. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock
bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the block protect
bits cannot be altered.
12
SPI(x1/x2/x4) NAND Flash
1G
6 COMMANDS DESCRIPTION
Table6-1. Commands Set
Command Name
Byte 1
Write Enable
Write Disable
Get Features
Set Feature
Page Read (to cache)
Read From Cache
Fast Read From Cache
Read From Cache x 2
Read From Cache x 4
Read From Cache Dual IO
Read From Cache Quad IO
Read ID(5)
Program Load
Program Load x4
Program Execute
Program Load Random Data
Program Load Random Data x4
Block Erase(128K)
Reset(6)
06H
04H
0FH
1FH
13H
03H
0BH
3BH
6BH
BBH
EBH
9FH
02H
32H
10H
84H(7)
C4H/34H(7)
D8H
FFH
Byte 2
Byte 3
A7-A0
A7-A0
A23-A16
dummy(2)
dummy(2)
dummy(2)
dummy(2)
A15-A0
A15-A0(4)
MID
A15-A8
A15-A8
A23-A16
A15-A8
A15-A8
A23-A16
(D7-D0)
(D7-D0)
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
dummy(3)
(D7-D0)x4
DID
A7-A0
A7-A0
A15-A8
A7-A0
A7-A0
A15-A8
Byte 4
The dummy byte can be inputted or not.
2.
The x8 clock = dummy.
3.
The x8 clock = dummy, D7-D0.
4.
The x8 clock = A15-A0, dummy, D7-D0.
5.
MID is Manufacture ID (C8h for GigaDevice), DID is Device ID.
6.
Reset command:
dummy(1)
A7-A0
A7-A 0(8)
A7-A0
A7-A0
A7-A0
(D7-D0)x2
DID
(D7-D0)
(D7-D0)x4
A7-A0
(D7-D0)
(D7-D0)x4
A7-A0
• During busy, Reset will reset PAGE READ/PROGRAM/ERASE operation.
• During idle, Reset will reset status register bits P_FAIL/E_FAIL/ECCS bits.
7.
Those commands are only available in Internal Data Move operation.
8.
A0 need be 0 for the 03H command.
9.
The output would be updated by real-time, until CS# is driven high.
13
Byte N
Wrap(9)
Notes:
1.
Byte 5
(D7-D0)
dummy(2)
dummy(2)
dummy(2)
(D7-D0)
(D7-D0)x2
(D7-D0)x4
Next byte
Next byte
Byte N
Byte N
Next byte
Next byte
Byte N
Byte N
SPI(x1/x2/x4) NAND Flash
1G
7 WRITE OPERATIONS
7.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to following operations that change the contents of the memory array:
• Page program
• OTP program/OTP protection
• Block erase
The WEL bit can be cleared after a reset command.
Figure7-1. Write Enable Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7
Command
06H
High-Z
7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is also reset by following
condition:
• Page program
• OTP program/OTP protection
• Block erase
Figure7-2. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7
Command
04H
High-Z
14
SPI(x1/x2/x4) NAND Flash
1G
8 FEATURE OPERATIONS
8.1 Get Features (0FH) and Set Features (1FH)
The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the
device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Features such as OTP and block locking can be enabled or disabled by setting specific feature bits (shown in the following
table). The status register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H) command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise
specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.
Table8-1. Features Settings
Register Addr.
7
6
5
4
3
2
1
0
Protection A0H
BRWD
Reserved
BP2
BP1
BP0
INV
CMP
Reserved
Feature
B0H
OTP_PRT
Status
C0H
Reserved
Feature
D0H
Reserved
OTP_EN Reserved ECC_EN Reserved Reserved Reserved
ECCS2
ECCS1
ECCS0
P_FAIL
E_FAIL
QE
WEL
DS_IO[1] DS_IO[0] Reserved Reserved Reserved Reserved
OIP
Reserved
Note: If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.
If QE is enabled, the quad IO operations can be executed.
All the reserved bits must be held low when the feature is set.
00h is the default data byte value for Output Driver Register after power-up.
These registers are write/read type, except for Register of Status (C0H) is read only.
Figure8-2. Get Features Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
0FH
High-Z
1 byte address
7 6 5 4 3 2 1 0
Data byte
MSB
7 6 5 4 3 2 1 0
MSB
Note: The output would be updated by real-time, until CS# is driven high.
15
SPI(x1/x2/x4) NAND Flash
1G
The set features command supports a dummy byte mode after the data byte as well. The features in the feature byte B0H
are all volatile except OTP_PRT bit.
Figure8-3. Set Features Sequence Diagram
CS#
SCLK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
1FH
SO
1 byte address
Data byte
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
MSB
High-Z
16
SPI(x1/x2/x4) NAND Flash
1G
9 READ OPERATIONS
9.1 Page Read
The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command
sequence is as follows:
• 13H (PAGE READ to cache)
• 0FH (GET FEATURES command to read the status)
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH (Read from cache
dual IO)/EBH (Read from cache quad IO)
The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts
the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0FH)
command can be issued to monitor the status. Followed the page read operation, the RANDOM DATAREAD
(03H/0BH/3BH/6BH/BBH/EBH) command must be issued in order to read out the data from cache. The output data starts
at the initial address specified in the command, and will continue until CS# is pulled high to terminate this operation.
Refer waveforms to view the entire READ operation.
9.2 Page Read to Cache (13H)
Figure9-1.Page Read to cache Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10
SCLK
Command
SI
28 29 30 31
24-bit address
13H
23 22 21
3 2 1 0
High-Z
SO
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SLK
tCS
Get Feature
0FH
SI
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7 6 5 4 3 2 1 0 7
MSB
17
1 byte address
7 6 5 4 3 2 1 0
MSB
SPI(x1/x2/x4) NAND Flash
1G
9.3 Read From Cache (03H)
Figure9-2. Read From Cache Sequence Diagram
CS#
0
1
2
3
4
5
6
8
7
9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
SCLK
Command
SI
Dummy Byte
7
03H
6
5
4
3
2
1
A15-0
0 15 14 13 12 11
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39
SCLK
SI
SO
7 6
MSB
Byte 0
4 3
5
2
1
0
7 6
MSB
Byte 1
5
9.4 Fast Read From Cache (0BH)
Figure9-3. Read From Cache Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
SCLK
Command
SI
Dummy Byte
7
0BH
6
5
4
3
2
1
A15-0
0 15 14 13 12 11
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO
7
6
5
4
3
2
1
0
7 6
MSB
5
Byte 0
4 3
18
2
1
0
7 6
MSB
Byte 1
5
3
2
1
0
SPI(x1/x2/x4) NAND Flash
1G
9.5 Read From Cache x2 (3BH)
Figure9-4. Read From Cache x2 Sequence Diagram
CS#
0
1
2
3
4
5
6
8
7
9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
SCLK
Command
SI
Dummy Byte
7
3BH
6
5
4
3
2
A15-0
0 15 14 13 12 11
1
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
6
4
2
0
6
Byte 0
7 5 3 1
SO
MSB
4
2
0
6
Byte 1
7 5 3 1
4
2
Byte 2
7 5 3
MSB
9.6 Read From Cache x4 (6BH)
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command.
Figure9-5. Read From Cache x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
8
7
9 10 11 12 13 14 15 16 17 18 19 20 21
30 31
SCLK
Command
SI
Dummy Byte
7
6BH
6
5
4
3
2
A15-0
0 15 14 13 12 11
1
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
7
6
5
4
3
2
1
0
4
0
4
0
4
0
4
0
4
SO(SIO1)
5
1
5
1
5
1
5
1
5
WP#(SIO2)
6
2
6
2
6
2
6
2
6
HOLD#(SIO3)
7 3 7 3 7 3 7 3 7
Byte0 Byte1 Byte2 Byte3
SI(SIO0)
19
3
2
1
0
SPI(x1/x2/x4) NAND Flash
1G
9.7 Read From Cache Dual IO (BBH)
The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH), followed by a 12bit
column address for the starting byte address and a dummy byte by SIO0 and SIO1, each bit being latched in during the
rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address
byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted
out until the end of whole page.
Figure9-6. Read From Cache Dual IO Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Command
SI(SIO0)
BBH
SO(SIO1)
A7-0
Dummy, A11-8
Dummy
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(SIO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(SIO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
20
Byte4
Byte0
SPI(x1/x2/x4) NAND Flash
1G
9.8 Read From Cache Quad IO (EBH)
The Read from Cache Quad IO command is similar to the Read from Cache x4 command, followed a 12-bit column address
for the starting byte address and a dummy byte by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising
edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out until the end of whole page. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read
from cache quad IO command.
Figure9-7. Read From Cache Quad IO Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
SO(SIO1)
5
1
5
1
5
1
5
1
5
1
5
WP#(SIO2)
6
2
6
2
6
2
6
2
6
2
6
HOLD#(SIO3)
7
3
7
3
7
3
7
3
7
3
7
SCLK
Command
SI(SIO0)
EBH
A7-0
Dummy, A11-A8
21
Dummy
Byte0 Byte1
SPI(x1/x2/x4) NAND Flash
1G
10 Read ID (9FH)
The READ ID command is used to identify the NAND Flash device.
• The READ ID command outputs the Manufacturer ID and the device ID. See Table10-1 for details.
Figure10-1. Read ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
Manufacturer ID
6 5 4 3 2 1
SCLK
Command
SI
9FH
High-Z
SO
CS#
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
Device ID(Byte 1)
SO
7
6
5
4
3
2
1
MSB
Device ID(Byte 2)
0
7
6
5
4
3
2
1
0
MSB
Table10-1. READ ID Table
ID
Description
Part No
Value
Manufacture ID (GigaDevice)
SPI NAND 3.3V
GD5F1GQ4U
C8h
SPI NAND 1.8V
GD5F1GQ4R
Device ID
SPI NAND 1Gbit 3.3V
GD5F1GQ4U
B1h
2Kbyte +
(Byte 1)
SPI NAND 1Gbit 1.8V
GD5F1GQ4R
A1h
128Byte
Device ID
SPI NAND 1Gbit 3.3V
GD5F1GQ4U
48h
(Byte 2)
SPI NAND 1Gbit 1.8V
GD5F1GQ4R
22
Page Size
SPI(x1/x2/x4) NAND Flash
1G
11 PROGRAM OPERATIONS
11.1 Page Program
The PAGE PROGRAM operation sequence programs 1 byte to 2176 bytes of data with in a page. The page program
sequence is as follows:
• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The data bytes are loaded into a cache
register that is 2176 bytes long. If more than 2176bytes are loaded, then those additional bytes are ignored by the cache
register. The command sequence ends when CS# goes from LOW to HIGH. Figure11-1 shows the PROGRAMLOAD
operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must
be issued. As with any command that changes the memory contents, the WRITEENABLE must be executed in order to set
the WEL bit. If this command is not issued, then the rest of the program sequence is ignored.
Note:
1.
The contents of Cache Register doesn’t reset when Program Load (02h) command, Program Random Load (84h) command and
RESET (FFh) command.
2.
When Program Execute (10h) command was issued just after Program Load (02h) command, SPI-NAND controller outputs 0xFF
data to the NAND for the address that data was not loaded by Program Load (02h) command.
3.
When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, SPI-NAND controller
outputs contents of Cache Register to the NAND.
4.
The addressing should be done in sequential order in a block.
23
SPI(x1/x2/x4) NAND Flash
1G
11.2 Program Load (PL) (02H)
Figure11-1. Program Load Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
0
0
22 23
SCLK
Command
SI
Dummy, A11-A0
02H
0 0 11 10
3
2
1
0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
17424
17431
SCLK
Data Byte0
SI
7 6
MSB
5
4
3
Data Byte1
2
1
0 7
6
5
4
3
2
1
0
7
6
Data Byte
2175/2111
5 4 3 2 1
0
Note: when internal ECC disabled the Data Byte is 2175, when internal ECC enabled the Data Byte is 2111.
24
SPI(x1/x2/x4) NAND Flash
1G
11.3 Program Load x4 (PL x4) (32H)
The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the
data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE)
of feature (B0[0]) must be set to enable the program load x4 command.
Figure11-2. Program Load x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
SI(SIO0)
Dummy, A11-A0
32H
15 14 13
3
2
1
Byte0 Byte1 Byte2 Byte3
0 4
0
4
0
4
0
4
0
SO(SIO1)
5
1
5
1
5
1
5
1
WP#(SIO2)
6
2
6
2
6
2
6
2
HOLD#(SIO3)
7
3
7
3
7
3
7
3
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Byte
2175/2111
Byte4 Byte5 Byte6 Byte7 Byte8 Byte9 Byte10Byte11
SI(SIO0)
4
SO(SIO1)
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
WP#(SIO2)
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
HOLD#(SIO3) 7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
Note: when internal ECC disabled the Byte is 2175, when internal ECC enabled the Byte is 2111.
25
0
SPI(x1/x2/x4) NAND Flash
1G
11.4 Program Execute (PE) (10H)
After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the
cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After
the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and
is busy for tPROG time. This operation is shown in Figure11-3. During this busy time, the status register can be polled to
monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series
of data can be loaded with the PROGRAM LOAD command.
Figure11-3. Program Execute Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SCLK
Command
SI
24-bit address
10H
23 22 21
3 2 1 0
High-Z
SO
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
tCS
SI
get feature
0FH
SO
High-Z
CS#
Status register address
7 6 5 4 3 2 1 0
MSB
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
SO
Status register data out
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
MSB
MSB
26
SPI(x1/x2/x4) NAND Flash
1G
11.5 Internal Data Move
The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The
INTERNAL DATA MOVE command sequence is as follows:
• 13H (PAGE READ to cache)
• Optional 84H/C4H/34H (PROGRAM LOAD RANDOM DATA)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Prior to performing an internal data move operation, the target page content must be read out into the cache register by
issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H/34H) command can be
issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random
data is not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H/34H) command must be issued with the
new column address. After the data is loaded, the WRITE ENABLE command must be issued, and the PROGRAM
EXECUTE (10H) command can be issued to start the programming operation.
11.6 Program Load Random Data (84H)
This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded
in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD
RANDOM DATA (84H) command must be issued with a new column address, see Figure11-4 for details. This command is
only available during internal data move sequence.
Figure11-4. Program Load Random Data Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
22 23
SCLK
Dummy, A11-A0
Command
SI
84H
0
0
0 0 11 10
3
2
1
0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
17424
17431
SCLK
Data Byte0
SI
7 6
MSB
5
4
3
Data Byte1
2
1
0
7
6
5
4
3
2
1
0
7
6
Data Byte
2175/2111
5 4 3 2 1
0
Note: when internal ECC disabled the Data Byte is 2175, when internal ECC enabled the Data Byte is 2111.
27
SPI(x1/x2/x4) NAND Flash
1G
11.7 Program Load Random Data x4 (C4H/34H)
The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H)
but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown
below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command.
SeeFigure11-5 for details. Those two commands are only available during internal data move sequence.
Figure11-5. Program Load Random Data x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
SI(SIO0)
Dummy, A11-A0
C4H/34H
15 14 13
3
2
1
Byte0 Byte1
0 4
0
4
0
4
0
4
0
SO(SIO1)
5
1
5
1
5
1
5
1
WP#(SIO2)
6
2
6
2
6
2
6
2
HOLD#(SIO3)
7
3
7
3
7
3
7
3
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Byte
2175/2111
Byte10Byte11
SI(SIO0)
4
SO(SIO1)
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
WP#(SIO2)
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
HOLD#(SIO3) 7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
Note: when internal ECC disabled the Data is 2175, when internal ECC enabled the Data is 2111.
28
0
SPI(x1/x2/x4) NAND Flash
1G
12 ERASE OPERATIONS
12.1 Block Erase (D8H)
Figure12-1. Block Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SCLK
Command
SI
24-bit address
D8H
23 22 21
3 2 1 0
High-Z
SO
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SLK
tCS
Status register address
get feature
0FH
SI
7 6 5 4 3 2 1 0
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
SO
Status register data out
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
MSB
MSB
The BLOCK ERASE (D8H) command is used to erase at the block level. The blocks are organized as 64 pages per
block, 2176 bytes per page (2048 + 128 bytes). Each block is136 Kbytes. The BLOCK ERASE command (D8H) operates
on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:
• 06H (WRITE ENBALE command)
• D8H (BLOCK ERASE command)
• 0FH (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06H) command must be issued. As with any
command that changes the memory contents, the WRITEENABLE command must be executed in order to set the WEL
bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE
command must be followed by a BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the
row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy
for tERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the
status of the operation.
When
a
block
erase
operation
is
in
progress,
user
(03H/0BH/3BH/6BH/BBH/EBH) to read the data in the cache.
29
can
issue
normal
read
from
cache
commands
SPI(x1/x2/x4) NAND Flash
1G
13 RESET OPERATIONS
13.1 Soft Reset (FFH)
Figure13-1. Reset Sequence Diagram
CS#
tCS
0
1
2
3
4
5
6
7
SCLK
Command
SI
FFH
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
Status register address
get feature
SI
0FH
High-Z
SO
CS#
7
6
5
4
3
2
1
0
MSB
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
SO
7
6
5
4
3
2
1
0
MSB
Status register data out
7
6
5
4
3
2
1
0
7
6
MSB
The RESET (FFH) command stops all operations. For example, in case of a program or erase or read operation, the
reset command can make the device enter the wait state.
During a cache program or cache read, a reset can also stops the previous operation and the pending operation. The
OIP status can be read from 300ns after the reset command is sent.
30
SPI(x1/x2/x4) NAND Flash
1G
14 ADVANCED FEATURES
14.1 OTP Region
The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages (2176 bytes per
page) are available on the device. Customers can use the OTP area any way they want, like programming serial
numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP_PRT is 0.
To access the OTP feature, the user must set feature bits OTP_EN/OTP_PRT by SET FEATURES command. When the
OTP is ready for access, pages 00h–03H can be programmed in sequential order by PROGRAM LOAD (02H) and
PROGRAM EXECUTE(10H) commands ( when not yet protected), and read out by PAGE READ (13H) command and
output data by READ from CACHE(03H/0BH/3BH/6BH/BBH/EBH).
Table14-1. OTP States
OTP_PRT
OTP_EN
State
x
0
Normal operation
0
1
Access OTP region, read and program data.
1
1
1.
When the device power on state OTP_PRT is 0, user can set feature
bit OTP_PRT and OTP_EN to 1, then issue PROGRAM EXECUTE
(10H) to lock OTP, and after that OTP_PRT will permanently remain 1.
2.
When the device power on state OTP_PRT is 1, user can only read the
OTP region data.
Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this
function carefully.
Access to OTP data
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN
• Issue the PAGE PROGRAM (only when OTP_PRT is 0) or PAGE READ command
Protect OTP region
Only when the following steps are completed, the OTP_PRT will be set and users can get this feature out with 0FH
command.
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN and OTP_PRT
• 06H (WRITE ENABLE)
• Issue the PROGRAM EXECUTE (10H) command.
31
SPI(x1/x2/x4) NAND Flash
1G
14.2 Block Protection
The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and ERASE
operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2are set to 1, INV, CMP
and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be issued to
alter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection feature bits
can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0.When an
ERASE command is issued to a locked block, the erase failure, 04H, is returned. When a PROGRAM command is issued
to a locked block, program failure,08h is returned.
Table14-1. Block Lock Register Block Protect Bits
CMP
INV
BP2
BP1
BP0
Protect Row Address
Protect Rows
1G
x
x
0
0
0
NONE
None—all unlocked
0
0
0
0
1
FC00h ~ FFFFh
Upper 1/64 locked
0
0
0
1
0
F800h ~ FFFFh
Upper 1/32 locked
0
0
0
1
1
F000h ~ FFFFh
Upper 1/16 locked
0
0
1
0
0
E000h ~ FFFFh
Upper 1/8 locked
0
0
1
0
1
C000h ~ FFFFh
Upper 1/4 locked
0
0
1
1
0
8000h ~ FFFFh
Upper 1/2 locked
x
x
1
1
1
0000h ~ FFFFh
All locked (default)
0
1
0
0
1
0000h ~ 03FFh
Lower 1/64 locked
0
1
0
1
0
0000h ~ 07FFh
Lower 1/32 locked
0
1
0
1
1
0000h ~ 0FFFh
Lower 1/16 locked
0
1
1
0
0
0000h ~ 1FFFh
Lower 1/8 locked
0
1
1
0
1
0000h ~ 3FFFh
Lower 1/4 locked
0
1
1
1
0
0000h ~ 7FFFh
Lower 1/2 locked
1
0
0
0
1
0000h ~ FBFFh
Lower 63/64 locked
1
0
0
1
0
0000h ~ F7FFh
Lower31/32 locked
1
0
0
1
1
0000h ~ EFFFh
Lower 15/16 locked
1
0
1
0
0
0000h ~ DFFFh
Lower7/8 locked
1
0
1
0
1
0000h ~ BFFFh
Lower3/4 locked
1
0
1
1
0
0000h ~ 003Fh
Block0
1
1
0
0
1
0400h ~ FFFFh
Upper 63/64 locked
1
1
0
1
0
0800h ~ FFFFh
Upper31/32 locked
1
1
0
1
1
1000h ~ FFFFh
Upper 15/16 locked
1
1
1
0
0
2000h ~ FFFFh
Upper7/8 locked
1
1
1
0
1
4000h ~ FFFFh
Upper3/4 locked
1
1
1
1
0
0000h ~ 003Fh
Block0
When WP# is not LOW, user can issue bellows commands to alter the protection states as want.
• Issue SET FEATURES register write (1FH)
• Issue the feature bit address (A0h) and the feature bits combination as the table
32
SPI(x1/x2/x4) NAND Flash
1G
14.3 Status Register and Driver Register
The NAND Flash device has a 16-bit status register that software can read during the device operation for operation state
query. The status register can be read by issuing the GET FEATURES (0FH)command, followed by the feature address
C0h (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE (0FH)
and GET FEATURE command followed by the feature address D0h (see FEATURE OPERATION)..
Table14-2. Status Register Bit Descriptions
Bit
Bit Name
Description
P_FAIL
Program
This bit indicates that a program failure has occurred (P_FAIL set to 1). It will also be
Fail
set if the user attempts to program an invalid address or a protected region, including
the OTP area. This bit is cleared during the PROGRAM EXECUTE command
sequence or a RESET command (P_FAIL = 0).
E_FAIL
Erase Fail
This bit indicates that an erase failure has occurred (E_FAIL set to 1). It will also be
set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at
the start of the BLOCK ERASE command sequence or the RESET command.
WEL
Write
This bit indicates the current status of the write enable latch (WEL) and must be set
Enable
(WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It
Latch
is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL =
0), by issuing the WRITE DISABLE command.
OIP
Operation
This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ, BLOCK
In Progress
ERASE, or RESET command is executing, indicating the device is busy. When the bit
is 0, the interface is in the ready state.
ECCS2~ECCS0
ECC Status
ECCS2~ECCS0 provides ECC status as the following table.
Table14-3. ECC Status
ECCS2
ECCS1
ECCS0
Description
0
0
0
No bit errors were detected during the previous read algorithm.
0
0
1
Bit errors(8, error exceeded. And cannot be corrected.
33
SPI(x1/x2/x4) NAND Flash
1G
Table14-4. Driver Register Bits Descriptions
DS_S1
DS_S0
Driver Strength
0
0
50%
0
1
25%
1
0
75%
1
1
100%
14.4 Assistant Bad Block Management
As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number of
valid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page that has
more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use. However,
the total number of available blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide badblock management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block from
other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by
programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with
ONFI Factory Defect Mapping requirements. See the following table I bad-block mark.
System software should initially check the first spare area location for non-FFH data I first page of each block prior to
performing any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling
system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased.
To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant Management
options as below.
Table14-5. Bad Block Mark information
Description
Density
Requirement
Minimum number of valid blocks (NVB)
1G
1004
Total available blocks per die
1G
1024
First spare area location
Byte 2048
Bad-block mark
00h(use non FFH to check)
34
SPI(x1/x2/x4) NAND Flash
1G
14.5 Internal ECC
The serial device offers data corruption protection by offering optional internal ECC.READs and PROGRAMs with internal
ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled after device power up, so the default
READ and PROGRAM commands operate with internal ECC in the “active” state. To enable/disable ECC, perform the
following command sequence:
• Issue the SET FEATURES command (1FH).
• Set the feature bit ECC_EN as you want:
1.
To enable ECC, Set ECC_EN to 1.
2.
To disable ECC, Clear ECC_EN to 0.
During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page
is written to the NAND Flash array.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated
and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cache
register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was
successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.
With internal ECC, the user must accommodate the following:
• Spare area definitions provided in the ECC Protection table below.
• ECC can protect according main and spare areas. WRITEs to the ECC area are ignored.
Table14-6. ECC Protection and Spare Area
Max Byte Address
Min Byte Address
ECC Protected
Area
Description
1FFh
000h
Yes
Main 0
User data 0
3FFh
200h
Yes
Main 1
User data 1
5FFh
400h
Yes
Main 2
User data 2
7FFh
600h
Yes
Main 3
User data 3
80Fh
800h
Yes
Spare 0
User meta data 0(1)
81Fh
810h
Yes
Spare 1
User meta data 1
82Fh
820h
Yes
Spare 2
User meta data 2
83Fh
830h
Yes
Spare 3
User meta data 3
87Fh
840h
Yes
Spare Area
Internal ECC parity data
Note1:800H is reserved for initial bad block mark, and please check the initial bad block mark with internal ECC off.
35
SPI(x1/x2/x4) NAND Flash
1G
15 POWER ON TIMING
Figure15-1. Power on Timing Sequence
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
Device is fully
accessible
VWI
Time
Table15-1. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V
Symbol
tVSL
VWI
Parameter
Min
VCC(min) To CS# Low
Write Inhibit Voltage
Max
5
ms
1.8V
1.7
3.3V
2.5
36
Unit
V
SPI(x1/x2/x4) NAND Flash
1G
16 ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Ambient Operating Temperature
-40 to 105
℃
Storage Temperature
-55 to 125
℃
Applied Input/Output Voltage
-0.6 to Vcc+0.4
V
-0.6 to Vcc+0.4
V
VCC
37
SPI(x1/x2/x4) NAND Flash
1G
17 CAPACITANCE MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
CIN
Input Capacitance
6
pF
VIN=0V
COUT
Output Capacitance
8
pF
VOUT=0V
CL
Load Capacitance
30
pF
Input Rise And Fall time
5
ns
Input Pulse Voltage
0.1VCC to 0.8VCC
V
Input Timing Reference Voltage
0.2VCC to 0.7VCC
V
0.5VCC
V
Output Timing Reference Voltage
Figure17-1. Input Test Waveform and Measurement Level
Input timing reference level
0.8VCC
0.7VCC
0.1VCC
0.2VCC
Output timing reference level
AC Measurement Level
Note: Input pulse rise and fall time are
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