FT24C04A-KDR-B

Fremont Micro Devices FT24C04A-KXX Two-Wire Serial EEPROM 4K (8-bit wide) FEATURES  Low voltage and low power operations:  FT24C04A-KXX: VCC = 1.8V to 5.5V, Industrial temperature range (-40℃ to 85℃).  16 bytes page write mode.  Partial page write operation allowed.  Internally organized: 512 × 8 (4K).  Standard 2-wire bi-directional serial interface.  Write protect pin for hardware data protection.  Schmitt trigger, filtered inputs for noise protection.  Self-timed programming cycle (5ms maximum).  1 MHz (2.5V-5V), 400 kHz (1.8V) Compatibility.  Automatic erase before write operation.  High reliability: typically 1,000,000 cycles endurance.  100 years data retention.  Standard 8-pin DIP/SOP/MSOP/TSSOP/DFN and 5-pin SOT-23/TSOT-23 Pb-free packages. DESCRIPTION The FT24C04A-KXX is 4096 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 512 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP, 8-lead DFN and 5-lead SOT-23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page1 Fremont Micro Devices FT24C04A-KXX PIN CONFIGURATION Pin Name Pin Function A2, A1 SDA SCL VCC WP GND Device Address Inputs Serial Data Input / Open Drain Output Serial Clock Input Power Supply Write Protect Ground NC No-Connect Table 1 All these packaging types come in conventional or Pb-free certified. Figure 1: Package types © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page2 Fremont Micro Devices FT24C04A-KXX ABSOLUTE MAXIMUM RATINGS Industrial operating temperature: -40℃ to 85℃ Storage temperature: -50℃ to 125℃ Input voltage on any pin relative to ground: -0.3V to VCC + 0.3V Maximum voltage: 8V ESD protection on all pins: >2000V * Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. Figure 2: Block Diagram © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page3 Fremont Micro Devices FT24C04A-KXX PIN DESCRIPTIONS (A) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (B) SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (C) DEVICE / CHIP SELECT ADDRESSES (A2, A1) These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL. However, due to capacitive coupling that may appear in customer applications, FMD recommends always connecting the address pins to a known state. When using a pull-up or pull-down resistor, FMD recommends using 10kΩ or less. (D) WRITE PROTECT (WP) The FT24C04A-KXX devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level. If left unconnected, it is internally recognized as VIL. However, due to capacitive coupling that may appear in customer applications, FMD recommends always connecting the WP pin to a known state. When using a pull-up or pull-down resistor, FMD recommends using 10kΩ or less. MEMORY ORGANIZATION The FT24C04A-KXX devices have 32 pages. Since each page has 16 bytes, random word addressing to FT24C04A-KXX will require 9 bits data word addresses. DEVICE OPERATION (A) SERIAL CLOCK AND DATA TRANSITIONS The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITION With SCL ≥ VIH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition. © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page4 Fremont Micro Devices FT24C04A-KXX (C) STOP CONDITION With SCL ≥ VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation. (F) SOFT RESET After an interruption in protocol power loss or system reset, any two-wire part can be reset by following these steps: 1. Creat a START condition, 2. Clock eighteen data bits “1”, 3. Creat a start condition as SDA is high. SCL SDA START Condition Data Valid Data Transition STOP Condition Figure 3: Timing diagram for START and STOP conditions © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page5 Fremont Micro Devices FT24C04A-KXX START Condition SCL Data in Data out ACK Figure 4: Timing diagram for output ACKNOWLEDGE DEVICE ADDRESSING The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next two bits are device address bits. These two device address bits (5th and 6th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th and 6th ) as noted below. The seventh bit of the device address (P0) is a memory page address bit. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. WRITE OPERATIONS (A) BYTE WRITE A write operation requires the seventh bit of the device address (P0) and 8-bit data word address following the device address word and ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters into an internallytimed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed. (B) PAGE WRITE A page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the same page or memory row. All FT24C04A-KXX are organized to have 16 bytes per memory row or page. With the same write command as the byte write, the micro-controller does not © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page6 Fremont Micro Devices FT24C04A-KXX issue a STOP bit after sending the 1st byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36th cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n × 9th clock cycle. After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page programming completes after a time of TWC, the devices will return to the STANDBY mode. The least significant 4 bits of the word address (column address) increments internally by one after receiving each data word. The rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. The first page write data word can be of any column address. Up to 16 data words can be loaded into a page. If more then 16 data words are loaded, the 9th data word will be loaded to the 1st data word column address. The 10th data word will be loaded to the 2nd data word column address and so on. In other word, data word address (column address) will “roll” over the previously loaded data. (C) ACKNOWLEDGE POLLING ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle. READ OPERATIONS The read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) CURRENT ADDRESS READ The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8bit data word will then be serially clocked out. automatically increase by one. The internal address word counter will then For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode. (B) SEQUENTIAL READ The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page7 Fremont Micro Devices FT24C04A-KXX cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead. (C) RANDOM READ Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send the address word. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address. S T A R T DEVICE ADDRESS W R I T E WORD ADDRESS S T O P DATA SDA LINE RAM P / C S 0 WK B M S B S T A R T DEVICE ADDRESS LA SC BK A C K Figure 5: Byte Write W R I T E WORD ADDRESS(N) DATA(N) ... SDA LINE M S B RAM P / CS 0 WK B L A SC BK S T O P A C K DATA(N+X) A C K Figure 6: Page Write © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page8 Fremont Micro Devices FT24C04A-KXX S T A R T DEVICE ADDRESS R E A D S T O P DATA SDA LINE N O LRA S / C B WK M S B A C K Figure 7: Current Address Read DEVICE ADDRESS R E A D DATA (N) DATA (N+1) DATA (N+2) S T O P DATA (N+3) SDA LINE RA / C WK A C K A C K N O A C K A C K Figure 8: Sequential Read S T A R T DEVICE ADDRESS W R I T E S T A R T WORD ADDRESS(N) DEVICE ADDRESS R E A D S T O P DATA (N) SDA LINE M S B RA M P / C S 0 WK B LA SC BK M S B L RA S / C B WK Figure 9: Random Read © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 N O A C K FT24C04A-KXX-page9 Fremont Micro Devices FT24C04A-KXX Figure 10: SCL and SDA Bus Timing Electrical Specifications (A)Power-Up Requirements During a power-up sequence, the VCC supplied to the device should monotonically rise from GND to the minimum VCC level, with a slew rate no faster than 0.05 V/μs and no slower then 0.1 V/ms. A decoupling cap should be connected to the VCC PAD which is no smaller than 10nF. (B)Device Reset To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, this device includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby mode. The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. Figure 11: Power on and Power down If an event occurs in the system where the VCC level supplied to the device drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up sequence in compliance with the requirements defined in this section. © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page10 Fremont Micro Devices FT24C04A-KXX AC CHARACTERISTICS Symbol fSCL tLOW tHIGH tI tAA 1.8 V Parameter Min Clock frequency, SCL tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tPWR,R(1) tPUP(1) 2.5V-5.5V Max Min 400 Clock pulse width low 1.3 Clock pulse width high 0.6 Unit Max 1000 kHz 0.4 µs Noise suppression time(1) 50 50 µs ns Clock low to data out valid Time the bus must be free before a new transmission can start(1) START hold time 0.9 0.55 µs 1.3 0.5 µs 0.6 0.25 µs START set-up time 0.6 0.25 µs 0 0 µs Data in hold time Data in set-up time 0.4 100 100 ns Input rise time(1) 0.3 0.3 µs Input fall time 300 100 ns (1) STOP set-up time 0.6 0.25 µs Date out hold time 50 50 ns 0.1 tWR Vcc slew rate at power up Time required after VCC is stable before the device can accept commands Minimum time at Vcc=0V between power cycles Write cycle time Endurance(1) 25oC, Page Mode, 3.3V tPOFF(1) Notes*: 50 0.1 50 V/ms 100 100 µs 500 500 ms 5 1,000,000 5 ms Write Cycles 1. This Parameter is expected by characterization but is not fully screened by test. 2. AC Measurement conditions: RL (Connects to Vcc): 1.3KΩ Input Pulse Voltages: 0.3Vcc to 0.7Vcc Input and output timing reference Voltages: 0.5Vcc © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page11 Fremont Micro Devices FT24C04A-KXX DC CHARACTERISTICS Symbol Parameter Test Conditions Min Typical Unit s 5.5 V VCC1 Power supply VCC ICC1 Supply read current VCC @ 5.0V SCL = 400 kHz 0.5 1.0 mA ICC2 Supply write current VCC @ 5.0V SCL = 400 kHz 2.0 3.0 mA ISB1 Supply current VCC @ 1.8V, VIN = VCC or VSS < 1.0 µA ISB2 Supply current VCC @ 2.5V, VIN = VCC or VSS < 1.0 µA ISB3 Supply current VCC @ 5.0V, VIN = VCC or VSS < 1.0 µA IIL Input leakage current VIN = VCC or VSS 3.0 µA ILO Output leakage current VIN = VCC or VSS 3.0 µA VIL Input low level -0.6 VCC × 0.3 V VIH Input high level VCC × 0.7 VCC + 0.5 V VOL1 Output low level VCC @ 1.8V, IOL = 0.15 mA 0.2 V VOL2 Output low level VCC @ 3.0V, IOL = 2.1 mA 0.4 V © 2019 Fremont Micro Devices Inc. 1.8 Max Confidential Rev1.4 FT24C04A-KXX-page12 Fremont Micro Devices FT24C04A-KXX ORDER CODE: FT24C04A - K X X - X Packaging B: Tube T: Tape and Reel Circuit Type HSF R: RoHS G: RoHS and Halogen Free Temp. Range K: -40℃-85℃ Package D: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: UDFN8 ORDER INFORMATION Package Temperature Range Vcc SOT23-5 -40℃-85℃ 1.8V-5.5V TSOT23-5 -40℃-85℃ 1.8V-5.5V DIP8 -40℃-85℃ 1.8V-5.5V HSF Packaging Order code RoHS Tape and Reel FT24C04A-KLR-T* Green Tape and Reel FT24C04A-KLG-T* RoHS Tape and Reel FT24C04A-KPR-T* Green Tape and Reel FT24C04A-KPG-T* RoHS Tube FT24C04A-KDR-B Green Tube FT24C04A-KDG-B Tube FT24C04A-KSR-B RoHS SOP8 -40℃-85℃ Tape and Reel FT24C04A-KSR-T Tube FT24C04A-KSG-B Tape and Reel FT24C04A-KSG-T Tube FT24C04A-KTR-B Tape and Reel FT24C04A-KTR-T Tube FT24C04A-KTG-B Tape and Reel FT24C04A-KTG-T RoHS Tape and Reel FT24C04A-KNR-T Green Tape and Reel FT24C04A-KNG-T 1.8V-5.5V Green RoHS TSSOP8 -40℃-85℃ 1.8V-5.5V Green UDFN8 -40℃-85℃ 1.8V-5.5V * KLR/KLG/KPR/KPG : The device address A2 and A1 bits must be set to zero © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page13 Fremont Micro Devices FT24C04A-KXX SOT-23-5 PACKAGE OUTLINE DIMENSIONS Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 1.050 1.250 0.041 0.049 A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 e 0.95 (BSC) 0.116 0.037 (BSC) e1 1.800 2.000 0.071 0.079 L 0.300 0.600 0.012 0.024 0° 8° 0° 6°  © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page14 Fremont Micro Devices FT24C04A-KXX TSOT-23-5 PACKAGE OUTLINE DIMENSIONS Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.900 0.028 0.035 A1 0.000 0.100 0.000 0.004 A2 0.700 0.800 0.028 0.031 b 0.350 0.500 0.014 0.020 c 0.080 0.200 0.003 0.008 D 2.820 3.020 0.111 0.119 E 1.600 1.700 0.063 0.067 E1 2.650 2.950 0.104 0.116 e 0.95 (BSC) 0.037 (BSC) e1 1.90 (BSC) 0.075 (BSC) L  0.300 0.600 0.012 0.024 0° 8° 0° 8° © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page15 Fremont Micro Devices FT24C04A-KXX DIP8 PACKAGE OUTLINE DIMENSIONS Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max 4.310 0.146 0.170 A 3.710 A1 0.510 A2 3.200 B B1 0.380 0.570 1.524（BSC） 0.015 0.022 0.060（BSC） C 0.204 0.360 0.008 0.014 D 9.000 9.400 0.354 0.370 E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 0.100（BSC） e 0.020 3.600 2.540 (BSC) 0.126 0.142 L 3.000 3.600 0.118 0.142 E2 8.400 9.000 0.331 0.354 © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page16 Fremont Micro Devices FT24C04A-KXX SOP8 PACKAGE OUTLINE DIMENSIONS Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 e 1.270 (BSC) 0.050 (BSC) L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8° © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page17 Fremont Micro Devices FT24C04A-KXX TSSOP8 PACKAGE OUTLINE DIMENSIONS Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max D 2.900 3.100 0.114 0.122 E 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A 1.100 0.043 A2 0.800 1.000 0.031 0.039 A1 0.020 0.150 0.001 0.006 e L 0.65 (BSC) 0.500 H θ 0.026 (BSC) 0.700 0.020 7° 1° 0.25 (TYP) 1° © 2019 Fremont Micro Devices Inc. 0.028 0.01 (TYP) Confidential Rev1.4 7° FT24C04A-KXX-page18 Fremont Micro Devices FT24C04A-KXX UDFN8 PACKAGE OUTLINE DIMENSIONS Symbol Dimensions In Millimeters Min Max A 0.450 A1 b Dimensions In Inches 0.550 Min 0.017 Max 0.021 0.000 0.050 0.000 0.002 0.180 0.300 0.007 0.039 b1 0.160REF 0.006REF c 0.100 0.200 0.004 0.008 D 1.900 2.100 0.075 0.083 D2 1.400 1.600 0.055 0.062 e 0.500BSC 0.020BSC Nd 1.500BSC 0.059BSC E 2.900 3.100 0.114 0.122 E2 1.500 1.700 0.059 0.067 L 0.300 0.500 0.012 0.020 0.300 0.066 0.12 h © 2019 Fremont Micro Devices Inc. 0.200 Confidential Rev1.4 FT24C04A-KXX-page19 Fremont Micro Devices FT24C04A-KXX Fremont Micro Devices (SZ) Limited #1&5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, Shenzhen Tel: (86 755) 86117811 Fax: (86 755) 86117810 Fremont Micro Devices (Hong Kong) Limited #16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong Kong Tel: (852) 27811186 Fax: (852) 27811144 Web Site: http://www.fremontmicro.com/ * Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners. © 2019 Fremont Micro Devices Inc. Confidential Rev1.4 FT24C04A-KXX-page20