GD25LQ32DSIGR

1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D DATASHEET 1 GD25LQ32D 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Contents 1. FEATURES .........................................................................................................................................................4 2. GENERAL DESCRIPTION ................................................................................................................................5 3. MEMORY ORGANIZATION ...............................................................................................................................7 4. DEVICE OPERATION ........................................................................................................................................8 5. DATA PROTECTION ..........................................................................................................................................9 6. STATUS REGISTER......................................................................................................................................... 11 7. COMMANDS DESCRIPTION .......................................................................................................................... 13 7.1. WRITE ENABLE (WREN) (06H) ................................................................................................................................ 17 7.2. WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 18 7.3. WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 19 7.4. READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .............................................................................................. 20 7.5. WRITE STATUS REGISTER (WRSR) (01H) ................................................................................................................... 21 7.6. READ DATA BYTES (READ) (03H)............................................................................................................................. 22 7.7. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH) .............................................................................................. 22 7.8. FAST READ (0BH) IN QPI MODE ............................................................................................................................... 23 7.9. DUAL OUTPUT FAST READ (3BH) .............................................................................................................................. 23 7.10. QUAD OUTPUT FAST READ (6BH) ............................................................................................................................. 24 7.11. DUAL I/O FAST READ (BBH) .................................................................................................................................... 24 7.12. QUAD I/O FAST READ (EBH) ................................................................................................................................... 26 7.13. QUAD I/O WORD FAST READ (E7H) ......................................................................................................................... 28 7.14. SET BURST WITH WRAP (77H) ................................................................................................................................. 29 7.15. PAGE PROGRAM (PP) (02H) .................................................................................................................................... 30 7.16. QUAD PAGE PROGRAM (32H) .................................................................................................................................. 31 7.17. SECTOR ERASE (SE) (20H) ....................................................................................................................................... 33 7.18. 32KB BLOCK ERASE (BE) (52H) ............................................................................................................................... 34 7.19. 64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 35 7.20. CHIP ERASE (CE) (60/C7H) ..................................................................................................................................... 36 7.21. DEEP POWER-DOWN (DP) (B9H) ............................................................................................................................. 37 7.22. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ......................................................................... 38 7.23. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 40 7.24. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ................................................................................................. 41 7.25. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H)................................................................................................. 42 7.26. READ IDENTIFICATION (RDID) (9FH) ......................................................................................................................... 43 7.27. PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 44 7.28. PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 45 7.29. READ UNIQUE ID (4BH) .......................................................................................................................................... 46 7.30. ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 46 7.31. PROGRAM SECURITY REGISTERS (42H) ....................................................................................................................... 47 2 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.32. READ SECURITY REGISTERS (48H) ............................................................................................................................. 48 7.33. SET READ PARAMETERS (C0H) ................................................................................................................................. 49 7.34. BURST READ WITH WRAP (0CH) ............................................................................................................................... 50 7.35. ENABLE QPI (38H)................................................................................................................................................. 50 7.36. DISABLE QPI (FFH) ................................................................................................................................................ 51 7.37. ENABLE RESET (66H) AND RESET (99H) ..................................................................................................................... 52 LECTRICAL CHARACTERISTICS ................................................................................................................. 53 8. 8.1. POWER-ON TIMING ................................................................................................................................................ 53 8.2. INITIAL DELIVERY STATE ........................................................................................................................................... 53 8.3. ABSOLUTE MAXIMUM RATINGS................................................................................................................................. 53 8.4. CAPACITANCE MEASUREMENT CONDITIONS................................................................................................................. 54 8.5. DC CHARACTERISTICS......................................................................................................................................... 55 8.6. AC CHARACTERISTICS ......................................................................................................................................... 58 ORDERING INFORMATION............................................................................................................................ 62 9. 9.1. 10. VALID PART NUMBERS ............................................................................................................................................ 63 PACKAGE INFORMATION ......................................................................................................................... 65 10.1. PACKAGE SOP8 208MIL ........................................................................................................................................ 65 10.2. PACKAGE VSOP8 208MIL ...................................................................................................................................... 66 10.3. PACKAGE USON8 (3*4MM).................................................................................................................................... 67 10.4. PACKAGE USON8 (4*4MM, THICKNESS 0.45MM) ...................................................................................................... 67 10.5. PACKAGE WSON8 (6*5MM)................................................................................................................................... 69 10.6. PACKAGE WLCSP .................................................................................................................................................. 70 11. REVISION HISTORY ....................................................................................................................................71 3 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 1. FEATURES ◆ ◆ 32M-bit Serial Flash Fast Program/Erase Speed - 4096K-Byte - Page Program time: 0.7ms typical - 256 Bytes per programmable page - Sector Erase time: 90ms typical - Block Erase time: 0.3/0.45s typical ◆ Standard, Dual, Quad SPI, QPI - Chip Erase time: 20s typical - Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# ◆ - Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# Flexible Architecture - Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 - Uniform Sector of 4K-Byte - QPI: SCLK, CS#, IO0, IO1, IO2, IO3 - Uniform Block of 32/64K-Byte - Erase/Program Suspend/Resume ◆ High Speed Clock Frequency ◆ - 120MHz for fast read with 30PF load Low Power Consumption - Dual I/O Data transfer up to 240Mbits/s - 35uA typical stand-by current - Quad I/O Data transfer up to 480Mbits/s - 1μA typical power down current - QPI Mode Data transfer up to 480Mbits/s ◆ ◆Allows XIP (execute in place) Operation - 128-bit Unique ID for each device - Continuous Read With 8/16/32/64-byte Wrap ◆ Advanced security Features - 3x1024-Byte Security Registers With OTP Lock ◆ Software/Hardware Write Protection - Write protect all/portion of memory via software Single Power Supply Voltage - Full voltage range: 1.65~2.0V - Enable/Disable protection with WP# Pin - Top/Bottom Block protection ◆ Minimum 100,000 Program/Erase Cycles ◆ Data Retention - 20-year data retention typical 4 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 2. GENERAL DESCRIPTION The GD25LQ32D (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s. CONNECTION DIAGRAM CS# 1 8 VCC CS# 1 8 SO (IO1) 2 7 HOLD# (IO3) SO (IO1) 2 7 HOLD# (IO3) WP# (IO2) 3 6 SCLK WP# (IO2) 3 VSS 4 5 SI (IO0) Top View Top View VCC 6 SCLK VSS 4 5 SI (IO0) 8–LEAD USON/WSON 8–LEAD SOP TOP VIEW BOTTOM VIEW A1 A2 A3 A3 A2 A1 NC VCC CS# CS# VCC NC B2 B3 B3 B2 HOLD#/ IO3 SO/IO1 SO/IO1 HOLD#/ IO3 C2 C3 C3 C2 SCLK WP#/ IO2 WP#/ IO2 SCLK D1 D2 D3 D3 D2 D1 NC SI/IO0 VSS VSS SI/IO0 NC WLCSP PIN DESCRIPTION Pin Name Ball Name I/O Description CS# A3 I Chip Select Input SO (IO1) B3 I/O Data Output (Data Input Output 1) WP# (IO2) C3 I/O Write Protect Input (Data Input Output 2) VSS D3 SI (IO0) D2 I/O Data Input (Data Input Output 0) SCLK C2 I Serial Clock Input HOLD# (IO3) B2 I/O Hold Input (Data Input Output 3) VCC A2 Ground Power Supply Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. 5 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D BLOCK DIAGRAM Write Control Logic Status Register HOLD#(IO3) SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Protect Logic and Row Decode WP#(IO2) Flash Memory Column Decode And 256-Byte Page Buffer SI(IO0) SO(IO1) Byte Address Latch/Counter 6 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 3. MEMORY ORGANIZATION GD25LQ32D Each device has Each block has Each sector has Each page has 4M 64/32K 4K 256 bytes 16K 256/128 16 - pages 1024 16/8 - - sectors 64/128 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE GD25LQ32D 64K Bytes Block Sector Architecture Block 63 62 …… …… 2 1 0 Sector Address range 1023 3FF000H 3FFFFFH …… …… …… 1008 3F0000H 3F0FFFH 1007 3EF000H 3EFFFFH …… …… …… 992 3E0000H 3E0FFFH …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 7 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 4. DEVICE OPERATION SPI Mode Standard SPI The GD25LQ32D features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25LQ32D supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25LQ32D supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read”, “Quad Page Program” (6BH, EBH, E7H, 32H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set. QPI The GD25LQ32D supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between these two modes. Upon power-up and after software reset using “”Reset (99H)” command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure1. Hold Condition CS# SCLK HOLD# HOLD HOLD 8 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 5. DATA PROTECTION The GD25LQ32D provide the following data protection methods: ◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) -Software reset (66H+99H) -Erase Security Registers / Program Security Registers ◆ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change. ◆ Hardware Protection Mode: WP# goes low to protect the writable bit of Status Register. ◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command and reset command (66H+99H). Table1. GD25LQ32D Protected area size (CMP=0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 63 3F0000H-3FFFFFH 64KB Upper 1/64 0 0 0 1 0 62 to 63 3E0000H-3FFFFFH 128KB Upper 1/32 0 0 0 1 1 60 to 63 3C0000H-3FFFFFH 256KB Upper 1/16 0 0 1 0 0 56 to 63 380000H-3FFFFFH 512KB Upper 1/8 0 0 1 0 1 48 to 63 300000H-3FFFFFH 1MB Upper 1/4 0 0 1 1 0 32 to 63 200000H-3FFFFFH 2MB Upper 1/2 0 1 0 0 1 0 000000H-00FFFFH 64KB Lower 1/64 0 1 0 1 0 0 to 1 000000H-01FFFFH 128KB Lower 1/32 0 1 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/16 0 1 1 0 0 0 to 7 000000H-07FFFFH 512KB Lower 1/8 0 1 1 0 1 0 to 15 000000H-0FFFFFH 1MB Lower 1/4 0 1 1 1 0 0 to 31 000000H-1FFFFFH 2MB Lower 1/2 X X 1 1 1 0 to 63 000000H-3FFFFFH 4MB ALL 1 0 0 0 1 63 3FF000H-3FFFFFH 4KB Top Block 1 0 0 1 0 63 3FE000H-3FFFFFH 8KB Top Block 1 0 0 1 1 63 3FC000H-3FFFFFH 16KB Top Block 1 0 1 0 X 63 3F8000H-3FFFFFH 32KB Top Block 1 0 1 1 0 63 3F8000H-3FFFFFH 32KB Top Block 1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block 1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block 1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block 9 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block 1 1 1 1 0 0 000000H-007FFFH 32KB Bottom Block Table1a. GD25LQ32D Protected area size (CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 ALL 000000H-3FFFFFH 4MB ALL 0 0 0 0 1 0 to 62 000000H-3EFFFFH 4032KB Lower 63/64 0 0 0 1 0 0 to 61 000000H-3DFFFFH 3968KB Lower 31/32 0 0 0 1 1 0 to 59 000000H-3BFFFFH 3840KB Lower 15/16 0 0 1 0 0 0 to 55 000000H-37FFFFH 3584KB Lower 7/8 0 0 1 0 1 0 to 47 000000H-2FFFFFH 3MB Lower 3/4 0 0 1 1 0 0 to 31 000000H-1FFFFFH 2MB Lower 1/2 0 1 0 0 1 1 to 63 010000H-3FFFFFH 4032KB Upper 63/64 0 1 0 1 0 2 to 63 020000H-3FFFFFH 3968KB Upper 31/32 0 1 0 1 1 4 to 63 040000H-3FFFFFH 3840KB Upper 15/16 0 1 1 0 0 8 to 63 080000H-3FFFFFH 3584KB Upper 7/8 0 1 1 0 1 16 to 63 100000H-3FFFFFH 3MB Upper 3/4 0 1 1 1 0 32 to 63 200000H-3FFFFFH 2MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 to 63 000000H-3FEFFFH 4092KB L-1023/1024 1 0 0 1 0 0 to 63 000000H-3FDFFFH 4088KB L-511/512 1 0 0 1 1 0 to 63 000000H-3FBFFFH 4080KB L-255/256 1 0 1 0 X 0 to 63 000000H-3F7FFFH 4064KB L-127/128 1 0 1 1 0 0 to 63 000000H-3F7FFFH 4064KB L-127/128 1 1 0 0 1 0 to 63 001000H-3FFFFFH 4092KB U-1023/1024 1 1 0 1 0 0 to 63 002000H-3FFFFFH 4088KB U-511/512 1 1 0 1 1 0 to 63 004000H-3FFFFFH 4080KB U-255/256 1 1 1 0 X 0 to 63 008000H-3FFFFFH 4064KB U-127/128 1 1 1 1 0 0 to 63 008000H-3FFFFFH 4064KB U-127/128 10 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 6. STATUS REGISTER S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP4, BP3, BP2, BP1, BP0 bits. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. SRP1, SRP0 bits. The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. SRP1 SRP0 #WP Status Register 0 0 X Software Protected 0 1 0 Hardware Protected 0 1 1 Hardware Unprotected 1 0 X Power Supply Lock-Down(1)(2) 1 1 X One Time Program(2) Description The Status Register can be written to after a Write Enable command, WEL=1.(Default) WP#=0, the Status Register locked and cannot be written to. WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. NOTE: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available on special order. Please contact GigaDevice for details. 11 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (It is best to set the QE bit to 0 to avoid short issues if the WP# or HOLD# pin is tied directly to the power supply or ground.) LB3, LB2, LB1 bits. The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once they are set to 1, the Security Registers will become read-only permanently. CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS1, SUS2 bits The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset (66H+99H) command as well as a power-down, power-up cycle. 12 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with most significant bit first on SI, and each bit is latched on the rising edges of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to deselected status. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table2. Commands (Standard/Dual/Quad SPI) Command Name Byte 1 Write Enable Write Disable Volatile SR Write Enable Read Status Register Read Status Register-1 Write Status Register Read Data Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Fast Read Quad I/O Word Fast Read(7) Page Program Quad Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase Enable QPI Enable Reset Reset Set Burst with Wrap 06H 04H 50H Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes 05H (S7-S0) (continuous) 35H (S15-S8) (continuous) 01H 03H 0BH 3BH S7-S0 A23-A16 A23-A16 A23-A16 S15-S8 A15-A8 A15-A8 A15-A8 BBH A23-A8(2) (D7-D0)(1) 6BH A23-A16 A7-A0 M7-M0(2) A15-A8 EBH A23-A0 M7-M0(4) A23-A0 M7-M0(4) A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 dummy(5) (D7-D0)(3) (continuous) dummy(6) (D7-D0)(3) (continuous) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 E7H 02H 32H 20H 52H D8H C7/60H 38H 66H 99H 77H A7-A0 A7-A0 A7-A0 A7-A0 W6-W4 13 (D7-D0) dummy dummy (Next byte) (D7-D0) (D7-D0)(1) (continuous) (continuous) (continuous) (continuous) dummy D7-D0 D7-D0 (D7-D0)(3) Next byte (continuous) 1.8V Uniform Sector Dual and Quad Serial Flash Program/Erase Suspend Program/Erase Resume Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Deep Power-Down Manufacturer/ Device ID Manufacturer/ Device ID by Dual I/O Manufacturer/ Device ID by Quad I/O Read Identification Read Unique ID 75H Erase Security Registers(8) Program Security Registers(8) Read Security Registers(8) GD25LQ32D 7AH ABH dummy dummy dummy (ID7-ID0) (continuous) B9H 90H dummy dummy 00H (M7-M0) 92H A23-A8 (M7-M0) (ID7-ID0) (continuous) 94H A23-A0, M[7:0] A7-A0, M[7:0] dummy (M7-M0) (ID7-ID0) (continuous) 9FH (M7-M0) (ID15-ID8) (ID7-ID0) 4BH 00H 00H 00H 44H A23-A16 A15-A8 A7-A0 42H A23-A16 A15-A8 48H A23-A16 A15-A8 ABH (ID7-ID0) dummy (UID7-UID0) A7-A0 D7-D0 D7-D0 A7-A0 dummy (D7-D0) (continuous) (continuous) (continuous) Table2a. Commands (QPI) Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Clock Number (0,1) (2,3) (4,5) (6,7) (8,9) (10,11) (12,13) Write Enable Volatile SR Write Enable Write Disable Read Status Register Read Status Register-1 Read Status Register-2 Write Status Register Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase Program/Erase Suspend Program/Erase Resume Deep Power-Down Set Read Parameters Fast Read Burst Read with Wrap Quad I/O Fast Read Release From Deep Power-Down, And Read Device ID Manufacturer/ Device ID 06H 50H 04H 05H 35H 15H 01H 02H 20H 52H D8H C7/60H 75H 7AH B9H C0H 0BH 0CH EBH ABH (S7-S0) (S15-S8) (S1-S0) S7-S0 A23-A16 A23-A16 A23-A16 A23-A16 S15-S8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 D7-D0 Next byte P7-P0 A23-A16 A23-A16 A23-A16 dummy A15-A8 A15-A8 A15-A8 dummy A7-A0 A7-A0 A7-A0 dummy dummy dummy M7-M0 (ID7-ID0) dummy dummy dummy 90H dummy dummy 00H (M7-M0) (ID7-ID0) 14 (D7-D0) (D7-D0) (D7-D0) 1.8V Uniform Sector Dual and Quad Serial Flash Read Identification Disable QPI Enable Reset Reset 9FH FFH 66H 99H (M7-M0) GD25LQ32D (ID15-ID8) (ID7-ID0) NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) 7. Fast Word Read Quad I/O Data: the lowest address bit must be 0. 8. Security Registers Address: Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address; Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address; Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address. 9. QPI Command, Address, Data input/output format: CLK #0 1 2 3 4 5 6 7 8 9 10 11 IO0= C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0, IO1= C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1 IO2= C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2 IO3= C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3 15 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Table of ID Definitions: GD25LQ32D Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH C8 60 16 90H C8 15 ABH 15 16 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes high. Figure2. Write Enable Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 Command 06H High-Z Figure2a. Write Enable Sequence Diagram (QPI) CS# 0 1 SCLK Command 06H IO0 IO1 IO2 IO3 17 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Figure3. Write Disable Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 Command 04H High-Z Figure3a. Write Disable Sequence Diagram (QPI) CS# 0 1 SCLK Command 04H IO0 IO1 IO2 IO3 18 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.3. Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command, and any other commands can't be inserted between them. Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. Figure4. Write Enable for Volatile Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command(50H) SI SO High-Z Figure4a. Write Enable for Volatile Status Register Sequence Diagram (QPI) CS# 0 1 SCLK Command 50H IO0 IO1 IO2 IO3 19 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.4. Read Status Register (RDSR) (05H or 35H or 15H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H” / “35H”, the SO will output Status Register bits S7~S0 / S15-S8. The command code “15H” only supports the QPI mode, the I/O0 will output Status Register S1-S0. (For 120MHz Frequency, the 15H will better than 05H to check the WIP bit) Figure5. Read Status Register Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Command 05H or 35H SO High-Z 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 MSB 7 S7~S0 or S15~S8 out 6 5 4 3 2 1 0 MSB Figure5a. Read Status Register Sequence Diagram (QPI) CS# 0 1 2 3 4 5 SCLK Command 05H or 35H IO0 4 0 4 0 4 IO1 5 1 5 1 5 IO2 6 2 6 2 6 IO3 7 3 7 3 7 S7-S0 or S15-S8 out Figure5b. Read Status Register Sequence Diagram (QPI) (15H) CS# 0 1 2 3 4 5 SCLK Command 15H S1 IO0 S0 S1 S1-S0 out IO1 IO2 IO3 20 S0 7 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.5. Write Status Register (WRSR) (01H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE bits will be cleared to 0 in SPI mode, while only CMP will be cleared to 0 in QPI mode. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. Figure6. Write Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Command SI 01H Status Register in 7 6 5 MSB SO 4 3 2 1 0 15 14 13 12 11 10 9 High-Z Figure6a. Write Status Register Sequence Diagram (QPI) CS# 0 2 1 3 5 4 SCLK Command 01H IO0 4 0 12 8 IO1 5 1 13 9 IO2 6 2 14 10 IO3 7 3 15 11 Status Register in 21 8 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.6. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the rising edge of SCLK. Then the memory content at that address is shifted out on SO, and each bit is shifted out, at a Max frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure7. Read Data Bytes Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI 24-bit address 23 22 21 03H 2 1 0 MSB High-Z SO 3 MSB 7 6 5 Data Out1 4 3 2 1 Data Out2 0 7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure8. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 0BH 3 23 22 21 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 7 6 MSB 22 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.8. Fast Read (0BH) in QPI mode The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. Figure8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SCLK IOs switch from Input to output Command 0BH IO0 A23-16 A15-8 20 16 12 8 A7-0 4 0 IO1 21 17 13 9 5 IO2 22 18 14 10 IO3 23 19 15 11 Dummy* Dummy* 4 0 4 0 4 0 4 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte1 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 7.9. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure9. Dual Output Fast Read Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24-bit address 23 22 21 3BH 3 2 1 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks SI SO 0 6 Data Out1 Data Out2 7 5 3 1 7 5 3 1 MSB MSB 7 6 23 4 2 0 6 4 2 0 1.8V Uniform Sector Dual and Quad Serial Flash 7.10. GD25LQ32D Quad Output Fast Read (6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad Output Fast Read command. Figure10. Quad Output Fast Read Sequence Diagram CS# 0 1 2 3 4 5 6 8 7 9 10 28 29 30 31 SCLK 24-bit address Command SI(IO0) 23 22 21 6BH SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z 3 2 1 0 CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks 7.11. SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 Dual I/O Fast Read (BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure11a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. 24 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Figure11. Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0)) CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Command SI(IO0) BBH SO(IO1) A23-16 A15-8 A7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 Figure11a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0)) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 CS# SCLK 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 25 Byte4 M7-0 1.8V Uniform Sector Dual and Quad Serial Flash 7.12. GD25LQ32D Quad I/O Fast Read (EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure12. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK Command SI(IO0) EBH A23-16 A15-8 A7-0 Dummy M7-0 Byte1 Byte2 Figure12a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0)) CS# 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 26 Dummy Byte1 Byte2 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. Quad I/O Fast Read (EBH) in QPI mode The Quad I/O Fast Read command is also supported in QPI mode. See Figure12b. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. In QPI mode, the “Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O Fast Read command. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0CH) command must be used. Figure12b. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0) QPI) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCLK IOs switch from Input to output Command EBH IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 A23-16 7 3 7 A15-8 A7-0 3 7 3 7 3 7 M7-0* dummy* Byte1 Byte2 27 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 1.8V Uniform Sector Dual and Quad Serial Flash 7.13. GD25LQ32D Quad I/O Word Fast Read (E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must be equal 0 and there are only 2-dummy clocks. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing normal command. Figure13. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK Command SI(IO0) E7H A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Figure13a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0)) CS# 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK 8 9 10 11 12 13 14 15 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 28 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. 7.14. Set Burst with Wrap (77H) The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page. The Set Burst with Wrap command sequence: CS# goes low  Send Set Burst with Wrap command  Send 24 dummy bits  Send 8 bits “Wrap bits”  CS# goes high. W6,W5 W4=0 W4=1 (default) Wrap Around Wrap Length Wrap Around Wrap Length 0, 0 Yes 8-byte No N/A 0, 1 Yes 16-byte No N/A 1, 0 Yes 32-byte No N/A 1, 1 Yes 64-byte No N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should be used to perform the Read Operation with “Wrap Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0H) command. Figure14. Set Burst with Wrap Sequence Diagram CS# 0 8 9 10 11 12 13 14 15 x x x x x x 4 x SO(IO1) x x x x x x 5 x WP#(IO2) x x x x x x 6 x HOLD#(IO3) x x x x x x x x SCLK 1 2 3 4 5 6 7 Command SI(IO0) 77H W6-W4 29 1.8V Uniform Sector Dual and Quad Serial Flash 7.15. GD25LQ32D Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI  at least 1 byte data on SI  CS# goes high. The command sequence is shown in Figure15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed. Figure15. Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 8 7 28 29 30 31 32 33 34 35 36 37 38 39 9 10 SCLK 24-bit address Command 23 22 21 2 3 Data Byte 1 6 0 7 1 MSB 4 5 2 3 1 2078 2079 6 2076 7 2077 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 CS# 2072 MSB 2075 02H 2074 SI 1 0 SCLK Data Byte 3 Data Byte 2 SI 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 MSB 2 Data Byte 256 1 0 MSB 30 5 4 3 2 0 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Figure15a. Page Program Sequence Diagram (QPI) 3 4 5 6 7 8 9 10 11 12 13 519 2 518 1 517 0 516 CS# SCLK Command A23-16 A15-8 20 16 12 8 A7-0 4 0 Byte1 Byte2 Byte3 IO0 4 0 4 0 4 0 4 0 4 0 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 02H 7.16. Byte255 Byte256 Quad Page Program (32H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO pins. The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is not executed. 31 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Figure16.Quad Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI(IO0) 24-bit address 3 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 539 540 541 542 543 1 537 2 538 32H Byte1 Byte2 23 22 21 MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 536 CS# SCLK Byte11 Byte12 Byte253 Byte256 SI(IO0) 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 0 4 0 4 0 4 0 4 0 4 0 4 32 0 4 0 4 0 4 0 4 0 4 0 1.8V Uniform Sector Dual and Quad Serial Flash 7.17. GD25LQ32D Sector Erase (SE) (20H) The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed. Figure17. Sector Erase Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 Command SI 29 30 31 24 Bits Address 20H 2 23 22 MSB 1 0 Figure17a. Sector Erase Sequence Diagram (QPI) CS# 0 1 2 3 4 5 6 7 SCLK Command 20H A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 33 1.8V Uniform Sector Dual and Quad Serial Flash 7.18. GD25LQ32D 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed. Figure18. 32KB Block Erase Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 Command SI 29 30 31 24 Bits Address 52H 2 23 22 MSB 1 0 Figure18a. 32KB Block Erase Sequence Diagram (QPI) CS# 0 1 2 3 4 5 6 7 SCLK Command 52H A23-16 A12-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 34 1.8V Uniform Sector Dual and Quad Serial Flash 7.19. GD25LQ32D 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed. Figure19. 64KB Block Erase Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 Command SI 29 30 31 24 Bits Address D8H 2 23 22 MSB 1 0 Figure19a. 64KB Block Erase Sequence Diagram (QPI) CS# SCLK 0 1 2 3 4 6 5 7 Command A23-16 A15-8 A7-0 IO0 20 16 12 8 4 0 IO1 21 17 13 9 5 1 IO2 22 18 14 10 6 2 IO3 23 19 15 11 7 3 D8H 35 1.8V Uniform Sector Dual and Quad Serial Flash 7.20. GD25LQ32D Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors are protected. Figure20. Chip Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 60H or C7H Figure20a. Chip Erase Sequence Diagram (QPI) CS# 0 1 SCLK Instruction C7H/60H IO0 IO1 IO2 IO3 36 1.8V Uniform Sector Dual and Quad Serial Flash 7.21. GD25LQ32D Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) (ABH) or Enable Reset (66H) and Reset (99H) commands. These commands can release the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command releases the device from deep power down mode , also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-Up. The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure21. Deep Power-Down Sequence Diagram CS# SCLK Command SI tDP 0 1 2 3 4 5 6 7 Stand-by mode Deep Power-down mode B9H Figure21a. Deep Power-Down Sequence Diagram (QPI) CS# SCLK 0 tDP 1 Command B9H IO0 IO1 IO2 IO3 Stand-by mode 37 Deep Power-down mode 1.8V Uniform Sector Dual and Quad Serial Flash 7.22. GD25LQ32D Release from Deep Power-Down and Read Device ID (RDI) (ABH) The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the GD25LQ32D is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure22. Release Power-Down Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 t RES1 7 Command SI ABH Deep Power-down mode Stand-by mode Figure22a. Release Power-Down Sequence Diagram (QPI) CS# tRES1 SCLK 0 1 Command ABH IO0 IO1 IO2 IO3 Deep Power-down mode 38 Stand-by mode 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Figure23. Release Power-Down/Read Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 29 30 31 32 33 34 35 36 37 38 9 SCLK SI 23 22 ABH 2 1 0 MSB High-Z SO t RES2 3 Dummy Bytes Command 7 Device ID 5 4 3 2 6 MSB 1 0 Deep Power-down Mode Stand-by Mode Figure23a. Release Power-Down/Read Device ID Sequence Diagram (QPI) CS# tRES2 SCLK 0 1 Command 2 3 4 5 6 8 7 IOs switch from Input to Output 3 Dummy Bytes ABH IO0 4 0 IO1 5 1 IO2 6 2 IO3 7 3 Device ID Deep Power-down mode 39 Stand-by mode 1.8V Uniform Sector Dual and Quad Serial Flash 7.23. GD25LQ32D Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure24. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 23 22 21 90H SO CS# 3 2 1 0 High-Z 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 32 SCLK SI SO 7 Manufacturer ID 6 5 4 3 2 1 MSB Device ID 0 7 6 5 4 3 2 1 0 MSB Figure24a. Read Manufacture ID/ Device ID Sequence Diagram (QPI) CS# SCLK 0 1 Command 2 3 4 6 5 7 IO0 A7-0 A23-16 A15-8 (00H) 20 16 12 8 4 0 IO1 21 17 13 9 5 IO2 22 18 14 10 IO3 23 19 15 90H 11 9 8 10 IOs switch from Input to Output 4 0 4 0 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 MID 40 Device ID 1.8V Uniform Sector Dual and Quad Serial Flash 7.24. GD25LQ32D Read Manufacture ID/ Device ID Dual I/O (92H) The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O. The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure25. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 Command SI(IO0) 92H SO(IO1) 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 6 5 3 1 7 A7-0 4 2 0 5 3 1 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI(IO0) 6 SO(IO1) 7 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID Device ID 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID (Repeat) 41 Device ID (Repeat) 4 2 0 6 4 2 0 5 3 1 7 5 3 1 MFR ID (Repeat) Device ID (Repeat) 1.8V Uniform Sector Dual and Quad Serial Flash 7.25. GD25LQ32D Read Manufacture ID/ Device ID Quad I/O (94H) The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure26. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram CS# 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 0 1 2 3 4 5 6 7 SCLK Command SI(IO0) 94H A23-16 A15-8 A7-0 M7-0 CS# 24 25 26 27 28 29 30 31 SCLK SI(IO0) 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 MFR ID DID MFR ID DID (Repeat)(Repeat)(Repeat)(Repeat) 42 Dummy MFR ID DID 1.8V Uniform Sector Dual and Quad Serial Flash 7.26. GD25LQ32D Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The command sequence is shown in Figure27. The Read Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure27. Read Identification ID Sequence Diagram CS# 0 1 2 3 4 5 6 8 9 10 11 12 13 14 15 7 6 7 SCLK SI 9FH SO Manufacturer ID 5 4 3 2 1 0 MSB CS# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI Memory Type ID15-ID8 7 6 5 4 3 2 1 0 SO Capacity ID7-ID0 6 5 4 3 2 1 7 0 MSB MSB Figure27a. Read Identification ID Sequence Diagram (QPI) CS# 0 2 1 3 6 5 4 SCLK IOs switch from Input to Output Command 9FH IO0 4 0 12 8 4 0 IO1 5 1 13 9 5 1 IO2 6 2 14 10 6 2 IO3 7 3 15 11 7 3 MID 43 ID15-8 ID7-0 1.8V Uniform Sector Dual and Quad Serial Flash 7.27. GD25LQ32D Program/Erase Suspend (PES) (75H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. The Write Status Register command (01H) and Erase/Program Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command (02H, 32H) are not allowed during Program suspend. The Write Status Register command (01H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure28. Figure28. Program/Erase Suspend Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 tSUS Command 75H High-Z Accept read command Figure28a. Program/Erase Suspend Sequence Diagram (QPI) CS# SCLK 0 tSUS 1 Command 75H IO0 IO1 IO2 IO3 Accept Read 44 1.8V Uniform Sector Dual and Quad Serial Flash 7.28. GD25LQ32D Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure29. Figure29. Program/Erase Resume Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 7AH SO Resume Erase/Program Figure29a. Program/Erase Resume Sequence Diagram (QPI) CS# SCLK 0 1 Command 7AH IO0 IO1 IO2 IO3 Resume previously suspended program or Erase 45 1.8V Uniform Sector Dual and Quad Serial Flash 7.29. GD25LQ32D Read Unique ID (4BH) The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3-Byte Address (000000H) Dummy Byte128bit Unique ID Out CS# goes high. Figure30. Read Unique ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK 24-bit address (000000H) 23 22 21 3 2 Command SI 4BH 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 7 6 MSB SO 7.30. Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Erase Security Registers (44H) The GD25LQ32D provides three 1024-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  3-byte address on SI CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 46 A11-10 00 00 00 A9-0 Don’t care Don’t care Don’t care 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Figure31. Erase Security Registers command Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 Command SI 7.31. 29 30 31 24 Bits Address 23 22 MSB 44H 2 1 0 Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. Each security register contains four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11-10 00 00 00 A9-0 Byte Address Byte Address Byte Address Figure32. Program Security Registers command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 23 22 21 3 2 1 0 7 MSB 5 4 3 2 1 2078 2079 6 2077 7 2076 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CS# 6 MSB 2075 42H Data Byte 1 2074 SI 24-bit address 1 0 SCLK Data Byte 3 Data Byte 2 SI 7 6 MSB 5 4 3 2 1 0 7 6 5 4 3 MSB 2 Data Byte 256 1 0 MSB 47 5 4 3 2 0 1.8V Uniform Sector Dual and Quad Serial Flash 7.32. GD25LQ32D Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high. Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11-10 00 00 00 A9-0 Byte Address Byte Address Byte Address Figure33. Read Security Registers command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 48H 3 23 22 21 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 7 6 MSB 48 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 1.8V Uniform Sector Dual and Quad Serial Flash 7.33. GD25LQ32D Set Read Parameters (C0H) In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy clocks for “Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. The “Wrap Length” is set by W5-6 bit in the “Set Burst with Wrap (77H)” command. This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode. Maximum Read Freq. P5-P4 Dummy Clocks 00 01 10 11 4 4 6 8 -40℃~105℃ -40℃~85℃ P1-P0 Wrap Length 00 01 10 11 8-byte 16-byte 32-byte 64-byte -40℃~125℃ 80MHz 80MHz 108MHz 120MHz 60MHz 60MHz 70MHz 80MHz Figure34. Set Read Parameters command Sequence Diagram CS# 0 1 2 3 SCLK Command C0H Read Parameters IO0 P4 P0 IO1 P5 P1 IO2 P6 P2 IO3 P7 P3 49 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 7.34. Burst Read with Wrap (0CH) The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with “Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0H)” command. Figure35. Burst Read with Wrap command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCLK IOs switch from Input to output Command 0CH IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 A23-16 A15-8 Dummy* A7-0 Byte1 Byte2 *"Set Read Parameters" Command (C0H) can set the number of dummy clocks 7.35. Enable QPI (38H) The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and “Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored and the device will remain in SPI mode. When the device is switched from SPI mode to QPI mode, the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure36. Enable QPI mode command Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 Command 38H 50 6 7 1.8V Uniform Sector Dual and Quad Serial Flash 7.36. GD25LQ32D Disable QPI (FFH) To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. Figure37. Disable QPI mode command Sequence Diagram CS# 0 1 SCLK Command FFH IO0 IO1 IO2 IO3 51 1.8V Uniform Sector Dual and Quad Serial Flash 7.37. GD25LQ32D Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset (99H)” and the “Reset (99H)” command sequence is as followed: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST =30μs / tRST_E =12ms to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure38. Enable Reset and Reset command Sequence Diagram CS# 0 SCLK SI 1 2 3 4 5 6 7 0 1 2 3 4 5 Command Command 66H 99H 6 7 High-Z SO Figure39. Enable Reset and Reset command Sequence Diagram (QPI) CS# 0 0 1 1 SCLK Command 99H Command 66H IO0 IO1 IO2 IO3 52 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D 8. LECTRICAL CHARACTERISTICS 8.1. Power-On Timing Figure40. Power-On Timing Sequence Diagram Vcc(max) Chip Selection is not allowed Vcc(min) tVSL Device is fully accessible VWI Time Table3. Power-Up Timing and Write Inhibit Threshold Symbol Parameter tVSL VCC (min) To CS# Low VWI Write Inhibit Voltage Min Max 1.8 1 Unit ms 1.4 V 8.2. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFH). The Status Register contains 00H (all Status Register bits are 0). 8.3. Absolute Maximum Ratings Parameter Value Ambient Operating Temperature Unit -40 to 85 -40 to 105 ℃ -40 to 125 ℃ Storage Temperature -65 to 150 Applied Input/Output Voltage -0.6 to VCC+0.4 V Transient Input/Output Voltage (note: overshoot) -2.0 to VCC+2.0 V -0.6 to 2.5 V VCC 53 1.8V Uniform Sector Dual and Quad Serial Flash GD25LQ32D Figure41. Input Test Waveform and Measurement Level Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns 8.4. Capacitance Measurement Conditions Symbol Parameter Min Typ Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 pF Input Rise And Fall time 5 ns Input Pause Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure42. Input Test Waveform and Measurement Level Input timing reference level 0.8VCC 0.7VCC 0.1VCC 0.2VCC Output timing reference level AC Measurement Level Note: Input pulse rise and fall time are