TC58CVG2S0HRAIG

TC58CVG2S0HRAIG KIOXIA 4Gb 3.3V Serial Interface NAND Technical Data Sheet Rev. 2.0 2019 – 10 – 01 KIOXIA Coporation © 2016-2019 KIOXIA Corporation 1 2019-10-01 TC58CVG2S0HRAIG CONTENTS 1. Introduction ............................................................................................................................................................ 5 1.1. General Description ......................................................................................................................................... 5 1.2. Definitions and Abbreviations .......................................................................................................................... 5 1.3. Features .......................................................................................................................................................... 6 2. Memory Organization ............................................................................................................................................ 7 2.1. Pin Descriptions .............................................................................................................................................. 7 2.2. Pin Assignment (Top View) .............................................................................................................................. 7 2.3. Block Diagram ................................................................................................................................................. 8 2.4. Cell Layout ...................................................................................................................................................... 8 2.5. Addressing ...................................................................................................................................................... 9 2.6. Valid Blocks ..................................................................................................................................................... 9 3. Physical Interface ................................................................................................................................................ 10 3.1. Absolute Maximum Rating ............................................................................................................................. 10 3.2. Capacitance .................................................................................................................................................. 10 3.3. DC Operating Conditions............................................................................................................................... 10 3.4. Signal Timing .................................................................................................................................................. 11 3.5. AC Characteristics ......................................................................................................................................... 13 3.6. DC Operating Characteristics ........................................................................................................................ 13 3.7. Programming, Reading and Erasing Characteristics ..................................................................................... 14 3.8. Power ON/OFF Sequence............................................................................................................................. 14 3.9. AC Test Condition .......................................................................................................................................... 14 4. Command Description and Device Operation ................................................................................................... 15 4.1. Command Set ............................................................................................................................................... 15 4.2. Page Read Operation .................................................................................................................................... 16 4.2.1. Read Cell Array (13h) .......................................................................................................................... 16 4.2.2. Read Buffer (03h or 0Bh)..................................................................................................................... 17 4.2.3. Read Buffer x2 (3Bh) ........................................................................................................................... 18 4.2.4. Read Buffer x4 (6Bh) ........................................................................................................................... 19 4.3. Page Read Operation - High Speed Mode .................................................................................................... 19 4.4. Page Program Operation............................................................................................................................... 20 4.4.1. Program Load (02h) ............................................................................................................................ 20 4.4.2. Program Execute (10h) ....................................................................................................................... 21 4.4.3. Program Load Random Data (84h) ..................................................................................................... 22 4.5. 4.6. 4.7. 4.8. 4.9. Internal Data Move Operation ....................................................................................................................... 22 Block Erase (D8h) ......................................................................................................................................... 23 Reset (FFh or FEh)........................................................................................................................................ 24 Write Enable (06h) / Write Disable (04h) ....................................................................................................... 25 Set Feature (1Fh) / Get Feature (0Fh)........................................................................................................... 26 4.9.1. Set Feature (1Fh) ................................................................................................................................ 29 4.9.2. Get Feature (0Fh)................................................................................................................................ 29 4.10. Block Lock Operation .................................................................................................................................... 30 4.11. Block Protection Operation (One Time Program) .......................................................................................... 30 4.11.1. Protect Execute (2Ah)........................................................................................................................ 31 4.12. Parameter Page Read Operation .................................................................................................................. 32 4.13. Read ID (9Fh) ................................................................................................................................................ 33 4.14. Unique ID Read Operation ............................................................................................................................ 33 4.15. Bad Block Inhibit ............................................................................................................................................ 33 4.16. Internal ECC .................................................................................................................................................. 34 4.16.1. 4.16.2. 4.16.3. 4.16.4. 4.16.5. ECC Switch ....................................................................................................................................... 34 ECC Status........................................................................................................................................ 34 ECC Bit Flip Count Detection ............................................................................................................ 34 ECC Bit Flip Count Report................................................................................................................. 35 ECC Maximum Bit Flip Count Report ................................................................................................ 36 © 2016-2019 KIOXIA Corporation 2 2019-10-01 TC58CVG2S0HRAIG 5. Package Information............................................................................................................................................ 37 5.1. WSON8 (P-WSON8-0608-1.27-003) ............................................................................................................. 37 6. Application Notes ................................................................................................................................................ 38 6.1. Prohibition of Unspecified Commands........................................................................................................... 38 6.2. Restriction of Commands while in the Busy State ......................................................................................... 38 6.3. Addressing for Page Program Operation....................................................................................................... 38 6.4. Several Programming Cycles on the Same Page (Partial Page Program) .................................................... 38 6.5. Power Off Timing ........................................................................................................................................... 39 6.6. Invalid Blocks (Bad Blocks) ........................................................................................................................... 39 6.7. Failure Phenomena ....................................................................................................................................... 40 6.8. Reliability Guidance ....................................................................................................................................... 41 6.9 NAND Management ...................................................................................................................................... 42 7. Revision History................................................................................................................................................... 43 RESTRICTIONS ON PRODUCT USE ........................................................................................................................... 44 © 2016-2019 KIOXIA Corporation 3 2019-10-01 TC58CVG2S0HRAIG LIST of FIGURES Figure 1. WSON8 Pin Assignment .............................................................................................................................. 7 Figure 2. Block Diagram .............................................................................................................................................. 8 Figure 3. Cell Layout ................................................................................................................................................... 8 Figure 4. Addressing.................................................................................................................................................... 9 Figure 5. SPI Timing .................................................................................................................................................. 11 Figure 6. Serial Input Timing...................................................................................................................................... 11 Figure 7. Serial Output Timing ................................................................................................................................... 11 Figure 8. Hold Timing ................................................................................................................................................ 12 Figure 9. WP Timing (Example) ................................................................................................................................. 12 Figure 10. Power ON/OFF Timing ............................................................................................................................. 14 Figure 11. Page Read from Cell Array to Buffer......................................................................................................... 16 Figure 12. Page Read from Buffer Timing ................................................................................................................. 17 Figure 13. Page Read from Buffer x2 Timing ............................................................................................................ 18 Figure 14. Page Read from Buffer x4 Timing ............................................................................................................ 19 Figure 15. Program Load........................................................................................................................................... 20 Figure 16. Program Execute Timing .......................................................................................................................... 21 Figure 17. Program Load Random Data Timing ........................................................................................................ 22 Figure 18. Block Erase Timing ................................................................................................................................... 23 Figure 19. Reset Timing ............................................................................................................................................ 24 Figure 20. Write Enable Timing ................................................................................................................................. 25 Figure 21. Write Disable Timing................................................................................................................................. 25 Figure 22. Set Feature Timing ................................................................................................................................... 29 Figure 23. Get Feature Timing ................................................................................................................................... 29 Figure 24. Protect Execute Timing ............................................................................................................................ 31 Figure 25. Read ID Timing ......................................................................................................................................... 33 LIST of TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Pin Descriptions.......................................................................................................................................... 7 Valid Blocks ................................................................................................................................................ 9 Absolute Maximum Rating ........................................................................................................................ 10 Capacitance (TOPR = 25°C, f = 1MHz) ...................................................................................................... 10 DC Operating Condition ........................................................................................................................... 10 AC Characteristics (TOPR = −40 to 85°C, VCC = 2.7 to 3.6V) ................................................................... 13 DC & Operating Characteristics (TOPR = −40 to 85°C, VCC = 2.7 to 3.6V) ............................................... 13 Programming, Reading and Erasing Characteristics (TOPR = −40 to 85°C, VCC = 2.7 to 3.6V)................ 14 Power on Timing ....................................................................................................................................... 14 AC Test Condition ..................................................................................................................................... 14 Command Set ........................................................................................................................................... 15 Feature Table ........................................................................................................................................... 26 Feature Table - A0h Address Description ................................................................................................. 27 Feature Table - B0h Address Description ................................................................................................. 27 Feature Table - C0h Address Description ................................................................................................. 28 Block Lock Setting .................................................................................................................................... 30 Block Protection Setting ........................................................................................................................... 30 Block Number for Block Protection ........................................................................................................... 30 Parameter Page ....................................................................................................................................... 32 ID Table .................................................................................................................................................... 33 Page Assignment ..................................................................................................................................... 34 Definition of 528 bytes Data Pair .............................................................................................................. 34 Bit Flip Count Detection Setting (BFD) ..................................................................................................... 34 Bit Flip Count Detection Status (BFS) (Feature Table - 20h Address Description) ................................... 35 Bit Flip Count Report for Sector 0 (BFR) .................................................................................................. 35 Sector Definition (BFR) ............................................................................................................................ 36 Maximum Bit Flip Count (MBF) ................................................................................................................ 36 Maximum Bit Flip Count Sector (MFS) ..................................................................................................... 36 © 2016-2019 KIOXIA Corporation 4 2019-10-01 TC58CVG2S0HRAIG 1. Introduction 1.1. General Description The TC58CVG2S0HRAIG is a Serial Interface NAND Flash memory for embedded applications which supports the SPI interface. The TC58CVG2S0HRAIG is organized as (4096 + 128) bytes × 64 pages × 2048 blocks. The device has a 4224 byte data buffer which allows program and read data to be transferred between the buffer and the memory cell array in 4224-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 8 Kbytes: 4224 bytes × 64 pages). The device has the high speed mode for sequential Page Read operation. When high speed mode is enabled, the average of tR is shortened. The TC58CVG2S0HRAIG has ECC logic on the chip and 8bit read errors for each (512 bytes + 16 bytes) can be corrected. The internal ECC logic has detailed Bit Flip Count Report. 1.2. Definitions and Abbreviations SPI Serial Peripheral Interface Address The address is comprised of a column address (CA) with 13 bits and a row address (RA) with 17 bits. The row address identifies the page and block to be accessed. The column address identifies the byte within a page to access. Column The byte location within the page Row Refer to the block and page to be accessed Sector The (512 bytes+16 bytes) unit in a page Page The smallest addressable unit for the Read and the Program operations Block Consists of multiple pages and is the smallest addressable unit for the Erase operation. Data Buffer Buffer used to transfer data to and from the cell array Cell Array Memory cells of NAND Flash Device The packaged NAND unit ECC Error Correction Code © 2016-2019 KIOXIA Corporation 5 2019-10-01 TC58CVG2S0HRAIG 1.3. Features  Organization Organization (Internal ECC is enabled, default) Memory Cell Array 4224 × 64 × 2048 × 8 bits Data Buffer 4224 × 8 bits Page Size 4224 bytes Block Size (256K + 8K) bytes Organization (Internal ECC is disabled) Memory Cell Array 4352 × 64 × 2048 × 8 bits Data Buffer 4352 × 8 bits Page Size 4352 bytes Block Size (256K + 16K) bytes  ECC The device has ECC logic internally. When internal ECC is disabled, 8 bit ECC for each 512 bytes is required.  Mode Page Read, Page Program, Block Erase, Internal Data Move, Reset, Write Enable, Write Disable, Block Lock, Get Feature, Set Feature, Block Protection, Parameter Page Read, Read ID, Unique ID Read  Power Supply VCC = 2.7 V to 3.6 V  Access Time Cell Array to Data Buffer   Data Transfer rate 280 115 104 s max s typ. MHz max Program/Erase Time Programming Time Block Erasing Time 450 2.0 s/page typ. ms/block typ. Operating Current Read Operation Current with HSE ON (Average) 21 Read Operation Current with HSE OFF (Average) 15 Program Operation Current (Average) 18 Erase Operation Current (Average) 22 Standby Current 180 35  Reliability Refer to reliability note  Package WSON8 (P-WSON8-0608-1.27-003)  mA max mA max mA max mA max A max A typ. Weight: 0.12 g typ. Part Numbering Information TC58CVG2S0HRAIG 4Gb, 3.3V, WSON8 Serial Interface NAND © 2016-2019 KIOXIA Corporation 6 2019-10-01 TC58CVG2S0HRAIG 2. Memory Organization 2.1. Pin Descriptions Table 1 Pin Descriptions Pin Name ---------- CS SO/SO1 ------------ WP/SO2 SI/SO0 ------------------ HOLD/SO3 SCK VCC VSS Pin Function Chip Select Serial Data Output / Serial Data Output 1 Write Protect / Serial Data Output 2 Serial Data Input / Serial Data Output 0 Hold Input / Serial Data Output 3 Serial Clock Input Power Supply Ground ---------- Note: If the WP pin is low and BRWD bit is set to 1, the overwriting for the BRWD (bit [7]) and the BL bits (bits [5:3]) in address A0h of the feature table shown in Table 12 is prohibited.----------------The users should keep the status of WP signal while CS pin is low. --------------------------The HOLD pin and the WP pin are pull up to VCC internally. 2.2. Pin Assignment (Top View) 1 8 SO/SO1 2 7 WP /SO2 3 6 SCK VSS 4 5 SI/SO0 CS VCC HOLD/SO3 Figure 1. WSON8 Pin Assignment © 2016-2019 KIOXIA Corporation 7 2019-10-01 TC58CVG2S0HRAIG 2.3. Block Diagram VCC VSS ECC Logic Control Logic ---------- CS Data Buffer SO/SO1 ------------ W P /SO2 Command Register Memory cell array SI/SO0 ------------------- Address Register HOL D /SO3 SCK Status Register Figure 2. Block Diagram 2.4. Cell Layout The Program operation works on page units while the Erase operation works on block units. When internal ECC is turned ON, a page consists of 4224 bytes in which 4096 bytes are used for main memory storage and 128 bytes are used for redundancy or for other uses. In the case that internal ECC is turned OFF, the redundancy area will be expanded to 256 bytes automatically. Data Cache 1 4096 128 Data Cache 1 4096 256 Data Cache 0 4096 128 Data Cache 0 4096 256 64 Pages=1 block 64 Pages=1 block 131072 pages 2048 blocks 131072 Pages 2048 blocks 8 bits 8 bits 4352 4224 Internal ECC = ON Internal ECC = OFF Figure 3. Cell Layout © 2016-2019 KIOXIA Corporation 8 2019-10-01 TC58CVG2S0HRAIG 2.5. Addressing There are two address types used; the column address and the row address. The column address is used to access bytes within a page. The row address is used to address pages and blocks. There are some operations that may require only row addresses, such as Block Erase. Row Address (RA): 17 bits Block Address (2048 blocks/device) Page Address (64 pages/block) : 11 bits : 6 bits Column Address (CA): 13 bits Column Address (4224 or 4352 bytes/page) : 13 bits MSB LSB Block Address Page Address Column Address Row Address Figure 4. Addressing 2.6. Valid Blocks Table 2 Valid Blocks SYMBOL PARAMETER MIN TYP. MAX UNIT NVB Number of Valid (Good) Blocks 2008 - 2048 Block Note: The device occasionally contains unusable blocks. The first block (Block 0) is guaranteed to be a valid block at the time of shipment. The specification for the minimum number of valid blocks is applicable over the lifetime. © 2016-2019 KIOXIA Corporation 9 2019-10-01 TC58CVG2S0HRAIG 3. Physical Interface 3.1. Absolute Maximum Rating Stresses greater than those listed in Table 3 may cause permanent damage to the device. This is a stress rating only. Table 3 Absolute Maximum Rating Symbol Parameter Value Unit −0.3 to 3.9 V VCC Power Supply Voltage VIN Input Voltage −0.3 to VCC +0.3 (≤ 3.9 V) V VI/O Input /Output Voltage −0.3 to VCC +0.3 (≤ 3.9 V) V PD1 Power Dissipation 1 0.42 W PD2 Power Dissipation 2 (WSON8 ePAD without solder) 0.27 W TSOLDER Soldering Temperature (10 s) 260 °C TSTG Storage Temperature −55 to 150 °C TOPR Operating Temperature −40 to 85 °C Note: Avoid locations where the device may be exposed to water (wet, rain, dew condensation, etc.) 3.2. Capacitance Table 4 Symbol Capacitance (TOPR = 25 °C, f = 1 MHz) Parameter Condition Min Max Unit CIN Input VIN = 0 V - 2.5 pF COUT Output VOUT = 0 V - 4 pF Note: This parameter is periodically sampled and is not tested for every device. 3.3. DC Operating Conditions Table 5 DC Operating Condition Symbol Parameter Min Typ. Max Unit 2.7 - 3.6 V VCC Power Supply Voltage VIH High Level Input Voltage VCC × 0.8 - VCC + 0.3 V VIL Low Level Input Voltage −0.3 - VCC × 0.2 V © 2016-2019 KIOXIA Corporation 10 2019-10-01 TC58CVG2S0HRAIG 3.4. Signal Timing The device supports SPI mode 0 and mode 3. Input-----------------data is latched at the rising edge of SCK and data is output at the falling edge of SCK for mode 0 and 3. When HOLD goes Low, the communication is held. The hold state begins at the falling edge of SCK. Mode 0 Mode 3 CPOL CPHA 0 0 SCK 1 1 SCK CS SI MSB LSB SO MSB LSB Figure 5. SPI Timing tSLCH tCHSL tCHSH tCHCL tCLCH tSHCH SCK tSHSL CS tCHDX tDVCH SI SO MSB LSB High-Z : Don’t care Figure 6. Serial Input Timing tCLL tCLH SCK CS SI High-Z tCLQV SO tCLQX High-Z tSHQZ LSB OUT : Don’t care Figure 7. Serial Output Timing © 2016-2019 KIOXIA Corporation 11 2019-10-01 TC58CVG2S0HRAIG tCHHL tHHCH tHLCH SCK tCHHH CS SI tHLQZ tHHQX SO High-Z HOLD Figure 8. Hold Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCK CS Command (1Fh) Address (A0h) SI 7 6 MSB SO 5 4 3 2 Data byte 1 0 7 6 MSB 5 4 3 2 High-Z tWHSL WP 1 17 18 19 20 21 22 23 SCK CS Data byte SI 6 5 SO 4 3 2 1 0 High-Z tSHWL WP 1 Figure 9. WP Timing (Example) © 2016-2019 KIOXIA Corporation 12 2019-10-01 TC58CVG2S0HRAIG 3.5. AC Characteristics Table 6 AC Characteristics (TOPR = −40 to 85 °C, VCC = 2.7 to 3.6 V) Symbol Parameter Min Typ. Max Unit FC Serial Clock Frequency for All Operations - - 104 MHz tCLH Serial Clock High Time 4.5 - - ns tCLL Serial Clock Low Time 4.5 - - ns tCLCH Serial Clock Rise Time (Slew Rate) 0.1 - - V/ns tCHCL Serial Clock Fall Time (Slew Rate) 0.1 - - V/ns 4.6 - - ns 5 - - ns 5 - - ns 5 - - ns 100 - - ns - - 20 ns tSLCH --------- CS Active Setup Time --------- tCHSH tSHCH tCHSL tSHSL CS Active Hold Time --------- CS Not Active Setup Time --------- CS Not Active Hold Time --------- tSHQZ CS High Time Output Disable Time tCLQX Output Hold Time 1 - - ns tDVCH Data In Setup Time 2 - - ns tCHDX Data In Hold Time 5 - - ns 5 - - ns 5 - - ns 5 - - ns 5 - - ns - - 7 ns - - 7 ns tHLCH tHHCH tCHHL tCHHH tHLQZ tHHQX tCLQV tWHSL ---------------- HOLD Low Setup Time (relative to Clock) ---------------- HOLD High Setup Time (relative to Clock) ---------------- HOLD High Hold Time (relative to Clock) ---------------- HOLD Low Hold Time (relative to Clock) ---------------- HOLD Low to High-Z Output ---------------- HOLD High to Output - 20 - 100 - - Clock Low to Output Valid ---------- --------- WP Setup Time Before CS Low ---------- tSHWL - 7.0(CL=10 pF) 7.5(CL=20 pF) 8.0(CL=30 pF) - --------- WP Hold Time After CS High ns ns ns 3.6. DC Operating Characteristics Table 7 DC & Operating Characteristics (TOPR = −40 to 85 °C, VCC = 2.7 to 3.6 V) Symbol Parameter Condition Min Typ. Max Unit IIL Input Leakage Current VIN = 0 V to VCC - - ±10 A ILO Output Leakage Current VOUT = 0 V to VCC - - ±10 A ICCOA1 Read Operation Current (Average) FC = 104 MHz High Speed Mode = Enable Read Buffer Command: 03h or 0Bh (x1) - - 21 mA ICCOA2 Read Operation Current (Average) FC = 104 MHz High Speed Mode = Disable Read Buffer Command: 03h or 0Bh (x1) - - 15 mA ICCOA3 Program Operation Current (Average) FC = 104 MHz - - 18 mA ICCOA4 Erase Operation Current (Average) FC  104 MHz - - 22 mA ICCS Standby Current C S = VCC  0.2 V, WP = VCC, HOLD = VCC - 35 180 A VOH High Level Output Voltage IOH = −0.1 mA VCC  0.2 - - V VOL Low Level Output Voltage IOL = 0.1 mA - - 0.2 V ---------- ---------------- Note: Refer to the High Speed Mode in 4.3. Page Read Operation - High Speed Mode. ICCOA1 to ICCOA4 are the average current during the full operation sequence. Typ. values reflect values obtained in specific test environments under typical test parameters. Actual results will vary based on the conditions and environment in which the part is used. © 2016-2019 KIOXIA Corporation 13 2019-10-01 TC58CVG2S0HRAIG 3.7. Programming, Reading and Erasing Characteristics Table 8 Programming, Reading and Erasing Characteristics (TOPR = −40 to 85 °C, VCC = 2.7 to 3.6 V) Symbol Parameter Min Typ. Max Unit 450 600 s tPROG Programming Time (with ECC) - N Number of Partial Program Cycles in the Same Page - - 4 times tBERASE Block Erasing Time Cell Array to the Buffer (with ECC) (High Speed Mode = Disable) Average Read Time for Sequential Read (with ECC) (High Speed Mode = Enable, Read Buffer x4) Device Reset Time (Read) - 2 7 ms - 115 280 s - 35 - s - - 280 s Device Reset Time (Program) - - 600 s Device Reset Time (Erase) - - 7 ms tR tRHSA4 tRST Note: Refer to the data pair of ECC calculation in 4.16. Internal ECC. Refer to the High Speed Mode in 4.3. Page Read Operation - High Speed Mode. tR is the average busy time for Page Read operation of 64 pages continuously in a block. tRHSA4 is the average busy time for sequential Page Read operation with all data output in each page of 64 pages continuously in a block. The busy time after Protect Execute command is shorter than t PROG (max). Typ. values reflect values obtained in specific test environments under typical test parameters. Actual results will vary based on the conditions and environment in which the part is used. 3.8. Power ON/OFF Sequence The timing sequence shown in the figure below is necessary for the power ON/OFF sequence. The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. The users cannot issue any commands while tVSL. From the end of tVSL to the end of tVOP, Get Feature and Reset operation can be issued. OIP bit in the Feature Table indicates the busy state in this time period. All operations are available after tVOP. VCC 2.7 V 2.7 V tPUW tVSL 0.5 V tVOP 0 V 2.7 V 0.5 V Available operations: All Operations Available operations: Reset, Get Feature Figure 10. Power ON/OFF Timing Table 9 Power on Timing Symbol Parameter --------- Min Max Unit tVSL VCC(min) to CS Low - 100 s tVOP VCC(min) to all operation - 1.1 ms tPUW Waiting time for power on 1 - ms VCCSR VCC Slew Rate - 216 mV/s 3.9. AC Test Condition Table 10 AC Test Condition Parameter Condition VCC: 2.7 to 3.6 V Input level Input pulse rise and fall time VCC × 0.2 to VCC × 0.8 2 ns Input comparison level VCC / 2 Output data comparison level VCC / 2 Output load © 2016-2019 KIOXIA Corporation CL (30 pF) + 1 TTL 14 2019-10-01 TC58CVG2S0HRAIG 4. Command Description and Device Operation 4.1. Command Set Table 11 Command Set Operation Read Cell Array Read Buffer Read Buffer x2 Read Buffer x4 Program Load Byte 1 (CMD) 13h 03h / 0Bh 3Bh 6Bh 02h Byte 2 Byte 3 Byte 4 Dummy + RA16 (Input) Dummy + CA12-CA8 (Input) Dummy + CA12-CA8 (Input) Dummy + CA12-CA8 (Input) Dummy + CA12-CA8 RA15-RA8 RA7-RA0 (Input) (Input) CA7-CA0 Dummy (Input) CA7-CA0 Dummy (Input) CA7-CA0 Dummy (Input) CA7-CA0 Byte 5 Byte N - - D*-D* D*-D* (Output) (Output) D*-D* D*-D* (Output) (Output) D*-D* D*-D* (Output) (Output) D*-D* D*-D* D*-D* (Input) (Input) - - - - (Input) (Input) (Input) RA15-RA8 RA7-RA0 (Input) (Input) RA15-RA8 RA7-RA0 (Input) (Input) CA7-CA0 D*-D* D*-D* D*-D* (Input) (Input) - - FFh / FEh Dummy + RA16 (Input) Dummy + RA16 (Input) Dummy + CA12-CA8 (Input) Dummy + RA16 (Input) - Write Enable 06h Write Disable 04h Program Execute Protect Execute Program Load Random Data Block Erase Reset 10h 2Ah 84h D8h Get Feature 0Fh Set Feature 1Fh Read ID 9Fh (Input) (Input) RA15-RA8 RA7-RA0 (Input) (Input) - - - - - - - - - - - - - - A7-A0 (Input) A7-A0 D7-D0 (Output) D7-D0 D7-D0 (Output) D7-D0 (Output) D7-D0 (Output) (Input) (Input) ID Byte 0 (Output) - - - Reserved Reserved (Output) (Output) Dummy ID Byte 1 (Output) Note: 1) Input of a command other than those specified in Table 11 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. 2) During the operation in progress, do not input any command except 0Fh, FFh and FEh. 3) The users can issue the Protect Execute (2Ah) only one time for each block. 4) Once the Get Feature command is issued, the status and setting information are outputted continuously. © 2016-2019 KIOXIA Corporation 15 2019-10-01 TC58CVG2S0HRAIG 4.2. Page Read Operation The Read Cell Array and Read Buffer commands are required to read the data in a page. The Read Cell Array command reads the page data from the NAND cell array to the data buffer. The Read Buffer command reads the data from the data buffer. The operation sequence is as follows. 1. Read Cell Array (13h) 2. Get Feature (0Fh) 3. Read Buffer (03h or 0Bh) or Read Buffer x2 (3Bh) or Read Buffer x4 (6Bh) : To read the data from the cell array to the internal data buffer : To read the status (OIP, ECCS0 and ECCS1 bits) of the device : To output the data from the internal data buffer The Read Buffer, Read Buffer x2, Read Buffer x4 and Get Feature commands are repeatable commands. For the Read Buffer x2 and Read Buffer x4 read modes are available as shown in Figure 13 and Figure 14. The users are able to check the detailed bit flip count using ECC Bit Flip Count Detection and other functions using Get Feature command. 4.2.1. Read Cell Array (13h) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS Command (13h) SI 6 SO 17-bit row address 7 dummy bits 5 4 3 2 1 0 16 15 14 13 12 11 10 9 8 7 6 High-Z 1 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK CS 17-bit row address SI 8 7 6 5 4 3 Get Feature (0Fh) 2 1 Feature Table address (C0h) 0 7 6 MSB 5 4 3 2 1 0 High-Z SO 1 2 13 14 15 2 1 0 16 17 18 19 20 21 22 23 SCK CS SI Feature Table data out SO 7 6 MSB 5 4 3 2 Feature Table data out 1 0 7 6 MSB 5 4 3 2 1 0 2 : Don’t care Figure 11. Page Read from Cell Array to Buffer © 2016-2019 KIOXIA Corporation 16 2019-10-01 TC58CVG2S0HRAIG 4.2.2. Read Buffer (03h or 0Bh) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS Command (03h or 0Bh) SI 3 dummy bits 2 SO 1 0 13-bit column address 12 11 10 MSB 9 8 7 6 5 1 dummy byte 4 3 2 1 0 High-Z 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 33815 33823 SCK CS 1 dummy byte SI High-Z 0 Data byte 1 SO High-Z 7 6 MSB 5 4 3 Data byte 4224 2 1 0 7 6 MSB 1 5 4 3 2 1 0 : Don’t care Note: When internal ECC is turned OFF, the maximum output data size is 4352 Bytes. Figure 12. Page Read from Buffer Timing © 2016-2019 KIOXIA Corporation 17 2019-10-01 TC58CVG2S0HRAIG 4.2.3. Read Buffer x2 (3Bh) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4 3 21 22 23 24 25 SCK CS Command (3Bh) 2 SO/ SO1 13-bit column address 3 dummy bits SI SO0 1 0 12 11 10 MSB 9 8 7 6 5 1 dummy byte 2 1 0 High-Z 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 16919 16927 SCK CS 1 dummy byte SI switches from input to output SI/ SO0 High-Z 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 SO/ SO1 High-Z 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Data byte 1 Data byte 2 Data byte 4223 Data byte 4224 1 : Don’t care Note: When internal ECC is turned OFF, the maximum output data size is 4352 Bytes. Figure 13. Page Read from Buffer x2 Timing © 2016-2019 KIOXIA Corporation 18 2019-10-01 TC58CVG2S0HRAIG 4.2.4. Read Buffer x4 (6Bh) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS 3 dummy bits Command (6Bh) SI/ SO0 2 SO/ SO1 High-Z WP / SO2 High-Z HOLD / SO3 High-Z 1 0 13-bit column address 12 11 10 MSB 9 8 7 6 5 4 1 dummy byte 3 2 1 0 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK CS 1 dummy byte SI switches from input to output SI/ SO0 High-Z 4 0 4 0 4 0 4 0 4 SO/ SO1 High-Z 5 1 5 1 5 1 5 1 5 WP / SO2 High-Z 6 2 6 2 6 2 6 2 6 HOLD / SO3 High-Z 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Byte 4 1 : Don’t care Figure 14. Page Read from Buffer x4 Timing 4.3. Page Read Operation - High Speed Mode The device has a high speed mode for sequential read operation. When high speed mode is enabled, the average tR is shortened. The command sequence is the same as the Page Read operation. The users set or clear the HSE bit which enables or disables the high speed mode in the feature table as shown in Table 12. High speed mode is enabled (HSE bit is set to 1) in the default condition. When the users switching the HSE bit, the users have to issue the Set Feature command just before the Read Cell Array (13h) command. When the users use the random page read, the recommended setting of the HSE bit is 0 (disable) since tR becomes longer. © 2016-2019 KIOXIA Corporation 19 2019-10-01 TC58CVG2S0HRAIG 4.4. Page Program Operation The Program Load and Program Execute commands are required to program data to a page. The Program Load command transfers data to the buffer. The unit of data transfer is a byte. The Program Execute command programs data from the buffer to the cell array. The operation sequence is as follows. 1. Write Enable (06h) 2. Program Load (02h) 3. Program Execute (10h) 4. Get Feature (0Fh) : To enable the Program Operation : To transfer data to the internal data buffer : To program data from the buffer to the cell array : To read the status (OIP and PRG_F bits) of the device The internal data buffer is cleared by the Program Load command. The Program Load Random Data (84h) command is also available to transfer data to the internal buffer. The users issue Program Load Random Data and the column address before the Program Execute (10h). The operation sequence is as follows. 1. Write Enable (06h) 2. Program Load (02h) 3. Program Load Random Data (84h) 4. Program Execute (10h) 5. Get Feature (0Fh) : To enable the Program operation : To transfer data to the internal data buffer : To transfer data to the internal data buffer : To program data from the buffer to the cell array : To read the status (OIP and PRG_F bits) of the device Program Load Random Data and Get Feature commands are repeatable command. The internal data buffer is not cleared by the Program Load Random Data command. 4.4.1. Program Load (02h) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 7 25 SCK CS Command (02h) 13-bit column address 3 dummy bits SI 2 1 0 12 11 10 MSB 9 8 7 6 5 Data byte 1 4 3 2 1 6 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 33808 33815 SCK CS Data byte 1 SI 7 6 5 4 3 Data byte 2 2 1 0 7 6 5 4 3 Data byte 4224 2 1 0 7 6 5 4 3 2 1 0 1 : Don’t care Note: When internal ECC is turned OFF, the maximum input data size is 4352 Bytes. Figure 15. Program Load © 2016-2019 KIOXIA Corporation 20 2019-10-01 TC58CVG2S0HRAIG 4.4.2. Program Execute (10h) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS 7 dummy bits Command (10h) SI 6 5 4 3 2 17-bit row address 1 0 16 15 14 13 12 11 10 9 8 7 6 High-Z SO 1 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK CS 17-bit row address SI 7 6 5 4 3 2 1 Get Feature (0Fh) Feature Table address (C0h) 0 7 6 MSB 5 4 3 2 1 0 High-Z SO 1 12 2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 0 SCK CS SI 2 1 0 Feature Table data out SO High-Z 7 6 MSB 5 4 3 2 Feature Table data out 1 0 7 6 MSB 5 4 3 2 2 : Don’t care Figure 16. Program Execute Timing © 2016-2019 KIOXIA Corporation 21 2019-10-01 TC58CVG2S0HRAIG 4.4.3. Program Load Random Data (84h) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS Command (84h) 13-bit column address 3 dummy bits SI 2 1 0 12 11 MSB 10 9 8 7 6 5 4 Data byte 1 3 2 1 0 7 6 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 33808 33815 SCK CS Data byte 1 SI 7 6 5 4 3 Data byte 2 2 1 0 7 6 5 4 3 Data byte 4224 2 1 0 7 6 5 4 3 2 1 0 1 Note: When internal ECC is turned OFF, the maximum input data size is 4352 Bytes. Figure 17. Program Load Random Data Timing 4.5. Internal Data Move Operation The Internal Data Move Operation is used to change the data in a page without data output. Before using this operation, the users must disable the Page Read High Speed Mode. The operation sequence is as follows. 1. Set Feature (1Fh) 2. Read Cell Array (13h) 3. Get Feature (0Fh) 4. Write Enable (06h) 5. Program Load Random Data (84h) 6. Program Execute (10h) 7. Get Feature (0Fh) : To disable Page Read High Speed Mode : To read data from the cell array to internal buffer : To read the status (OIP, ECCS0 and ECCS1 bits) of the device : To enable the write : To change the data in the internal buffer : To program data from the buffer to the cell array : To read the status (OIP, PRG_F bits) of the device Program Load Random Data and Get Feature commands are repeatable command. The status of the internal ECC depends on ECC_E bit in the feature table. When internal ECC is disabled, bit flips are not managed by the device. © 2016-2019 KIOXIA Corporation 22 2019-10-01 TC58CVG2S0HRAIG 4.6. Block Erase (D8h) The Block Erase Operation erases the selected block. The page address is ignored automatically. The operation sequence is as follows. 1. Write Enable (06h) 2. Block Erase (D8h) 3. Get Feature (0Fh) : To enable the Erase operation : To erase data in the block : To read the status (OIP and ERS_F bits) of the device Get Feature command is repeatable command. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS Command (D8h) SI 6 SO 17-bit row address 7 dummy bits 5 4 3 2 1 0 16 15 14 13 12 11 10 9 8 7 6 High-Z 1 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK CS 17-bit row address SI 7 6 5 4 3 2 Get Feature (0Fh) 1 Feature Table address (C0h) 0 7 6 MSB 5 4 3 2 1 0 High-Z SO 1 12 2 13 14 15 2 0 16 17 18 19 20 21 22 23 SCK CS SI 1 Feature Table data out SO High-Z 7 6 MSB 5 4 3 2 1 Feature Table data out 0 7 6 MSB 5 4 3 2 1 0 2 : Don’t care Figure 18. Block Erase Timing © 2016-2019 KIOXIA Corporation 23 2019-10-01 TC58CVG2S0HRAIG 4.7. Reset (FFh or FEh) The device offers Reset operation by command FFh or FEh. For example, in case of a Program or Erase operation, the internally generated voltage is discharged and the device enters the busy state. The operation sequence is as follows. 1. Reset (FFh or FEh) 2. Get Feature (0Fh) : To reset the device : To read the status of the device Get Feature command is repeatable command. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK CS Command (FFh or FEh) Get Feature (0Fh) Feature Table address (C0h) SI 7 6 MSB SO 5 4 3 2 1 0 High-Z 1 13 14 15 16 17 18 19 20 21 22 23 SCK CS SI 2 1 0 Feature Table data out SO 7 6 MSB 5 4 3 2 1 Feature Table data out 0 7 6 MSB 5 4 3 2 1 0 1 : Don’t care Figure 19. Reset Timing © 2016-2019 KIOXIA Corporation 24 2019-10-01 TC58CVG2S0HRAIG 4.8. Write Enable (06h) / Write Disable (04h) The Write Enable/Disable commands set or reset the WEL (Write Enable Latch) bit in the feature table shown in Table 12. The Write Enable command sets the WEL bit to 1. The Write Enable command must be issued before the Page Program, Block Protection and Block Erase operations. The Write Disable command clears the WEL bit to 0. If the WEL bit is cleared, Page Program, Block Protection and Block Erase commands are ignored by the device. 0 1 2 3 4 5 6 7 SCK CS Command (06h) SI Figure 20. Write Enable Timing 0 1 2 3 4 5 6 7 SCK CS Command (04h) SI Figure 21. Write Disable Timing © 2016-2019 KIOXIA Corporation 25 2019-10-01 TC58CVG2S0HRAIG 4.9. Set Feature (1Fh) / Get Feature (0Fh) The users set individual features using the Set Feature operation and get feature settings or status of the device using the Get Feature operation. Feature settings and status are shown in Table 12. Refer to other sections for the details of each setting and status. When a feature is set once by the Set Feature command, the device keeps the bit until power OFF even if a Reset (FFh or FEh) command is issued. Table 12 Feature Table Address Bit 6 5 4 3 2 1 0 A0h BRWD (R/W) 7 Reserved BL2 (R/W) BL1 (R/W) BL0 (R/W) Reserved Reserved Reserved B0h PRT_E (R/W) IDR_E (R/W) Reserved ECC_E (R/W) Reserved BBI (R) HSE (R/W) Reserved C0h Reserved Reserved ECCS1 (R) ECCS0 (R) PRG_F (R) ERS_F (R) WEL (R/W) OIP (R) 10h BFD3 (R/W) BFD2 (R/W) BFD1 (R/W) BFD0 (R/W) Reserved Reserved Reserved Reserved 20h BFS7 (R) BFS6 (R) BFS5 (R) BFS4 (R) BFS3 (R) BFS2 (R) BFS1 (R) BFS0 (R) 30h MBF3 (R) MBF2 (R) MBF1 (R) MBF0 (R) Reserved MFS2 (R) MFS1 (R) MFS0 (R) 40h BFR7 (R) BFR6 (R) BFR5 (R) BFR4 (R) BFR3 (R) BFR2 (R) BFR1 (R) BFR0 (R) 50h BFR15 (R) BFR14 (R) BFR13 (R) BFR12 (R) BFR11 (R) BFR10 (R) BFR9 (R) BFR8 (R) 60h BFR23 (R) BFR22 (R) BFR21 (R) BFR20 (R) BFR19 (R) BFR18 (R) BFR17 (R) BFR16 (R) 70h BFR31 (R) BFR30 (R) BFR29 (R) BFR28 (R) BFR27 (R) BFR26 (R) BFR25 (R) BFR24 (R) Note: (R/W): Read / Write, (R): Read only The users must use the Write Enable (06h) or the Write Disable (04h) command to switch the WEL bit since Set Feature command cannot change it. The value of Reserved bits in Feature Table is 0. The access to any unknown address which is not defined in this Feature Table is not allowed. The bits in Feature Table which are related to ECC functions become valid when the Internal ECC is turned on by the setting of ECC_E bit (bit [4]) in address B0h. All the bits in Feature Table will be back to the default value after the power on sequence. © 2016-2019 KIOXIA Corporation 26 2019-10-01 TC58CVG2S0HRAIG Table 13 Feature Table - A0h Address Description Bit Symbol Parameter Read / Write Description R/W When W P pin is Low and BRWD is set to 1, over write for BRWD and BL bits are prohibit. 1b: Disable 0b: Enable (Default) ------------ Block Register Write Disable 7 BRWD 6 Reserved 5 BL2 Block Lock 2 R/W 4 BL1 Block Lock 1 R/W 3 BL0 Block Lock 0 R/W 2 Reserved - - The users set the locked blocks as entire of device or portion of device using the BL bits. 000b: All Unlocked 001b: Upper 1/64 Locked 010b: Upper 1/32 Locked 011b: Upper 1/16 Locked 100b: Upper 1/8 Locked 101b: Upper 1/4 Locked 110b: Upper 1/2 Locked 111b: All Locked (Default) Reserved 1 Reserved - - Reserved 0 Reserved - - Reserved - - Reserved Note: (R/W): Read / Write, (R): Read only Refer to the description of BRWD and BL2-0 in 4.10 Block Lock Operation. Table 14 Feature Table - B0h Address Description Bit Symbol Parameter Read / Write Description 7 PRT_E Block Protect Enable R/W The setting for Block Protection. 0b: Normal Operation (Default) 1b: Block Protection Enable – The Protect Execute command (2Ah) is acceptable for Block Protection. 6 IDR _E ID Read Enable R/W The setting for Parameter Page Read and Unique ID Read. 0b: Normal Operation (Default) 1b: Parameter Page Read and Unique ID read mode 5 Reserved 4 ECC _E 3 Reserved 2 BBI Bad Block Inhibit 1 HSE High Speed Mode Enable R/W 0 Reserved - - ECC Enable R/W - Reserved The setting for internal ECC Function. 0b: Internal ECC Disable 1b: Internal ECC Enable (Default) - Reserved R The setting for Bad Block Inhibit Function. 0b: Not Available 1b: Bad Block Inhibit Enable (Default) The setting for Page Read High Speed Mode. 0b: High Speed Mode Disable 1b: High Speed Mode Enable (Default) Reserved Note: (R/W): Read / Write, (R): Read only Refer to the description of PRT_E in 4.11. Block Protection Operation (One Time Program). Refer to the description of ECC_E in 4.16.1. ECC Switch. Refer to the description of BBI in 4.15. Bad Block Inhibit. Refer to the description of HSE in 4.3. Page Read Operation - High Speed Mode. © 2016-2019 KIOXIA Corporation 27 2019-10-01 TC58CVG2S0HRAIG Table 15 Feature Table - C0h Address Description Bit Symbol Parameter Read / Write 7 Reserved - - Reserved 6 Reserved - - 5 ECCS1 ECC Status 1 R 4 ECCS0 ECC Status 0 R Reserved ECC status bits indicate the status of internal ECC operation. 00b: No bit flips were detected in previous page read. 01b: Bit flips were detected and corrected. Bit flip count was less than the threshold bit count. The threshold bit count is set by bits [7:4] in address 10h in the feature table. 10b: Multiple bit flips were detected and not corrected. 11b: Bit flips were detected and corrected. Bit flip count was equal to or more than the threshold bit count. The threshold bit count is set by bits [7:4] in address 10h in the feature table. Description 3 PRG_F Program Fail R Program fail bit indicates that a program failure has occurred in the previous Program or Block Protection operation. 0b: Program Pass 1b: Program Fail 2 ERS_F Erase Fail R Erase fail bit indicates that an erase failure has occurred in the previous Erase operation. 0b: Erase Pass 1b: Erase Fail 1 WEL Write Enable Latch 0 OIP Operation In Progress R/W R This bit indicates the status of write enable/disable. 0b: Write Disable (Default) 1b: Write Enable This bit indicates the status of the device. This bit will be set while busy state. 0b: Operation is not in progress. Ready state. 1b: Operation is in progress. Busy state. Note: (R/W): Read / Write, (R): Read only The users must use the Write Enable (06h) or the Write Disable (04h) command to switch the WEL bit since Set Feature command cannot change it. Once the Get Feature command is issued, the status and setting information are outputted continuously. OIP, PRG_F, ERS_F bits are updated automatically during the status information are outputted continuously. © 2016-2019 KIOXIA Corporation 28 2019-10-01 TC58CVG2S0HRAIG 4.9.1. Set Feature (1Fh) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK CS Command (1Fh) Feature Table address SI 7 6 MSB 5 4 3 2 Data byte 1 0 6 7 MSB 5 4 3 2 1 0 Figure 22. Set Feature Timing 4.9.2. Get Feature (0Fh) After the Get Feature command and the address are input, the 8bit status and setting information will be output continuously until CS goes High. ---------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SCK CS Command (0Fh) Feature Table address SI 7 6 MSB 5 4 3 2 1 0 7 6 MSB High-Z SO 5 1 14 15 1 0 16 17 18 19 20 21 22 23 SCK CS SI Feature Table data out SO 7 6 MSB 5 4 3 2 1 Feature Table data out 0 7 6 MSB 5 4 3 2 1 1 0 : Don’t care Figure 23. Get Feature Timing © 2016-2019 KIOXIA Corporation 29 2019-10-01 TC58CVG2S0HRAIG 4.10. Block Lock Operation The Block Lock Operation prevents Page Program, Block Protection and Block Erase operations. The users set the range of locked blocks as the entire device or a portion of the device using the BL bits (bits [5:3]) in address A0h of the feature table shown in Table 12. The users set the BL bits by the Set Feature operation. After the power on sequence, all blocks are locked (bits [5:3] are all set to 1). If the Program Execute (10h), Protect Execute (2Ah) or Block Erase (D8h) command is issued to locked blocks, Program Fail or Erase Fail will be indicated in the feature table shown in Table 12. The users must clear / change the BL bits using Set Feature command to unlock the entire of the device or portion of the device. When BRWD bit is set and WP pin is Low, the users cannot switch the BRWD and the BL bits. The Block Lock Operation is different from the Block Protection Operation. ------------- Table 16 Block Lock Setting BL2 BL1 BL0 0 0 0 All Unlocked Protected Area None Protected Blocks 0 0 1 Upper 1/64 Locked Block 2016 to 2047 0 1 0 Upper 1/32 Locked Block 1984 to 2047 0 1 1 Upper 1/16 Locked Block 1920 to 2047 1 0 0 Upper 1/8 Locked Block 1792 to 2047 1 0 1 Upper 1/4 Locked Block 1536 to 2047 1 1 0 Upper 1/2 Locked Block 1024 to 2047 1 1 1 All Locked Block0 to 2047 4.11. Block Protection Operation (One Time Program) The Block Protection Operation provides the function to prohibit the Program and Erase operations to user selected blocks. The users protect individual blocks using the Set Feature, Write Enable and Protect Execute commands. The last 128 blocks of the device are able to be set to protected blocks. The block protection setting is permanent. Once a block is protected, the users cannot unprotect the block. When PRT_E (bit [7]) in address B0h of the feature table is set to 1, and the users issue the Protect Execute command (2Ah), the user block will become a protected block. The users must set the PRT_E bit (bit [7]) just before the Write Enable command for the Protect Execute. After the protection to the block, the users must clear bit [7] in address B0h using the Set Feature command. The users can issue the Protect Execute (2Ah) only one time for each block. The Block Protection Operation is different from the Block Lock Operation. The operation sequence to set block “N” as a protected block is as follows. 1. Set Feature (1Fh) 2. Write Enable (06h) 3. Protect Execute (2Ah) for block “N” 4. Get Feature (0Fh) 5. Set Feature (1Fh) : To set PRT_E bit [7] in address B0h to block protection mode : To enable the Protect Execute command : To protect the block “N” : To read the status (OIP and PRG_F bits) of the device : To clear PRT_E bit [7] in address B0h Get Feature command is repeatable command. Table 17 Block Protection Setting PRT_E State 0 Normal Operation (Default) 1 Block Protection Enable – The Protect Execute command (2Ah) is acceptable for Block Protection. Table 18 Block Number for Block Protection Block Number Block Protection Block 0 – Block 1919 The users cannot protect these blocks by Block Protection operation. Block 1920 – Block 2047 The users can protect these blocks by Block Protection operation. © 2016-2019 KIOXIA Corporation 30 2019-10-01 TC58CVG2S0HRAIG 4.11.1. Protect Execute (2Ah) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS 7 dummy bits Command (2Ah) SI 6 5 4 3 17-bit row address 2 1 0 16 15 14 13 12 11 10 9 8 7 6 High-Z SO 1 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK CS 17-bit row address SI 7 6 5 4 3 2 Get Feature (0Fh) 1 Feature Table address (C0h) 0 7 6 MSB 5 4 3 2 1 0 High-Z SO 1 12 2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK CS SI 2 1 0 Feature Table data out SO High-Z 7 6 MSB 5 4 3 2 Feature Table data out 1 0 7 6 MSB 5 4 3 2 1 0 2 : Don’t care Figure 24. Protect Execute Timing © 2016-2019 KIOXIA Corporation 31 2019-10-01 TC58CVG2S0HRAIG 4.12. Parameter Page Read Operation The device has a parameter page. The operation sequence is as follows. 1. Set Feature (1Fh) with address B0h and set bit [6] : To set the IDR_E bit in the feature table 2. Read Cell Array (13h) with address 01h : To read the parameter page 3. Get Feature (0Fh) : To read the status (OIP bit) of the device 4. Read Buffer (03h or 0Bh) with address 00h : To output the parameter page or Read Buffer x2 (3Bh) or Read Buffer x4 (6Bh) 5. Set Feature (1Fh) with address B0h and clear bit [6] : To clear the IDR_E bit in the feature table Read Buffer, Read Buffer x2, Read Buffer x4 and Get Feature commands are repeatable commands. Table 19 Parameter Page Byte Parameter Value 0-3 4 - 31 Signature Reserved 32 - 43 Device manufacturer 44 - 63 Device model; TC58CVG2S0HRAIG 64 65 - 79 80 - 83 84 - 85 86 - 89 90 - 91 92 - 95 96 - 99 100 101 102 103 - 104 105 - 106 107 108 - 109 110 111 112 113 - 127 128 129 - 132 Manufacturer ID Reserved Number of data bytes per page Number of spare bytes per page Number of data bytes per partial page Number of spare bytes per partial page Number of pages per block Number of blocks per unit Number of logical units Reserved Number of bits per cell Bad blocks maximum per unit Block endurance Guaranteed valid blocks at beginning of target Reserved Number of programs per page Reserved Number of ECC bits Reserved I/O pin capacitance Reserved 4Eh, 41h, 4Eh, 44h All 00h 54h, 4Fh, 53h, 48h, 49h, 42h, 41h, 20h, 20h, 20h, 20h, 20h 54h, 43h, 35h, 38h, 43h, 56h, 47h, 32h, 53h, 30h, 48h, 52h, 41h, 49h, 47h, 20h, 20h, 20h, 20h, 20h 98h All 00h 00h, 10h, 00h, 00h 80h, 00h 00h, 02h, 00h, 00h 10h, 00h 40h, 00h, 00h, 00h 00h, 08h, 00h, 00h 01h 00h 01h 28h, 00h 01h, 05h 01h All 00h 04h 00h 00h All 00h 04h All 00h 133 - 134 tPROG maximum page program time 58h, 02h 135 - 136 tBERASE maximum block erase time 58h, 1Bh 137 - 138 tR maximum page read time Reserved Integrity CRC Value of bytes 0–255 Value of bytes 0–255 18h, 01h 139 - 253 254 - 255 256 - 511 512 - 767 All 00h F5h, E1h - Note: The value of all parameters are default setting of the device. When the users change the setting of the device such as internal ECC enable/disable, parameter page is not updated. The Integrity CRC (Cyclic Redundancy Check) field is used to verify that the contents of the Parameter Page were transferred correctly to the host. The CRC of the Parameter Page is a word (16-bit) field. The CRC calculation covers all of data between byte 0 and byte 253 of the Parameter Page inclusive. The CRC shall be calculated on byte (8-bit) quantities starting with byte 0 in the Parameter Page. The bits in the 8-bit quantity are processed from the most significant bit (bit 7) to the least significant bit (bit 0). The CRC shall be calculated using the following 16-bit generator polynomial: G(X) = X16 + X15 + X2 + 1 This polynomial in hex may be represented as 8005h. The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the final CRC value after it is calculated. There is no reversal of the data bytes or the CRC calculated value. © 2016-2019 KIOXIA Corporation 32 2019-10-01 TC58CVG2S0HRAIG 4.13. Read ID (9Fh) The ID of the device is read by command 9Fh. Table 20 ID Table Byte Description Value Byte 0 Manufacture ID (KIOXIA) 98h Byte 1 Device ID CDh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCK CS Command (9Fh) 8 dummy bits SI 7 6 5 4 3 2 1 0 Manufacturer ID High-Z SO 23 24 25 26 Device ID 7 6 MSB 27 28 29 30 31 1 SCK CS SI Device ID SO 7 6 MSB 5 4 3 2 1 1 0 : Don’t care Figure 25. Read ID Timing 4.14. Unique ID Read Operation The device has a unique ID and it is different for each device. The device has 16 copies of 32 bytes of unique ID data. The first 16 bytes of data are unique ID data and the second 16 bytes of data are the complement value of the first 16 bytes of data. The operation sequence is as follows. 1. Set Feature (1Fh) with address B0h and set bit [6] 2. Read Cell Array (13h) with address 00h 3. Get Feature (0Fh) 4. Read Buffer (03h or 0Bh) with address 00h or Read Buffer x2 (3Bh) or Read Buffer x4 (6Bh) 5. Set Feature (1Fh) with address B0h and clear bit [6] : To set the IDR_E bit in the feature table : To read the unique ID : To read the status (OIP bit) of the device : To output the 16 copies of the Unique ID : To clear the IDR_E bit in the feature table Read Buffer, Read Buffer x2, Read Buffer x4 and Get Feature commands are repeatable commands. 4.15. Bad Block Inhibit The device occasionally contains unusable blocks in its initial condition. The Page Program, Block Protection and Erase operation are prohibited to invalid blocks. The device has a bad block inhibit function to protect initial invalid blocks. When the users issue the Program or Erase command to the initial invalid blocks, the device ignores these commands automatically and Program Fail or Erase Fail is indicated in the feature table as shown in Table 12. The bad block inhibit function is enabled by default and this setting is permanent. © 2016-2019 KIOXIA Corporation 33 2019-10-01 TC58CVG2S0HRAIG 4.16. Internal ECC The device has internal ECC and it generates error correction code during the busy time in a Program operation. The ECC logic manages 9 bit error detection and 8 bit error correction in each 528 bytes of main and spare data. A section of the main area (512 bytes) and spare area (16 bytes) are paired for ECC calculation. During the Read operation, the device executes ECC by itself. Once the Read command is executed, the Get Feature command can be issued to check the read status. The read status remains until other valid commands are executed. The device has the functions of Bit Flip Detection and Maximum Bit Flip Count Report. Internal ECC detects the bit flips in each sector and the maximum bit flip count in a page. These results are indicated in the feature table as shown in Table 12. Table 21 Page Assignment 1st Main 2nd Main 3rd Main 4th Main 5th Main 6th Main 7th Main 8th Main 1st 2nd 3rd 4th 5th 6th 7th 8th Spare Spare Spare Spare Spare Spare Spare Spare 512B 512B 512B 512B 512B 512B 512B 512B 16B 16B 16B 16B 16B 16B 16B 16B Internal ECC Parity Area 128B Table 22 Definition of 528 bytes Data Pair Column Address Main Area Spare Area 0 to 511 4096 to 4111 512 to 1023 4112 to 4127 1024 to 1535 4128 to 4143 1536 to 2047 4144 to 4159 2048 to 2559 4160 to 4175 2560 to 3071 4176 to 4191 3072 to 3583 4192 to 4207 3584 to 4095 4208 to 4223 Data Pair 1st Data Pair (Sector 0) 2nd Data Pair (Sector 1) 3rd Data Pair (Sector 2) 4th Data Pair (Sector 3) 5th Data Pair (Sector 4) 6th Data Pair (Sector 5) 7th Data Pair (Sector 6) 8th Data Pair (Sector 7) Note: The ECC parity code generated by internal ECC is stored in column addresses 4224-4351 and the users cannot access to these specific addresses when internal ECC is enabled. While using the Partial Page Program, the users must program the data to main and spare area simultaneously by the definition of data pair. 4.16.1. ECC Switch The internal ECC is enabled after the power on sequence. The users set or clear the ECC_E bit (bit [4]) in address B0h of the feature table to enable or disable the internal ECC by the Set Feature command. If the ECC_E bit is cleared to 0 in the feature table, internal ECC will be disabled. In this case, the spare area size is changed from 128 bytes to 256 bytes automatically. When the users switching the ECC_E bit, the users must issue the Set Feature command just before the Page Read, Page Program or Block Erase operation. 4.16.2. ECC Status The ECC Status function is used to monitor the error correction status. The device can correct up to 8 bit errors. ECC is performed on the NAND Flash main and spare areas. The ECC status is indicated in the ECCS1 and ECCS0 bit (bits [5:4]) in address C0h of the feature table shown in Table 15. The users issue the Get Feature command to read the ECC status. 4.16.3. ECC Bit Flip Count Detection The ECC Bit Flip Count Detection function detects the bit flip count in a page. The users set the threshold bit count using the Set Feature command. The threshold bit count is decided by the BFD bits in address 10h in the feature table as shown in Table 12. The detected results will be indicated in the BFS bits (bits [7:0]) in address 20h. When bit flips exceed the threshold in a sector, the BFS bits are set after the Read Buffer command. Table 23 Bit Flip Count Detection Setting (BFD) BFD3 0 0 0 0 0 0 0 0 1 1 BFD2 0 0 0 0 1 1 1 1 0 1 BFD1 0 0 1 1 0 0 1 1 0 1 BFD0 0 1 0 1 0 1 0 1 0 1 © 2016-2019 KIOXIA Corporation Description Reserved Detect 1 bit flip in a sector Detect 2 bit flips in a sector Detect 3 bit flips in a sector Detect 4 bit flips in a sector (Default) Detect 5 bit flips in a sector Detect 6 bit flips in a sector Detect 7 bit flips in a sector Detect 8 bit flips in a sector Detect the uncorrectable error (9+ bit errors in a sector) 34 2019-10-01 TC58CVG2S0HRAIG Table 24 Bit Flip Count Detection Status (BFS) (Feature Table - 20h Address Description) Bit Symbol 7 Parameter BFS7 6 Bit Flip Count Detection Status 7 BFS6 5 Bit Flip Count Detection Status 6 BFS5 4 Bit Flip Count Detection Status 5 BFS4 3 Bit Flip Count Detection Status 4 BFS3 2 Bit Flip Count Detection Status 3 BFS2 1 Bit Flip Count Detection Status 2 BFS1 0 Bit Flip Count Detection Status 1 BFS0 Bit Flip Count Detection Status 0 Read / Write Description R Bit flip count detection status 7 indicates that the bit flip count in sector 7 is more than threshold bit count. 0b: Bit flip count in sector 7 is less than the threshold. 1b: Bit flip count in sector 7 is equal to or more than the threshold bit count. R Bit flip count detection status 6 indicates that the bit flip count in sector 6 is more than threshold bit count. 0b: Bit flip count in sector 6 is less than the threshold. 1b: Bit flip count in sector 6 is equal to or more than the threshold bit count. R Bit flip count detection status 5 indicates that the bit flip count in sector 5 is more than threshold bit count. 0b: Bit flip count in sector 5 is less than the threshold. 1b: Bit flip count in sector 5 is equal to or more than the threshold bit count. R Bit flip count detection status 4 indicates that the bit flip count in sector 4 is more than threshold bit count. 0b: Bit flip count in sector 4 is less than the threshold. 1b: Bit flip count in sector 4 is equal to or more than the threshold bit count. R Bit flip count detection status 3 indicates that the bit flip count in sector 3 is more than threshold bit count. 0b: Bit flip count in sector 3 is less than the threshold. 1b: Bit flip count in sector 3 is equal to or more than the threshold bit count. R Bit flip count detection status 2 indicates that the bit flip count in sector 2 is more than threshold bit count. 0b: Bit flip count in sector 2 is less than the threshold. 1b: Bit flip count in sector 2 is equal to or more than the threshold bit count. R Bit flip count detection status 1 indicates that the bit flip count in sector 1 is more than threshold bit count. 0b: Bit flip count in sector 1 is less than the threshold. 1b: Bit flip count in sector 1 is equal to or more than the threshold bit count. R Bit flip count detection status 0 indicates that the bit flip count in sector 0 is more than threshold bit count. 0b: Bit flip count in sector 0 is less than the threshold. 1b: Bit flip count in sector 0 is equal to or more than the threshold bit count. 4.16.4. ECC Bit Flip Count Report The ECC Bit Flip Count Report function reports the bit flip count of each sector in a page. The users can read the bit flip count using the Get Feature command with address 40h and 50h. Table 25 Bit Flip Count Report for Sector 0 (BFR) BFR3 BFR2 BFR1 BFR0 0 0 0 0 No bit flip occurred in sector 0 0 0 0 1 1 bit flip occurred in sector 0 and corrected 0 0 1 0 2 bit flips occurred in sector 0 and corrected 0 0 1 1 3 bit flips occurred in sector 0 and corrected 0 1 0 0 4 bit flips occurred in sector 0 and corrected 0 1 0 1 5 bit flips occurred in sector 0 and corrected 0 1 1 0 6 bit flips occurred in sector 0 and corrected 0 1 1 1 7 bit flips occurred in sector 0 and corrected 1 0 0 0 8 bit flips occurred in sector 0 and corrected 1 1 1 1 Bit flips over 8 bits occurred in sector 0 and were not corrected © 2016-2019 KIOXIA Corporation Description 35 2019-10-01 TC58CVG2S0HRAIG Table 26 Sector Definition (BFR) BFR7 BFR6 BFR5 BFR4 BFR3 BFR2 Sector 1 BFR15 BFR14 BFR13 BFR22 BFR12 BFR11 BFR8 BFR17 BFR16 Sector 2 BFR21 BFR30 BFR9 BFR10 BFR20 BFR19 BFR18 Sector 5 BFR31 BFR0 Sector 0 Sector 3 BFR23 BFR1 Sector 4 BFR29 BFR28 BFR27 BFR26 Sector 7 BFR25 BFR24 Sector 6 4.16.5. ECC Maximum Bit Flip Count Report The ECC Maximum Bit Flip Count Report function provides the maximum bit flip count in a page. The maximum count is indicated in address 30h of the feature table shown in Table 12. The sector number in which the maximum bit flip occurred in a page is indicated in the MFS bit (bits [2:0]) in address 30h as shown in Table 28. When several sector’s maximum bit flip count are the same, the lowest sector number is indicated in these bits. The users get the report using the Get Feature command. Table 27 Maximum Bit Flip Count (MBF) MBF3 MBF2 MBF1 MBF0 Description 0 0 0 0 No bit error is detected in the page. 0 0 0 1 Maximum bit flip count is 1 bit in a sector. Bit flip was corrected. 0 0 1 0 Maximum bit flip count is 2 bits in a sector. Bit flips were corrected. 0 0 1 1 Maximum bit flip count is 3 bits in a sector. Bit flips were corrected. 0 1 0 0 Maximum bit flip count is 4 bits in a sector. Bit flips were corrected. 0 1 0 1 Maximum bit flip count is 5 bits in a sector. Bit flips were corrected. 0 1 1 0 Maximum bit flip count is 6 bits in a sector. Bit flips were corrected. 0 1 1 1 Maximum bit flip count is 7 bits in a sector. Bit flips were corrected. 1 0 0 0 Maximum bit flip count is 8 bits in a sector. Bit flips were corrected. 1 1 1 1 Maximum bit flip count exceed 8 bits in a sector. Bit flips were not corrected. Table 28 Maximum Bit Flip Count Sector (MFS) MFS2 MFS1 MFS0 Description 0 0 0 Maximum bit flips occurred in sector 0 0 0 1 Maximum bit flips occurred in sector 1 0 1 0 Maximum bit flips occurred in sector 2 0 1 1 Maximum bit flips occurred in sector 3 1 0 0 Maximum bit flips occurred in sector 4 1 0 1 Maximum bit flips occurred in sector 5 1 1 0 Maximum bit flips occurred in sector 6 1 1 1 Maximum bit flips occurred in sector 7 © 2016-2019 KIOXIA Corporation 36 2019-10-01 TC58CVG2S0HRAIG 5. Package Information 5.1. WSON8 (P-WSON8-0608-1.27-003) The WSON8 features an exposed PAD (ePAD). The ePAD is configured on the package bottom without any connection to the chip inside. It is recommended for users to solder the ePAD onto PC board with connection to VSS or None, as the adhesive strength to the PC board will be enhanced. ePAD Weight: 0.12 g (typ.) © 2016-2019 KIOXIA Corporation 37 2019-10-01 TC58CVG2S0HRAIG 6. Application Notes 6.1. Prohibition of Unspecified Commands The operation commands are listed in Table 11. Input of a command other than those specified in Table 11 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. 6.2. Restriction of Commands while in the Busy State During the operation in progress, do not input any command except Get Feature (0Fh) and Reset (FFh or FEh). 6.3. Addressing for Page Program Operation Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page of the block to MSB (Most Significant Bit) page of the block. Random page address programming is prohibited. From the LSB page to MSB page DATA IN: Data (1) e.g.) Random page program (Prohibition) Data (64) DATA IN: Data (1) Data Buffer Data (64) Data Buffer Page 0 Page 1 Page 2 (1) (2) (3) Page 0 Page 1 Page 2 (2) (32) (3) Page 31 (32) Page 31 (1) Page 63 (64) Page 63 (64) 6.4. Several Programming Cycles on the Same Page (Partial Page Program) Internal ECC ON: Partial Page Program should follow the Table 22 restriction while ECC_E bit is set to 1. ECC Parity Code is generated during Program operation on Main area (512 byte) + Spare area (16 byte), and this parity code is written to the Parity area as shown in Table 21. While using the Partial Page Program, the user must program the data to main and spare area simultaneously by the definition of sector in section “Internal ECC”. For example, each segment can be programmed individually as follows: Program Load Random Data (84h) command can be used to skip column address within the selected page to improve the data input operation. © 2016-2019 KIOXIA Corporation 38 2019-10-01 TC58CVG2S0HRAIG Internal ECC OFF: Each segment can be programmed individually as follows while ECC_E bit is set to 0. 1st programming Data Pattern 1 2nd programming All 1 s All 1 s Data Pattern 2 All 1 s 4th programming Result All 1 s Data Pattern 1 Data Pattern 2 Data Pattern 4 Data Pattern 4 Program Load Random Data (84h) command can be used to skip column address within the selected page to improve the data input operation. 6.5. Power Off Timing Please do not turn off the power before Page Program, Block Protection and Erase operation is completed. Avoid using the device when the battery is low. Power shortage and/or power failure before Write/Erase operation is completed will cause loss of data and/or damage to data. 6.6. Invalid Blocks (Bad Blocks) The device occasionally contains unusable blocks. Therefore, the following issues must be recognized: The Page Program, Block Protection and Erase operation are prohibited to the invalid blocks. When the users issue the Program or Erase command to the initial invalid blocks, the device ignores these commands automatically and Program Fail or Erase Fail is indicated in the feature table as shown in Table 12. Check if the device has any bad blocks after installation into the system. Refer to the test flow for initial bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the bit lines by select gates. The number of valid blocks over the device lifetime is as Table 2. Regarding invalid blocks, the bad block mark is in the whole pages. Please read one column of any page in each block. If the data of the column is 00 (Hex), define the block as a bad block. Start Block No = 1 Read Check Block No. = Block No.  1 No Fail Pass Bad Block *1 Last Block Yes When internal ECC is turned ON: For Bad Block Test Flow, during Read Check, irrespective of Read Status result (ECC Pass or Fail), use the read data value to make judgment for Bad Block. End *1: No erase operation is allowed to detected bad blocks. © 2016-2019 KIOXIA Corporation 39 2019-10-01 TC58CVG2S0HRAIG 6.7. Failure Phenomena The device may fail during a Program, Erase or Read operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Erase Failure Status Read after Erase  Block Replacement Block Protection Failure Status Read after Block Protection  Block Replacement Page Programming Failure Status Read after Program  Block Replacement Read Bit Error Check the ECC correction status by Get Feature command and take appropriate measures such as rewrite in consideration of Wear Leveling before uncorrectable ECC error occurs. Block  Block Protection Failure is checked by PRG_F bit in Feature Table using Get Feature command after Protect Execute. Block Replacement Program Error occurs Buffer memory Block A When an error happens in Block A, reprogramming the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using another appropriate scheme). Block B Erase When an error occurs during an Erase operation, prevent further accesses to this bad block (by creating a table within the system or by using another appropriate scheme). © 2016-2019 KIOXIA Corporation 40 2019-10-01 TC58CVG2S0HRAIG 6.8. Reliability Guidance This reliability guidance is intended to provide some guidance related to using NAND Flash with 8 bit ECC for each 512 bytes. NAND Flash memory cells are gradually worn out and the reliability level of memory cells is degraded by repeating Write and Erase operation of ‘0’ data in each block. For detailed reliability data, please refer to the reliability note for each product. Although random bit errors may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be marked as bad when a program status failure or erase status failure is detected. The reliability of NAND Flash memory cells during the actual usage on system level depends on the usage and environmental conditions. KIOXIA adopts the checker pattern data, 0x55 & 0xAA for alternative Write/Erase cycles, for the reliability test. Write/Erase Endurance Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a Status Read after either an Auto Page Program or Auto Block Erase operation. The cumulative bad block count will increase along with the number of Write/Erase cycles. Data Retention The data in NAND Flash memory may change after a certain amount of storage time. This is due to charge loss or charge gain. After block erasure and reprogramming, the block may become usable again. Data Retention time is generally influenced by the number of Write/Erase cycles and temperature. Data Retention [Years] Here is a graph plotting the relationship between Write/Erase Endurance and Data Retention. Write/Erase Endurance [Cycles] Read Disturb A Read operation may disturb the data in NAND Flash memory. The data may change due to charge gain. Usually, bit errors occur on other pages in the block, not the page being read. After a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure and reprogramming, the block may become usable again. Read Disturb capability is generally influenced by the number of Write/Erase cycles. © 2016-2019 KIOXIA Corporation 41 2019-10-01 TC58CVG2S0HRAIG 6.9 NAND Management NAND Management such as Bad Block Management, ECC treatment and Wear Leveling, but not limited to these treatments, should be recognized and incorporated in the system design. ECC treatment for read data is mandatory against random bit errors, and host should monitor ECC status to take appropriate measures such as rewrite in consideration of Wear Leveling before uncorrectable Error occurs. To realize robust system design, generally it is necessary to prevent the concentration of Write/Erase cycles at the specific blocks by adopting Wear Leveling which manages to distribute Write/Erase cycles evenly among NAND Flash memory. And also it is necessary to avoid dummy ‘0’ data write, e.g. ‘0’ data padding, which accelerate block endurance degradation. Continuous Write and Erase cycling with high percentage of '0' bits in data pattern can lead to faster block endurance degradation. Example: NAND cell array with ‘0’ data padding 0 : “0” data cell 1 : “1” data cell 0 0 1 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 User data area 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 User data area Remaining area 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Remaining area (b) “1” data for Remaining area (Recommended) (a) Accelerate block endurance degradation by fixed dummy “0” data write © 2016-2019 KIOXIA Corporation 1 1 0 1 0 0 1 0 42 2019-10-01 TC58CVG2S0HRAIG 7. Revision History Date 2016-06-22 2016-11-08 Rev. 1.0 1.1 2018-02-06 1.2 2018-10-01 1.3 2019-10-01 2.0 © 2016-2019 KIOXIA Corporation Description Initial Release Merged the datasheet of SOP16 and WSON 8 together Added package code in 1.3. Features. Updated the specification and description in 3.7. Programming, Reading and Erasing Characteristics. Updated the description in 4.2. Page Read Operation, 4.3. Page Read Operation - High Speed Mode, 4.4. Page Program Operation, 4.5. Internal Data Move Operation, 4.6. Block Erase (D8h), 4.7. Reset (FFh or FEh), 4.10. Block Lock Operation, 4.11. Block Protection Operation (One Time Program), 4.12. Parameter Page Read Operation, 4.14. Unique ID Read Operation and 4.16. Internal ECC. Updated 6.4. Several Programming Cycles on the Same Page (Partial Page Program) and 6.7. Failure Phenomena. Separate the definition of address into RA (row address) and CA (column address) in 4.1 Command Set Table. Added description in the weight of package, the definition of Reserved bits in Feature Table and 6.9. NAND Management Corrected typo, and described some notes. Renewed Reliability Guidance. Modified Table 16 Block Lock Setting and removed note. Changed “RESTRICTIONS ON PRODUCT USE”. Rebrand as “KIOXIA” Corrected Package Weight and typo. Described some notes and deleted unnecessary parts. 43 2019-10-01 TC58CVG2S0HRAIG RESTRICTIONS ON PRODUCT USE KIOXIA Corporation and its subsidiaries and affiliates are collectively referred to as “KIOXIA”. Hardware, software and systems described in this document are collectively referred to as “Product”.  KIOXIA reserves the right to make changes to the information in this document and related Product without notice.  This document and any information herein may not be reproduced without prior written permission from KIOXIA. Even with KIOXIA's written permission, reproduction is permissible only if reproduction is without alteration/omission.  Though KIOXIA works continually to improve Product's quality and reliability, Product can malfunction or fail. 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Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.  Please contact your KIOXIA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. KIOXIA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. © 2016-2019 KIOXIA Corporation 44 2019-10-01