FT24C02A-FLR-T

Fremont Micro Devices FT24C02A-FXX Two-Wire Serial EEPROM 2K (16-bit wide) FEATURES  Low voltage and low power operations:  FT24C02A-FXX: VCC = 1.8V to 5.5V, Industrial temperature range (-40℃ to 85℃). Maximum Standby current < 1µA (typically 0.02µA and 0.06µ A @ 1.8V and 5.5V respectively). 16 bytes page write mode.  Partial page write operation allowed.  Internally organized: 256 × 8 (2K).  Standard 2-wire bi-directional serial interface.  Schmitt trigger, filtered inputs for noise protection.  Self-timed programming cycle (5ms maximum).  1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.  Automatic erase before write operation.  High reliability: typically 1,000,000 cycles endurance.  100 years data retention.  Standard 8-pin DIP/SOP/MSOP/TSSOP/DFN and 5-pin SOT-23/TSOT-23 Pb-free packages. en fid on DESCRIPTION tia l   The FT24C02A-FXX is 2048 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 256 words of 8 bits (1 byte) each. The devices are C fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP, 8-lead DFN and 5-lead SOT-23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write FM D functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page1 Fremont Micro Devices FT24C02A-FXX PIN CONFIGURATION Pin Function SDA SCL VCC Serial Data Input / Open Drain Output Serial Clock Input Power Supply GND NC Ground No-Connect Table 1 All these packaging types come in conventional or Pb-free certified. FT24C02A-FXX 2 7 3 6 4 5 8L 8L 8L 8L 8L DIP SOP TSSOP DFN MSOP FT24C02A-FXX VCC NC SCL SDA SCL GND SDA 1 5 NC 4 VCC en 8 2 3 5L SOT-23 5L TSOT-23 fid 1 on NC NC NC GND tia l Pin Name FM D C Figure 1: Package types © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page2 Fremont Micro Devices FT24C02A-FXX ABSOLUTE MAXIMUM RATINGS Industrial operating temperature: -40℃ to 85℃ Storage temperature: -50℃ to 125℃ Input voltage on any pin relative to ground: -0.3V to VCC + 0.3V Maximum voltage: 8V ESD protection on all pins: >2000V FM D C on fid en tia l * Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. © 2015 Fremont Micro Devices Inc. Figure 2: Block Diagram Confidential Rev1.0 FT24C02A-FXX-page3 Fremont Micro Devices FT24C02A-FXX PIN DESCRIPTIONS (A) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (B) SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can MEMORY ORGANIZATION tia l be wired-OR with other open-drain output devices. The FT24C02A-FXX devices have 16 pages. Since each page has 16 bytes, random word addressing to DEVICE OPERATION (A) SERIAL CLOCK AND DATA TRANSITIONS en FT24C02A-FXX will require 8 bits data word addresses. fid The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP (B) START CONDITION on condition as described below. With SCL ≥ VIH, a SDA transition from high to low is interpreted as a START condition. All valid C commands must begin with a START condition. (C) STOP CONDITION With SCL ≥ VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read D or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the FM STANDBY mode after the self-timed internal programming finish. (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation. © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page4 Fremont Micro Devices FT24C02A-FXX SCL SDA Data Valid Data Transition STOP Condition tia l START Condition Figure 3: Timing diagram for START and STOP conditions en START Condition fid SCL on Data in ACK C Data out FM D Figure 4: Timing diagram for output ACKNOWLEDGE © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page5 Fremont Micro Devices FT24C02A-FXX DEVICE ADDRESSING The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are not cared and could be coded from 000 (b) to 111 (b). Only one FT24C02A-FXX device can be used on the on 2-wire bus. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. WRITE OPERATIONS (A) BYTE WRITE tia l The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. A byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM device address and then a write command. If the device address bits match the chip select en th address, the EEPROM device will acknowledge at the 9 clock cycle. The micro-controller will then th send the rest of the lower 8 bits word address. At the 18 cycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then transmit the 8 bit data. Following an th fid ACKNOWLDEGE signal from the EEPROM at the 27 clock cycle, the micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed programming mode during which all external inputs will be disabled. After a programming time of T WC, the byte on programming will finish and the EEPROM device will return to the STANDBY mode. (B) PAGE WRITE A page write is similar to a byte write with the exception that one to sixteen bytes can be programmed C along the same page or memory row. All FT24C02A-FXX are organized to have 16 bytes per memory row or page. With the same write command as the byte write, the micro-controller does not issue a STOP bit after st D sending the 1 byte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27 th clock cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the th 36 cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller th FM sends a STOP bit after the n × 9 clock cycle. After which the EEPROM device will go into a selftimed partial or full page programming mode. After the page programming completes after a time of TWC, the devices will return to the STANDBY mode. The least significant 4 bits of the word address (column address) increments internally by one after receiving each data word. The rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. The first page write data word can be of any column address. Up to 16 data words can be loaded into a page. If more then 16 data th st th words are loaded, the 9 data word will be loaded to the 1 data word column address. The 10 data word will be loaded to the 2 nd data word column address and so on. In other word, data word address (column address) will “roll” over the previously loaded data. © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page6 Fremont Micro Devices FT24C02A-FXX (C) ACKNOWLEDGE POLLING ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9 th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a th valid ACKNOWLEDGE signal at the 9 clock cycle. READ OPERATIONS th The read command is similar to the write command except the 8 read/write bit in address word is set to “1”. tia l The three read operation modes are described as follows: (A) CURRENT ADDRESS READ The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the th en micro-controller issues a START bit and a valid device address word with the read/write bit (8 ) set to th “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9 serial clock cycle. An 8bit data word will then be serially clocked out. For current address read the micro-controller will not issue an th fid automatically increase by one. The internal address word counter will then ACKNOWLEDGE signal on the 18 clock cycle. The micro-controller issues a valid STOP bit after th (B) SEQUENTIAL READ on the 18 clock cycle to terminate the read operation. The device then returns to STANDBY mode. The sequential read is very similar to current address read. The micro-controller issues a START bit th and a valid device address word with read/write bit (8 ) set to “1”. The EEPROM will response with th serial clock cycle. An 8-bit data word will then be serially C an ACKNOWLEDGE signal on the 9 clocked out. Meanwhile the internally address word counter will then automatically increase by one. th Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18 clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the D ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an th FM ACKNOWLEDGE signal on the 27 clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead. © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page7 Fremont Micro Devices FT24C02A-FXX (C) RANDOM READ Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a th START bit first, follows by a valid device address with the read/write bit (8 ) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send the address word. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, - which is to read the current address. W R I T E DEVICE ADDRESS WORD ADDRESS DATA *** LRAM S / C S B WK B M S B LA SC BK fid SDA LINE S T O P en S T A R T tia l the EEPROM will reset the internal programming process and continue to execute the new instruction A C K S T A R T W R I T E DEVICE ADDRESS LRAM S / C S B WK B FM D M S B WORD ADDRESS(N) C *** SDA LINE on Figure 5: Byte Write S T O P DATA(N) ... L A S C B K A C K DATA(N+X) A C K Figure 6: Page Write S T A R T R E A D DEVICE ADDRESS S T O P DATA *** SDA LINE M S B L RA S / C B WK N O A C K Figure 7: Current Address Read © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page8 Fremont Micro Devices FT24C02A-FXX R E A D DEVICE ADDRESS DATA (N) DATA (N+1) DATA (N+2) S T O P DATA (N+3) *** SDA LINE RA / C WK A C K A C K N O A C K A C K W R I T E DEVICE ADDRESS S T A R T WORD ADDRESS(N) DEVICE ADDRESS *** *** L RA M S / C S B WK B M S B LA SC BK M S B S T O P DATA (N) L RA S / C B WK fid SDA LINE R E A D en S T A R T tia l Figure 8: Sequential Read N O A C K FM D C Notes: 1) * = Don’t Care bits on Figure 9: Random Read Figure 10: SCL and SDA Bus Timing © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page9 Fremont Micro Devices FT24C02A-FXX AC CHARACTERISTICS 1.8 V Parameter Min fSCL tLOW tHIGH tI tAA Clock frequency, SCL tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH 0.6 Data in hold time 120 µs ns 0.55 µs 0.5 0.6 µs 0.25 µs 0.25 µs 0 µs 100 ns (1) 0.3 0.3 µs 300 100 ns STOP set-up time 0.6 0.25 µs Date out hold time 50 50 ns o 25 C, Page Mode, 3.3V fid Endurance 0.2 1.3 100 (1) Write cycle time (1) µs en Input fall time 0.9 0 Data in set-up time WR 5 1,000,000 5 ms Write Cycles 1. This Parameter is expected by characterization but is not fully screened by test. on Notes*: START set-up time kHz 0.4 180 0.3 Unit Max 0.4 0.6 (1) Clock low to data out valid Time the bus must be free before a new transmission can (1) start START hold time Input rise time Min 1000 1.3 Clock pulse width high tBUF Max 400 Clock pulse width low Noise suppression time 2.5-5.0 V tia l Symbol 2. AC Measurement conditions: RL (Connects to Vcc): 1.3KΩ C Input Pulse Voltages: 0.3Vcc to 0.7Vcc FM D Input and output timing reference Voltages: 0.5Vcc © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page10 Fremont Micro Devices FT24C02A-FXX DC CHARACTERISTICS Symbol Parameter Test Conditions Min Typical Max Unit s 5.5 V VCC1 Power supply VCC ICC Supply read current VCC @ 5.0V SCL = 400 kHz 0.5 1.0 mA ICC Supply write current VCC @ 5.0V SCL = 400 kHz 2.0 3.0 mA ISB1 Supply current VCC @ 1.8V, VIN = VCC or VSS 1.0 µA ISB2 Supply current VCC @ 2.5V, VIN = VCC or VSS 1.0 µA ISB3 Supply current VCC @ 5.0V, VIN = VCC or VSS 1.0 µA IIL Input leakage current Output leakage current VIN = VCC or VSS 3.0 µA VIN = VCC or VSS 3.0 µA 0.07 tia l ILO 1.8 Input low level -0.6 VCC × 0.3 V VIH Input high level VCC × 0.7 VCC + 0.5 V VOL1 Output low level VCC @ 1.8V, IOL = 0.15 mA VOL2 Output low level VCC @ 3.0V, IOL = 2.1 mA 0.2 V 0.4 V FM D C on fid en VIL © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page11 Fremont Micro Devices FT24C02A-FXX ORDER CODE: FT24C02A - F X R - X Packaging B: Tube T: Tape and Reel Circuit Type HSF R: RoHS G: RoHS and Halogen Free Version F: Without device address and write protect en tia l Package D: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 L: SOT23-5 P: TSOT23-5 N: DFN8 Temperature Range Vcc SOT23-5 -40℃-85℃ 1.8V-5.5V TSOT23-5 -40℃-85℃ 1.8V-5.5V DIP8 -40℃-85℃ 1.8V-5.5V TSSOP8 DFN8 C -40℃-85℃ -40℃-85℃ Packaging Order code RoHS Tape and Reel FT24C02A-FLR-T Green Tape and Reel FT24C02A-FLG-T RoHS Tape and Reel FT24C02A-FPR-T Green Tape and Reel FT24C02A-FPG-T RoHS Tube FT24C02A-FDR-B Green Tube FT24C02A-FDG-B Tube FT24C02A-FSR-B RoHS Tape and Reel FT24C02A-FSR-T Tube FT24C02A-FSG-B Tape and Reel FT24C02A-FSG-T Tube FT24C02A-FTR-B Tape and Reel FT24C02A-FTR-T Tube FT24C02A-FTG-B Tape and Reel FT24C02A-FTG-T RoHS Tape and Reel FT24C02A-FNR-T Green Tape and Reel FT24C02A-FNG-T 1.8V-5.5V D -40℃-85℃ FM SOP8 HSF on Package fid ORDER INFORMATION Green RoHS 1.8V-5.5V Green 1.8V-5.5V © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page12 Fremont Micro Devices FT24C02A-FXX Dimensions In Millimeters Min Dimensions In Inches Max Min Max A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 FM D Symbol C on fid en tia l SOP8 PACKAGE OUTLINE DIMENSIONS e 1.270 (BSC) 0.244 0.050 (BSC) L 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8° © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page13 Fremont Micro Devices FT24C02A-FXX on fid en tia l SOT-23-5 PACKAGE OUTLINE DIMENSIONS Dimensions In Millimeters C Symbol Dimensions In Inches Min Max Min Max 1.050 1.250 0.041 0.049 A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 FM D A e 0.95 (BSC) 0.116 0.037 (BSC) e1 1.800 2.000 0.071 0.079 L 0.300 0.600 0.012 0.024 0° 8° 0° 6°  © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page14 Fremont Micro Devices FT24C02A-FXX Fremont Micro Devices (SZ) Limited #1&5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, Shenzhen Tel: (86 755) 86117811 Fax: (86 755) 86117810 Fremont Micro Devices (Hong Kong) Limited #16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong Kong Tel: (852) 27811186 Fax: (852) 27811144 tia l Fremont Micro Devices (USA), Inc. en 42982 Osgood Road Fremont, CA 94539 Tel: (1-510) 668-1321 Fax: (1-510) 226-9918 FM D C on fid Web Site: http://www.fremontmicro.com/ * Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners. © 2015 Fremont Micro Devices Inc. Confidential Rev1.0 FT24C02A-FXX-page15