FT25H04S-RT

Fremont Micro Devices Preliminary FT25H04/02 FT25H04/02 DATASHEET © 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page1 Preliminary FT25H04/02 Fremont Micro Devices CONTENTS 1. FEATURES ............................................................................................................................................ 3 2. GENERAL DESCRIPTION .................................................................................................................... 4 3. MEMORY ORGANIZATION................................................................................................................... 6 4. DEVICE OPERATION............................................................................................................................ 8 5. DATA PROTECTION ............................................................................................................................. 8 6. STATUS REGISTER ............................................................................................................................ 10 7. COMM ANDS DESCRIPTION ..............................................................................................................11 7.1. WRITE ENABLE (WREN) (06H) ........................................................................................................ 13 7.2. WRITE DISABLE (WRDI) (04H)......................................................................................................... 13 7.3. READ STATUS REGISTER (RDSR) (05H)........................................................................................... 13 7.4. WRITE STATUS REGISTER (WRSR) (01H)......................................................................................... 14 7.5. READ DATA BYTES (READ) (03H) .................................................................................................... 14 7.6. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH)................................................................. 15 7.7. PAGE PROGRAM (PP) (02H)............................................................................................................. 15 7.8. SECTOR ERASE (SE) (20H).............................................................................................................. 16 7.9. BLOCK ERASE (BE) (D8H) ............................................................................................................... 17 7.10. CHIP ERASE (CE) (60/C7H)........................................................................................................... 17 7.11. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H)........................................................................ 18 7.12. READ IDENTIFICATION (RDID) (9FH)............................................................................................... 19 8. ELECTRICAL CHARACTERISTICS ................................................................................................... 20 POWER-ON TIMING ........................................................................................................................... 20 8.1. 8.2. INITIAL DELIVERY STATE ................................................................................................................... 20 8.3. DATA RETENTION AND ENDURANCE ................................................................................................... 20 8.4. LATCH UP CHARACTERISTICS ............................................................................................................ 20 8.5. ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 21 8.6. CAPACITANCE MEASUREMENT CONDITION ......................................................................................... 21 8.7. DC CHARACTERISTICS ..................................................................................................................... 22 8.8. AC CHARACTERISTICS ..................................................................................................................... 23 9. ORDERING INFORMATION................................................................................................................ 25 10. PACKAGE INFORMATION.............................................................................................................. 26 10.1. PACKAGE SOP8 150MIL................................................................................................................ 26 10.2. PACKAGE SOP8 208MIL................................................................................................................ 27 10.3. PACKAGE DIP8 300MIL ................................................................................................................. 28 10.4. PACKAGE VSOP8 208MIL ............................................................................................................. 29 10.5. PACKAGE TSSOP8 173MIL ........................................................................................................... 30 11. REVISION HISTORY........................................................................................................................ 31 © 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page2 Preliminary FT25H04/02 Fremont Micro Devices 1. FEATURES „ „ 4M-bit/2M-bit Serial Flash y 512K-byte/256K-byte y 256 bytes per programmable page Standard SPI y „ High Speed Clock Frequency y „ „ „ Standard SPI: SCLK, CS#, SI, SO, 120MHz for fast read with 30PF load Program/Erase Speed y Page Program time: 1.5ms typical y Sector Erase time: 150ms typical y Block Erase time: 0.8s typical y Chip Erase time: 6s/3s typical Flexible Architecture y Sector of 4K-byte y Block of 64k-byte Low Power Consumption y 10mA maximum active current y 5uA maximum standby current „ Single Power Supply Voltage: Full voltage range:2.7~3.6V „ Minimum 100,000 Program/Erase Cycle „ Hardware Features y 8-pin SOP8 (150mil) y 8-pin SOP8 (200mil) y 8-pin DIP8 (300mil) y 8-pin VSOP8 (200mil) y 8-pin TSSOP8 (173mil) © 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page3 Preliminary FT25H04/02 Fremont Micro Devices 2. GENERAL DESCRIPTION The FT25H04/02 (4M-bit/2M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI). SPI clock frequency of up to 120MHz is supported for fast read command. CONNECTION DIAGRAM CS# 1 8 VCC SO 2 7 NC Top View NC 3 6 SCLK VSS 4 5 SI 8 – LEAD SOP PIN DESCRIPTION Pin Name I/O Description CS# I Chip Select Input SO O Data Output Ground VSS SI I Data Input SCLK I Serial Clock Input VCC © 2014 Fremont Micro Devices Inc. Power Supply Confidential Rev1.0 DS25H04/02-page4 Preliminary FT25H04/02 Fremont Micro Devices BLOCK DIAGRAM Write Control Logic SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter © 2014 Fremont Micro Devices Inc. Flash Memory Column Decode And 256-Byte Page Buffer SI SO Write Protect Logic And Row Decode Status Register Byte Address Latch/Counter Confidential Rev1.0 DS25H04/02-page5 Preliminary FT25H04/02 Fremont Micro Devices 3. MEMORY ORGANIZATION FT25H04/02 Each Device has Each block has Each sector has Each page has 512K/256K 64K 4K 256 bytes 2K/1K 256 16 - pages 128/64 16 - - sectors 8/4 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE FT25H04 64K Bytes Block Sector Architecture Block 7 6 …… …… 2 1 0 © 2014 Fremont Micro Devices Inc. Sector Address range 127 07F000H 07FFFFH …… …… …… 112 070000H 070FFFH 111 06F000H 06FFFFH …… …… …… 96 060000H 060FFFH …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH Confidential Rev1.0 DS25H04/02-page6 Preliminary FT25H04/02 Fremont Micro Devices FT25H02 64K Bytes Block Sector Architecture Block 3 2 1 0 © 2014 Fremont Micro Devices Inc. Sector Address range 63 03F000H 03FFFFH …… …… …… 48 030000H 030FFFH 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH Confidential Rev1.0 DS25H04/02-page7 Preliminary FT25H04/02 Fremont Micro Devices 4. DEVICE OPERATION The FT25H04/02 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. 5. DATA PROTECTION The FT25H04/02 provide the following data protection methods: „ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: y Power-Up y Write Disable (WRDI) y Write Status Register (WRSR) y Page Program (PP) y Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) „ Software Protection Mode: y SRWD=0, the Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not change y SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. Table1.1 FT25H04 Protected Area Sizes Status bit Protect level Protect Block 0 0(none) None 0 1 1 (1 block) Block 7 0 1 0 2 (2 blocks) Block 6-7 0 1 1 3 (4 blocks) Block 4-7 1 0 0 4 (8 blocks) All 1 0 1 5 (All) All 1 1 0 6 (All) All 1 1 1 7 (All) All BP2 BP1 BP0 0 0 0 © 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page8 Preliminary FT25H04/02 Fremont Micro Devices Table1.2 FT25H02 Protected Area Sizes Status bit Protect level Protect Block 0 0(none) None 0 1 1 (1 block) Block 3 0 1 0 2 (2 blocks) Block 2-3 0 1 1 3 (4 blocks) ALL BP2 BP1 BP0 0 0 0 © 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page9 Preliminary FT25H04/02 Fremont Micro Devices 6. STATUS REGISTER S7 S6 S5 S4 S3 S2 S1 S0 SRWD Reserved Reserved BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, the device is busy in program/erase/write status register progress. When WIP bit sets 0, the device is not in program, erase or write status register . WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1.1 or 1.2).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. Chip Erase command will be ignored if one or more of the Block Protect (BP2, BP1, BP0) bits are 1. SRWD bit. The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit in the status register that provide another software protection. Once it is set to 1, the Write Status Register (WRSR) instruction is no longer accepted and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. SRWD Status register Memory Status register can be written in (WEL 0 bit is set to "1") and the SRWD, BP2-BP0 bits can be changed 1 The protected area cannot be program or erase The SRWD, BP2-BP0 of status register The protected area cannot be program bits cannot be changed or erase © 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page10 Preliminary FT25H04/02 Fremont Micro Devices 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable, CS# must be driven high exactly at a byte boundary, otherwise the command is rejected. That is CS# must driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table2. Commands Command Name Byte1 Byte2 Write Enable 06H Write Disable 04H Read Status Register 05H (S7-S0) (continuous) Write Status Register 01H (S7-S0) (continuous) Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous) Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous) Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) Sector Erase 20H A23-A16 A15-A8 A7-A0 Block Erase D8H A23-A16 A15-A8 A7-A0 Chip Erase C7/60H Manufacturer/Device ID 90H dummy dummy 00H (MID7-MID0) (DID7-DID0) (JDID15-JDI (JDID7-JDID Read Identification 9FH (MID7-MID0) D8) 0) © 2014 Fremont Micro Devices Inc. Byte3 Byte4 Byte5 Byte6 n-Bytes (continuous) (continuous) Confidential Rev1.0 DS25H04/02-page11 Preliminary FT25H04/02 Fremont Micro Devices Table of ID Definitions: FT25H04 Operation Code M7-M0 ID15-ID8 9FH 0E 40 90H 0E ID7-ID0 13 12 FT25H02 Operation Code M7-M0 ID15-ID8 9FH 0E 40 90H 0E © 2014 Fremont Micro Devices Inc. ID7-ID0 12 11 Confidential Rev1.0 DS25H04/02-page12 Preliminary FT25H04/02 Fremont Micro Devices 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes lowÆSend Write Enable commandÆCS# goes high. Figure1. Write Enable Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 06H High-Z SO 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes lowÆSend Write Disable commandÆCS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Figure2. Write Disable Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO 04H High-Z 7.3. Read Status Register (RDSR) (05H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. © 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page13 Preliminary FT25H04/02 Fremont Micro Devices Figure3. Read Status Register Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI 05H S7~S0 out High-Z SO S7~S0 out 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB 7.4. Write Status Register (WRSR) (01H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S6, S5, S1 and S0 of the Status Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1.1 and 1.2. The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit, the Write Status Register (WRSR) command allows the user to set the Status Register Write Disable (SRWD) bit to 1. The Status Register Write Disable (SRWD) bit allow the device to be put in another Software Protected Mode. Once the SRWD bit is set to 1, the Write Status Register (WRSR) command is not executed, and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. Figure4. Write Status Register Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI Command Status Register in 01H 7 6 5 4 3 2 1 0 MSB High-Z SO 7.5. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being © 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H04/02-page14 Preliminary FT25H04/02 Fremont Micro Devices latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Therefore, the whole memory can be read with a single Read Data Bytes (READ) command. During an Erase, Program or Write cycle, Read Data Byte (READ) command will be rejected without affecting the cycle in progress. Figure5. Read Data Bytes Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SCLK Command SI 24-bit address(A23:A0) 23 22 21 20 19 03H 7 6 5 4 3 2 1 0 MSB Data Out2 Data Out1 High-Z SO MSB 7 6 5 4 3 2 1 0 7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte address can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure6. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 24-bit address(A23:A0) 23 22 21 20 19 0BH 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 Data Out1 SO Data Out2 Data Out3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB 7.7. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command © 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H04/02-page15 Preliminary FT25H04/02 Fremont Micro Devices must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes lowÆsending Page Program commandÆ3-byte address on SIÆat least 1 byte data on SIÆ CS# goes high. The command sequence is shown in Figure7. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Page Program Cycle.. Page Program (PP) command applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bit (see Table1.1 or 1.2) is not executed. Figure7. Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 24-bit address(A23:A0) Command SI 23 22 21 20 19 02H Data Byte1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2072 2073 2074 2075 2076 2077 2078 2079 CS# SCLK Data Byte2 SI Data Byte3 Data Byte4 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB MSB Data Byte256 7 6 5 4 3 2 1 0 MSB 7.8. Sector Erase (SE) (20H) The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes lowÆsending Sector Erase commandÆ3-byte address on SIÆCS# goes high. The command sequence is shown in Figure8. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. © 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H04/02-page16 Preliminary FT25H04/02 Fremont Micro Devices While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Sector Erase cycle. Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP2, BP1, BP0) bit (see Table1.1 or 1.2) is not executed. Figure8. Sector Erase Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 20H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB 7.9. Block Erase (BE) (D8H) The Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The Block Erase command sequence: CS# goes lowÆsend Block Erase command Æ 3-byte address on SIÆCS# goes high. The command sequence is shown in Figure9. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Block Erase cycle. Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table1.1 or 1.2) is not executed. Figure9. Block Erase Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI D8H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB 7.10. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command © 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H04/02-page17 Preliminary FT25H04/02 Fremont Micro Devices is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes lowÆsend Chip Erase commandÆCS# goes high. The command sequence is shown in Figure10. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Chip Erase cycle. The Chip Erase (CE) command is ignored if one or more sectors are protected by (BP2, BP1, BP0) bits. Figure10. Chip Erase Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60H or C7H 7.11. Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is for reading both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure11. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure11. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 90H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK SI Manufacturer ID SO Device ID Manufacturer ID 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB © 2014 Fremont Micro Devices Inc. MSB MSB Confidential Rev1.1 DS25H04/02-page18 Preliminary FT25H04/02 Fremont Micro Devices 7.12. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure12. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. After CS# is driven high, the device returns to Standby Mode and awaits for new command. Figure12. Read Identification ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 49 50 51 52 53 54 55 SCLK Command SI 9FH Memory Type JDID15-JDID8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Manufacturer ID High-Z SO MSB CS# 16 17 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK SI SO Memory Type Capacity Manufacturer ID JDID15-JDID8 JDID7-JDID0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB © 2014 Fremont Micro Devices Inc. MSB MSB Confidential Rev1.1 DS25H04/02-page19 Preliminary FT25H04/02 Fremont Micro Devices 8. ELECTRICAL CHARACTERISTICS 8.1. Power-on Timing Vcc(max) Program,Erase and Write command are ignored Chip Selection is not allowed Vcc(min) Reset State tVSL Read command is allowed Device is fully accessible VWI tPUW Time Table3. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL VCC(min) To CS# Low 10 us tPUW Time Delay Before Write Instruction 1 10 ms VWI Write Inhibit Voltage 1 2.5 V 8.2. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 8.3. Data Retention and Endurance Parameter Minimum Pattern Data Retention Time Erase/Program Endurance Test Condition Min Unit 150ć 10 Years 125ć 20 Years -40 to 85ć 100K Cycles 8.4. Latch up Characteristics Parameter Min Max Input Voltage Respect To VSS On I/O Pins -1.0V VCC+1.0V VCC Current -100mA 100mA © 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H04/02-page20 Preliminary FT25H04/02 Fremont Micro Devices 8.5. Absolute Maximum Ratings Parameter Value Unit Ambient Operating Temperature -40 to 85 ć Storage Temperature -65 to 150 ć Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.5 to 4.0 V -0.5 to 4.0 V VCC Output timing reference level Input timing reference level 0.8VCC 0.7VCC AC Measurement level 0.5VCC 0.2VCC 0.1VCC Note:Input pulse rise and fall time are