NV6125-RA

NV6125 NV6125 650 V GaNFast™ Power IC 2. Description QFN 6 x 8 mm The NV6125 is a thermally enhanced version of the popular NV6115 650 V GaNFast™ power IC, optimized for high-frequency and soft-switching topologies. Monolithic integration of FET, drive and logic creates an easy-to-use ‘digital-in, power-out’ high-performance powertrain building block, enabling designers to create the fastest, smallest, most efficient integrated powertrain in the world. The highest dV/dt immunity, high-speed integrated drive and industry-standard low-profile, low-inductance, 6 x 8 mm SMT QFN package allow designers to exploit Navitas GaN technology with simple, quick, dependable solutions for breakthrough power density and efficiency. Navitas’ GaNFast™ power ICs extend the capabilities of traditional topologies such as flyback, half-bridge, resonant, etc. to MHz+ and enable the commercial introduction of breakthrough designs. Simplified schematic 1. Features GaNFast™ Power IC • Thermally enhanced version of NV6115 • Large cooling pad • Enhanced thermals when using CS resistor • Monolithically-integrated gate drive • Wide VCC range (10 to 30 V) • Programmable turn-on dV/dt • 200 V/ns dV/dt immunity • 650 V eMode GaN FET 3. Topologies / Applications • • • • • • • • • • Low 175 mΩ resistance • Zero reverse-recovery charge • 2 MHz operation Small, low-profile SMT QFN • 6 x 8 mm footprint, 0.85 mm profile • Minimized package inductance AC-DC, DC-DC, DC-AC Buck, boost, half bridge, full bridge Active Clamp Flyback, LLC resonant, Class D Quasi-Resonant Flyback Mobile fast-chargers, adapters Notebook adaptors LED lighting, solar micro-inverters TV / monitor, wireless power Server, telecom & networking SMPS Environmental • RoHS, Pb-free, REACH-compliant 4. Typical Application Circuits DCIN(+) DCOUT(+) DCIN(+) D VCC PWM D 10V to 24V PWM Half Bridge Driver IC REG VDD DZ REG VDD VCC dV/dt DZ dV/dt NV6125 CP S D CP S VCC PWM REG VDD NV6125 CP DZ S dV/dt 10V to 24V NV6125 DCIN(-) DCIN(-) DCOUT(-) Half-bridge Boost Final Datasheet PGND 1 Rev Nov 21, 2019 NV6125 NV6125 5. Table of Contents 1. Features ................................................................. 1 Normal Operating Mode ................................... 12 2. Description............................................................. 1 Standby Mode .................................................. 12 3. Topologies / Applications ..................................... 1 Programmable Turn-on dV/dt Control .............. 12 4. Typical Application Circuits ................................. 1 Current Sensing ............................................... 13 5. Table of Contents .................................................. 2 Paralleling Devices ........................................... 13 6. Specifications ........................................................ 3 3.3V PWM Input Circuit .................................... 14 Absolute Maximum Ratings (1) ............................ 3 PCB Layout Guidelines .................................... 14 Recommended Operating Conditions(3) ............. 3 Recommended Component Values.................. 15 ESD Ratings ...................................................... 4 8.9.1. Zener Diode Selection .............................. 15 Thermal Resistance ........................................... 4 Drain-to-Source Voltage Considerations ........ 16 Electrical Characteristics.................................... 5 9. Recommended PCB Land Pattern ...................... 17 Switching Waveforms ........................................ 6 10. PCB Layout Guidelines ..................................... 18 Characteristic Graphs ........................................ 7 11. QFN Package Outline ........................................ 20 7. Internal Schematic, Pin Configurations and Functions ................................................................. 10 12. Tape and Reel Dimensions ............................... 21 13. Ordering Information ......................................... 23 8. Functional Description........................................ 11 14. Revision History................................................. 23 Start Up............................................................ 11 Final Datasheet 2 Rev Nov 21, 2019 NV6125 NV6125 6. Specifications Absolute Maximum Ratings(1) (with respect to Source (pad) unless noted) SYMBOL VDS PARAMETER Drain-to-Source Voltage MAX UNITS -7 to +650 V VTDS Transient Drain-to-Source Voltage 750 V VCC Supply Voltage 30 V (2) VPWM PWM Input Pin Voltage -3 to +30 V VDZ VDD Setting Pin Voltage 6.6 V VDD Drive Supply Voltage 7.2 V VCP Cooling Pad Voltage -10 to +10 V ID Continuous Drain Current (@ TC = 100ºC) 8 A ID PULSE Pulsed Drain Current (10 µs @ TJ = 25°C) 16 A I PULSE Pulsed Drain Current (10 µs @ TJ = 125°C) 12 A Slew Rate on Drain-to-Source 200 V/ns Operating Junction Temperature -55 to 150 ºC Storage Temperature -55 to 150 ºC D dV/dt T J TSTOR (1) Absolute maximum ratings are stress ratings; devices subjected to stresses beyond these ratings may cause permanent damage. (2) < 100 µs. VTDS is intended for surge rating during non-repetitive events (for example start-up, line interruption). Recommended Operating Conditions(3) SYMBOL PARAMETER VDZ Drive Supply Set Zener Voltage VDD Drive Supply Voltage IDD_EXT (4) MIN TYP MAX UNITS 5.8 6.2 6.6 V 5.5 Regulator External Load Current 7.0 V 3.0 mA Gate Drive Turn-On Current Set Resistance(5) 10 25 200 Ω PWM Input Pin Voltage 0 5 Min. of (VCC or 20) V VCC Supply Voltage 10 24 V TC Operating Case Temperature -40 125 °C RDD VPWM (3) Exposure to conditions beyond maximum recommended operating conditions for extended periods of time may affect device reliability. (4) Use of Zener diode other than 6.2 V is not recommended. See Table I for recommended part numbers of 6.2 V Zener diodes. (5) RDD resistor must be used. Minimum 10 Ohm to ensure application and device robustness. Final Datasheet 3 Rev Nov 21, 2019 NV6125 NV6125 ESD Ratings SYMBOL PARAMETER MAX UNITS HBM Human Body Model (per JS-001-2014) 1,000 V CDM Charged Device Model (per JS-002-2014) 1,000 V TYP UNITS Thermal Resistance SYMBOL PARAMETER RɵJC (6) Junction-to-Case 1.9 ºC/W RɵJA (6) Junction-to-Ambient 40 ºC/W (6) Rɵ measured on DUT mounted on 1 square inch 2 oz Cu (FR4 PCB) Final Datasheet 4 Rev Nov 21, 2019 NV6125 NV6125 Electrical Characteristics Typical conditions: VDS = 400 V, VCC = 15 V, VDZ = 6.2 V, FSW = 1 MHz, TAMB = 25 ºC, ID = 4 A, RDD = 10 Ω (or specified) SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS VCC Supply Characteristics IQCC VCC Quiescent Current 0.85 IQCC-SW VCC Operating Current 2.3 1.5 mA VPWM = 0 V mA FSW = 1 MHz, VDS = Open Low-Side Logic Input Characteristics VPWMH Input Logic High Threshold (rising edge) VPWML Input Logic Low Threshold (falling edge) VI-HYS 4 1 V V Input Logic Hysteresis 0.5 V TON Turn-on Propagation Delay 11 ns Fig.1, Fig.2 TOFF Turn-off Propagation Delay 9 ns Fig.1, Fig.2 TR Drain rise time 6 ns Fig.1, Fig.2 TF Drain fall time 3 ns Fig.1, Fig.2 Switching Characteristics FSW Switching Frequency tPW Pulse width IDSS Drain-Source Leakage Current 0.2 25 µA VDS = 650 V, VPWM = 0 V IDSS Drain-Source Leakage Current 7 50 µA VDS = 650 V, VPWM = 0 V, TC = 125 ºC 260 mΩ VPWM = 6 V, ID = 4 A mΩ VPWM = 6 V, ID = 4 A, TC = 125 ºC 0.02 2 MHz 1000 µs GaN FET Characteristics RDS(ON) Drain-Source Resistance 175 RDS(ON) Drain-Source Resistance 362 Source-Drain Reverse Voltage 3.2 QOSS Output Charge 16 nC Q Reverse Recovery Charge 0 nC COSS Output Capacitance 18 pF VDS = 400 V, VPWM = 0 V 24 pF VDS = 400 V, VPWM = 0 V 40 pF VDS = 400 V, VPWM = 0 V VSD RR CO(er)(7) CO(tr)(8) Effective Output Capacitance, Energy Related Effective Output Capacitance, Time Related 5 V VPWM = 0 V, ISD = 4 A VDS = 400 V, VPWM = 0 V (7) CO(er) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 400 V (8) CO(tr) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 400 V Final Datasheet 5 Rev Nov 21, 2019 NV6125 NV6125 Switching Waveforms (TC = 25 ºC unless otherwise specified) Fig. 1. Inductive switching circuit Fig. 2. Propagation delay and rise/fall time definitions Final Datasheet 6 Rev Nov 21, 2019 NV6125 NV6125 Characteristic Graphs (GaN FET, TC = 25 ºC unless otherwise specified) Fig. 3. Pulsed Drain current (ID PULSE) vs. Fig. 4. Pulsed Drain current (ID PULSE) vs. drain-to-source voltage (VDS) at T = 25 °C drain-to-source voltage (VDS) at T = 125 °C Fig. 5. Source-to-drain reverse conduction voltage Fig. 6. Drain-to-source leakage current (IDSS) vs. drain-to-source voltage (VDS) Fig. 7. VPWMH and VPWML vs. junction temperature (TJ) Fig. 8. Normalized on-resistance (RDS(ON)) vs. junction temperature (TJ) Final Datasheet 7 Rev Nov 21, 2019 NV6125 NV6125 Characteristic Graphs (Cont.) Fig. 9. Output capacitance (COSS) vs. drain-to-source voltage (VDS) Fig. 10. Energy stored in output capacitance (EOSS) vs. drain-to-source voltage (VDS) Fig. 11. Charge stored in output capacitance (QOSS) vs. drain-to-source voltage (VDS) Fig. 12. VCC operating current (IQCC-SW) vs. operating frequency (FSW) Fig. 13. VCC quiescent current (IQCC) vs. Fig. 14. Propagation delay (TON and TOFF) vs. junction temperature (TJ) supply voltage (VCC) Final Datasheet 8 Rev Nov 21, 2019 NV6125 NV6125 Characteristic Graphs (Cont.) Fig. 16. Power dissipation (PTOT) vs. case temperature (TC) Fig. 15. Slew rate (dV/dt) vs. gate drive turn-on current set resistance (RDD) at T = 25 °C Fig. 17. Max. thermal transient impedance (ZthJC) vs. pulse width (tP) Final Datasheet 9 Rev Nov 21, 2019 NV6125 NV6125 7. Internal Schematic, Pin Configurations and Functions Package Top View Pin I/O(1) Description CP T Metal cooling pad on bottom of package for thermal management. CP must be connected to Source or circuit PGND. Do not leave CP unconnected or floating! 2,3,4,5,6 S O, G 10 DZ I Gate drive supply voltage set pin (connect 6.2 V Zener to GND). 11 VDD I Gate drive supply voltage. Gate drive turn-on current set pin (using RDD). 27 PWM I PWM input 28 VCC P Supply voltage (10V to 24V) 15,16,17,18,19,20,21,22,23 D P Drain of power FET Number Symbol 1,7,8,9,12,13,14,24,25,26,29,30,31 Source of power FET & GaN IC supply ground. (1) I = Input, O = Output, P = Power, G = GaN IC Ground, T = Thermal Final Datasheet 10 Rev Nov 21, 2019 NV6125 NV6125 8. Functional Description The following functional description contains additional information regarding the IC operating modes and pin functionality. Start Up When the VCC supply is first applied to the NV6125, care should be taken such that the VDD and DZ pins are up at their correct voltage levels before the PWM input signal starts. The VDD pin ramp up time is determined by the internal regulator current at this pin and the external CVDD capacitor. Also, since the DZ pin voltage sets the VDD voltage level, the VDD pin will ramp up together with the DZ pin (Fig. 18). Fig. 18. Start-up circuit For half-bridge configurations, it is important that the VCC supply, the DZ pin, and the VDD supply of the high-side NV6125 are all charged up to their proper levels before the first high-side PWM pulses start. For LLC applications, a long on-time PWM pulse to the low-side (> 10 µs) is typically provided by the LLC controller to allow the supply pins of the high-side NV6125 to charge up (through the external bootstrap diode) to their correct levels before the first high-side PWM pulses start (Fig. 19). For active clamp flyback (ACF) applications, the halfbridge must be ready very quickly due to the soft-start mode of the ACF controller. When the first few PWM pulses are generated by the ACF controller, the highside supply pins of the NV6125 will require a few lowside pulses to charge up (through the external bootstrap diode) before the high-side starts to switch (Fig. 20). Fig. 19. LLC half-bridge start-up timing diagram Fig. 20. ACF half-bridge start-up timing diagram Final Datasheet 11 Rev Nov 21, 2019 NV6125 NV6125 Normal Operating Mode 200K During Normal Operating Mode, all of the internal circuit blocks are active. VCC is operating within the recommended range of 10 V to 24 V, the VDD pin is at the voltage set by the Zener diode at the DZ pin (6.2 V), and the internal gate drive and power FET are both enabled. The external PWM signal at the PWM pin determines the frequency and duty-cycle of the internal gate of the power FET. As the PWM voltage toggles above and below the rising and falling input thresholds (4 V and 1 V), the internal gate of the power FET toggles on and off between VDD and 0 V (Fig. 21). The drain of the power FET then toggles between the source voltage (typically power ground) and a higher voltage level (650 V max), depending on the external power conversion circuit topology. D CP CP CP PWM 30 VCC BSS84A CP 100K CP 10V to 24V 23 SI1330EDL ENABLE 1 CP 22 D D S 31 CP S S D D S D S D CP D D CP CP CP VDD DZ CP CP 8 15 Fig. 22 Standby mode VCC cut-off circuit Programmable Turn-on dV/dt Control VPWM During first start-up pulses or during hard-switching conditions, it is desirable to limit the slew rate (dV/dt) of the drain of the power FET during turn-on. This is necessary to reduce EMI or reduce circuit switching noise. To program the turn-on dV/dt rate of the internal power FET, a resistor (RDD) is placed in between the VDD capacitor and the VDD pin. This resistor (RDD) sets the turn-on current of the internal gate driver and therefore sets the turn-on falling edge dV/dt rate of the drain of the power FET (Fig. 23). A typical turn-on slew-rate change with respect to RDD is shown in Fig. 15. Minimum 10 Ω RDD is required. t VDS VBUS TOFF TON t TPERIOD Fig. 21. Normal operating mode timing diagram Standby Mode VPWM For applications where a low standby power is required, an external series cut-off circuit (Fig. 22) can be used to disconnect VCC of the NV6125 from the main VCC supply of the power supply. This will reduce VCC current consumption when the converter is in burst mode during light-load or open load conditions. The VCC cut-off circuit consists of a series PMOS FET that is turned on and off with a pull-down NMOS FET. The gate of the NMOS is controlled by an external ENABLE signal that should be provided by the main controller of the power supply. The capacitor value at the VCC pin should then be selected according to the desired start-up speed of the NV6125 each time the ENABLE signal toggles high. A 22 nF capacitor at VCC, for example, will give a typical start-up time of approximately 2 μs. An additional 200 kΩ resistor is placed across the PMOS cut-off FET to provide a small VCC voltage level for proper start-up. Final Datasheet TOFF TON t VDS VBUS Drain turn-on Falling edge Increase RDD to Decrease dv/dt t Fig. 23. Turn-on dV/dt slew rate control 12 Rev Nov 21, 2019 Current Sensing Paralleling Devices For many applications it is necessary to sense the cycleby-cycle current flowing through the power FET. To sense the current flowing through the NV6125, a standard current-sensing resistor can be placed in between the source and power ground (Fig. 24). In this configuration, all of the components around the NV6125 (CVCC, CVDD, DZ, etc.) should be grounded with a single connection at the source. Also, an additional RC filter can be inserted between the PWM signal and the PWM pin (100 Ω, 100 pF typical). This filter is necessary to prevent false triggering due to high-frequency voltage spikes occurring at the source node due to external parasitic inductance from the source PCB trace or the current-sensing resistor itself. For increased cooling pad PCB copper area it may be desired to connect CP to the circuit PGND. Fig. 24 shows the components around the NV6125 grounded at the source pins (S and CP connected to PGND). This allows for all CP pins and CP pad to be connected to a large and continuous thermal copper area without being obstructed by the current sensing resistor. CP must be connected to source (S) or circuit PGND! Do not leave CP floating! NV6125 NV6125 For some applications it is desirable to parallel ICs in order to reduce conduction losses and temperatures. Two NV6125 ICs can be connected in parallel in a PFC boost application working in boundary-conduction mode (BCM) only. The parallel configuration for two NV6125 ICs is shown in Fig. 25. The paired pins that are connected together include the drain pins (D), the source pins (S), the VCC pins, the PWM pins, and the DZ. A single DZ diode can be shared by both ICs. The VDD pins are not connected together and require separate VDD supply capacitors (CVDD1, CVDD2) and separate turnon current set resistors (RDD1, RDD2). Each IC should have its own local VCC supply filter capacitor (CVCC1, CVCC2). The PWM pins can have a single filter resistor (RPWM) but separate filter capacitors (CPWM1, CPWM2) should be placed at the PWM pin of each IC. When designing the PCB layout for the two paralleled ICs, the drain and source connections should be made as symmetrical as possible two avoid any parasitic inductance or capacitance mismatch. Fig. 25. Boost schematic using two parallel ICs Fig. 24. Current sensing circuit Final Datasheet 13 Rev Nov 21, 2019 NV6125 NV6125 The following rules should be followed carefully during 3.3V PWM Input Circuit the design of the PCB layout: For some applications where a 3.3 V PWM signal is required (DSP, MCU, etc.) an additional buffer can be placed before the PWM input pin (Fig. 26) with the buffer supply voltage connected to the VDD capacitor. 1) Place all IC filter and programming components directly next to the IC. These components include (CVCC, CVDD, RPWM, CPWM, RDD and DZ). 2) Keep ground trace of IC filter and programming components separate from power GND trace. Do not run power GND currents through ground trace of filter components! 3) For best thermal management, place thermal vias in the source pad area to conduct the heat out through the bottom of the package and through the PCB board to other layers (see Section 10 for correct layout examples). 4) Use large PCB thermal planes (connected with thermal vias to the source pad) and additional PCB layers to reduce IC temperatures as much as possible (see Section 10 for correct layout examples). Fig. 26. 3.3 V PWM input buffer circuit 5) For half-bridge layouts, do not extend copper planes from one IC across the components or pads of the other IC! PCB Layout Guidelines 6) For high density designs, use a 4-layer PCB and 2 oz. copper to route signal connections. This allows layout to maintain large thermal copper planes and reduce power device temperature. The design of the PCB layout is critical for good noise immunity, sufficient thermal management, and proper operation of the IC. Typical PCB layout examples for without current sensing resistor and with current sensing resistor are all shown in Section 10. Final Datasheet 14 Rev Nov 21, 2019 NV6125 NV6125 Recommended Component Values The following table (Table I) shows the recommended component values for the external filter capacitors, Zener diode, and RDD connected to the pins of the NV6125. These components should be placed as close as possible to the IC. Please see PCB Layout guidelines for more information. The Zener diode at the DZ pin should be a lowcurrent type with a flat knee, and the min/max limits must be followed. RDD must be a minimum of 10 Ω to ensure application and device robustness. SYM DESCRIPTION PART NO. SUPPLIER MIN TYP MAX UNITS CVCC Maximum VCC supply capacitor 0.1 µF CVDD VDD supply capacitor 0.01 µF RDD Gate drive turn-on current set resistor BZT52B6V2 RHG DZ MM3Z6V2ST1G PDZ6.2B.115 PLVA662A.215 LM3Z6V2T1 VDD set Zener diode (DZ pin) Taiwan Semiconductor Corporation ON-Semiconductor Nexperia (NXP) Nexperia (NXP) Leshan Radio Company 10 25 200 Ω 5.8 6.2 6.6 V RPWM PWM filter resistor 100 Ω CPWM PWM filter capacitor 100 pF Table I. Recommended component values. 8.9.1. Zener Diode Selection The Zener voltage is a critical parameter that sets the internal reference for gate drive voltage and other circuitry. The Zener diode needs to be selected such that the voltage on the DZ pin is within recommended operating conditions (5.8 V to 6.6 V) across operating temperature (-40°C to 125°C) and bias current (10 µA to 1 mA). To ensure effective operation, the current vs. voltage characteristics of the Zener diode should be measured down to 10 µA to ensure flat characteristics across the current operating range (10 µA to 1 mA). The recommended part numbers meet these requirements. If the Zener selected by user does not ensure that the voltage on the DZ pin is always within the recommended operating range, the functionality and reliability of the NV6125 can be impacted. An external resistor (~47 kΩ) between VCC and DZ can improve Zener voltage stability by adding bias current to the DZ pin to ensure the voltage on the DZ pin is always within the recommended operating range (Fig. 27). This will add ~200 µA of quiescent current. Fig. 27. Increasing Zener bias current for stable Zener voltage Final Datasheet 15 Rev Nov 21, 2019 NV6125 NV6125 Drain-to-Source Voltage Considerations For single ended topologies, such as quasi-resonant (QR) flyback, the drain-to-source voltage (VDS) of the GaN Power IC should be carefully designed in order to ensure there is sufficient derating to provide exceptional quality and long-term reliability. The different voltage stress levels found in a typical QR flyback topology can be analyzed using Fig. 28 as a reference. When the device is switched off each cycle, the energy stored in the transformer magnetizing and leakage inductances will cause the VDS to spike to the level of VSPIKE. The clamp circuit of the QR system should be designed such that VSPIKE stays below the Absolute Maximum rated VDS of 650 V on a cycle-bycycle basis in continuous operation. Following the dissipation of the spike energy due to the leakage inductance, the device VDS will be determined by the addition of the bus voltage (rectified AC input voltage) and the transformer reflected voltage which is defined in Fig. 28 as the VDS-OFF. To ensure sufficient design margin and long-term reliability, it is recommended to design the system such that VDS-OFF follows a typical derating of 80% from absolute maximum voltage. Finally, the transient drain to source voltage rating (V TDS) is provided in order to provide a margin for events that could occur on a non-repetitive basis, such as line surge due to lightning strikes. VTDS ensures excellent device robustness provided any non-repetitive drain-to-source voltages are maintained less than 750 V. For half-bridge based topologies, such as LLC or PFC, VDS voltage is clamped to the bus voltage. VDS should be designed such that it meets the VDS-OFF derating guideline. The VTDS of 750 V can also be used for non-repetitive events such as lightning surge. 750 V = VTDS VSPIKE Transient Voltage Surge Region 650 V = VDS-Abs Max 80% of V DS Abs Max 520 V = 80% of VDS Abs Max VDS-OFF Fig. 28. QR flyback drain-to-source voltage stress diagram Final Datasheet 16 Rev Nov 21, 2019 NV6125 NV6125 9. Recommended PCB Land Pattern All dimensions are in mm Final Datasheet 17 Rev Nov 21, 2019 NV6125 NV6125 10. PCB Layout Guidelines Without CS Resistor: Final Datasheet 18 Rev Nov 21, 2019 NV6125 NV6125 With CS Resistor: Final Datasheet 19 Rev Nov 21, 2019 NV6125 NV6125 11. QFN Package Outline Final Datasheet 20 Rev Nov 21, 2019 NV6125 NV6125 12. Tape and Reel Dimensions Final Datasheet 21 Rev Nov 21, 2019 NV6125 NV6125 7” Reel 13” Reel Final Datasheet 22 Rev Nov 21, 2019 NV6125 NV6125 13. Ordering Information Part Number Operating Temperature Grade Storage Temperature Range Package MSL Rating Packing (Tape & Reel) NV6125 -40 °C to +125 °C TCASE -55 °C to +150 °C TCASE 6 x 8 mm QFN 3 1,000 : 7” Reel 5,000 : 13” Reel 14. Revision History Date Status Notes July 19, 2019 Preliminary First publication Nov 21, 2019 Initial Release Updated figures 16&17; added section 8.10 Additional Information DISCLAIMER Navitas Semiconductor Inc. (Navitas) reserves the right to modify the products and/or specifications described herein at any time and at Navitas’ sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice . Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any k ind, whether express or implied. This document is presented only as a guide and does not convey any license under intellectual property rights of Navitas or any third parties. Navitas’ products are not intended for use in applications involving extreme environmental conditions or in life support systems. Products supplied under Navitas Terms and Conditions. Navitas Semiconductor, Navitas, GaNFast and associated logos are registered trademarks of Navitas. Copyright ©2019 Navitas Semiconductor Inc. All rights reserved Navitas Semiconductor Inc., 2101 E El Segundo Blvd, Suite 205, El Segundo, California 90245, USA. Final Datasheet 23 Contact info@navitassemi.com Rev Nov 21, 2019