S-8253A/B Series
BATTERY PROTECTION IC
FOR 2-SERIAL OR 3-SERIAL-CELL PACK
N
www.sii-ic.com
Rev.5.0_00
DE
SI
G
© Seiko Instruments Inc., 2003-2010
The S-8253A/B Series are protection ICs for 2-serial or 3-serial cell lithium-ion rechargeable batteries and include highaccuracy voltage detectors and delay circuits.
These ICs are suitable for protecting lithium-ion rechargeable battery packs from overcharge, overdischarge and overcurrent.
Features
High-accuracy voltage detection for each cell
• Overcharge detection voltage n (n = 1 to 3)
3.9 V to 4.4 V (50 mV steps)
*1
• Overcharge release voltage n (n = 1 to 3)
3.8 V to 4.4 V
• Overdischarge detection voltage n (n = 1 to 3)
2.0 V to 3.0 V (100 mV steps)
*2
• Overdischarge release voltage n (n = 1 to 3)
2.0 V to 3.4 V
(2) Three-level overcurrent detection (Including load short circuiting detection)
• Overcurrent detection voltage 1
0.05 V to 0.30 V (50 mV steps) Accuracy ±25 mV
• Overcurrent detection voltage 2
0.5 V (Fixed)
• Overcurrent detection voltage 3
1.2 V (Fixed)
(3) Delay times (Overcharge, Overdischarge, Overcurrent) are generated by an internal circuit.
are unnecessary).
(4) Charge / discharge operation can be inhibited via the control pin.
(5) 0 V battery charge function available / unavailable are selectable.
(6) High-voltage withstand devices
Absolute maximum rating 26 V
(7) Wide operating voltage range
2 V to 24 V
(8) Wide operating temperature range
−40°C to +85°C
(9) Low current consumption
• Operation mode
28 μA max. (+25°C)
• Power-down mode
0.1 μA max. (+25°C)
*3
(10) Lead-free, Sn100%, halogen-free
Accuracy ±25 mV
Accuracy ±50 mV
Accuracy ±80 mV
Accuracy ±100 mV
(External capacitors
MM
EN
DE
D
FO
R
NE
W
(1)
Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage
(Overcharge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.1 V to 0.4 V in
50 mV steps.)
*2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.2 V to 0.7 V in
100 mV steps.)
*3. Refer to “Product Name Structure” for details.
RE
Applications
CO
*1.
• Lithium-ion rechargeable battery packs
• Lithium polymer rechargeable battery packs
•
NO
T
Package
8-Pin TSSOP
Seiko Instruments Inc.
1
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Block Diagrams
S-8253A Series
DOP
DE
SI
G
N
1.
Oscillator, counter,
controller
NE
W
COP
VDD
+
−
95 kΩ
200 nA
CO
CTL
CTLH
VC1
−
+
+
−
VC2
−
+
+
−
VSS
All diodes shown in figure are parasitic diodes.
Figure 1
NO
T
2
+
−
CTLM
RE
Remark
D
MM
EN
900 kΩ
+
−
DE
VMP
FO
+
−
R
−
+
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
S-8253B Series
DOP
DE
SI
G
N
2.
Oscillator, counter,
controller
W
COP
VDD
NE
−
+
+
−
95 kΩ
+
−
MM
EN
DE
900 kΩ
200 nA
−
+
+
−
CTLH
VC2
−
+
+
−
CTLM
VSS
All diodes shown in figure are parasitic diodes.
Figure 2
NO
T
RE
Remark
CO
CTL
VC1
D
VMP
FO
+
−
R
+
−
Seiko Instruments Inc.
3
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Product Name Structure
Product Name
1. 1
Environmental code = U
S-8253
x
xx
−
T8T1
N
1.
U
DE
SI
G
Rev.5.0_00
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
T8T1: 8-Pin TSSOP, Tape
*2
FO
Environmental code = G
S-8253
x
xx
−
T8T1
G
Z
DE
Fixed
D
1. 2
R
*1. Refer to the tape specifications.
*2. Refer to the “3. Product Name List”.
NE
Product series name
A:
2-cell
B:
3-cell
W
Serial code
Sequentially set from AA to ZZ
MM
EN
Environmental code
G:
Lead-free (for details, please contact our sales office)
Package abbreviation and IC packing specifications
T8T1: 8-Pin TSSOP, Tape
*1
2.
Refer to the tape specifications.
Refer to the “3. Product Name List”.
Package
NO
T
Package Name
8-Pin TSSOP
4
Product series name
A:
2-cell
B:
3-cell
RE
*1.
*2.
CO
Serial code*2
Sequentially set from AA to ZZ
Environmental code = G
Environmental code = U
Package
FT008-A-P-SD
FT008-A-P-SD
Seiko Instruments Inc.
Drawing Code
Tape
FT008-E-C-SD
FT008-E-C-SD
Reel
FT008-E-R-SD
FT008-E-R-S1
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Product Name List
Table 1
N
3.
S-8253A Series (For 2-Serial Cell)
Overcharge
detection voltage
[VCU]
Overcharge
release voltage
[VCL]
Overdischarge
detection voltage
[VDL]
Overdischarge
release voltage
[VDU]
Overcurrent
detection voltage 1
[VIOV1]
0 V battery
charge function
S-8253AAA-T8T1
4.350 ±0.025 V
4.050 ±0.050 V
2.40 ±0.080 V
2.70 ±0.100 V
0.300 ±0.025 V
Available
S-8253AAB-T8T1
4.350 ±0.025 V
4.050 ±0.050 V
2.70 ±0.080 V
2.70 ±0.080 V
0.300 ±0.025 V
Available
S-8253AAC-T8T1
4.350 ±0.025 V
4.050 ±0.050 V
2.40 ±0.080 V
2.70 ±0.100 V
0.080 ±0.025 V
Available
S-8253AAD-T8T1
4.250 ±0.025 V
4.050 ±0.050 V
2.40 ±0.080 V
2.70 ±0.100 V
0.120 ±0.025 V
Available
S-8253AAE-T8T1
4.350 ±0.025 V
4.050 ±0.050 V
2.80 ±0.080 V
3.00 ±0.100 V
0.300 ±0.025 V
Available
S-8253AAF-T8T1
4.350 ±0.025 V
4.050 ±0.050 V
2.40 ±0.080 V
2.60 ±0.100 V
0.300 ±0.025 V
Unavailable
S-8253AAG-T8T1
4.280 ±0.025 V
4.080 ±0.050 V
2.40 ±0.080 V
2.70 ±0.100 V
0.150 ±0.025 V
Unavailable
S-8253AAH-T8T1
4.350 ±0.025 V
4.150 ±0.050 V
2.30 ±0.080 V
2.30 ±0.080 V
0.090 ±0.025 V
Available
0 V battery
charge function
W
NE
S-8253B Series (For 3-Serial Cell)
R
Table 2
DE
SI
G
Model No.
Overcharge
detection voltage
[VCU]
Overcharge
release voltage
[VCL]
Overdischarge
detection voltage
[VDL]
Overdischarge
release voltage
[VDU]
Overcurrent
detection voltage 1
[VIOV1]
S-8253BAA-T8T1
4.350 ±0.025 V
4.050 ±0.050 V
2.40 ±0.080 V
2.70 ±0.100 V
0.300 ±0.025 V
Available
S-8253BAB-T8T1
4.325 ±0.025 V
4.075 ±0.050 V
2.20 ±0.080 V
2.90 ±0.100 V
0.200 ±0.025 V
Unavailable
S-8253BAC-T8T1
4.350 ±0.025 V
4.050 ±0.050 V
2.40 ±0.080 V
2.70 ±0.100 V
0.080 ±0.025 V
Available
S-8253BAD-T8T1
4.250 ±0.025 V
4.050 ±0.050 V
2.40 ±0.080 V
2.70 ±0.100 V
0.120 ±0.025 V
Available
S-8253BAE-T8T1
4.350 ±0.025 V
4.150 ±0.050 V
2.20 ±0.080 V
2.40 ±0.100 V
0.100 ±0.025 V
Available
S-8253BAF-T8T1
4.280 ±0.025 V
4.180 ±0.050 V
2.20 ±0.080 V
2.50 ±0.100 V
0.190 ±0.025 V
Unavailable
S-8253BAG-T8T1
4.280 ±0.025 V
4.180 ±0.050 V
2.20 ±0.080 V
2.50 ±0.100 V
0.125 ±0.025 V
Unavailable
S-8253BAH-T8T1
4.350 ±0.025 V
4.150 ±0.050 V
2.20 ±0.080 V
2.40 ±0.100 V
0.250 ±0.025 V
Available
S-8253BAI-T8T1
4.350 ±0.025 V
4.150 ±0.050 V
2.20 ±0.080 V
2.40 ±0.100 V
0.160 ±0.025 V
Available
MM
EN
DE
D
FO
Model No.
Please contact the SII marketing department for the products with the detection voltage value other than those
specified above.
2. : GZ or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
NO
T
RE
CO
Remark 1.
Seiko Instruments Inc.
5
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Pin Configuration
DOP
COP
VMP
CTL
1
2
3
4
VDD
VC1
VC2
VSS
8
7
6
5
Symbol
Description
Connection pin for discharge control FET gate
1
DOP
(CMOS output)
Connection pin for charge control FET gate
2
COP
(Nch open-drain output)
Pin for voltage detection between VDD and VMP
3
VMP
(Detection pin for overcurrent)
Input pin for charge / discharge control signal,
Pin for shortening test time
4
CTL
( L : Normal operation,
H : inhibit charge / discharge
M (VDD × 1 / 2) : shorten test time)
Input pin for negative power supply,
5
VSS
Connection pin for negative voltage of battery 2
6
VC2
No connection *1
Connection pin for negative voltage of battery 1,
7
VC1
for positive voltage of battery 2
Input pin for positive power supply,
8
VDD
Connection pin for positive voltage of battery 1
*1. No connection is electrically open. This pin can be connected to VDD or
VSS.
Remark Refer to the package drawings for the external views.
DE
D
FO
R
NE
W
Figure 3
Pin No.
S-8253A Series
N
Table 3
8-Pin TSSOP
Top view
DE
SI
G
Rev.5.0_00
Symbol
CO
RE
NO
T
6
S-8253B Series
Description
Connection pin for discharge control FET gate
1
DOP
(CMOS output)
Connection pin for charge control FET gate
2
COP
(Nch open-drain output)
Pin for voltage detection between VDD and VMP
3
VMP
(Detection pin for overcurrent)
Input pin for charge / discharge control signal,
pin for shortening test time
4
CTL
( L : Normal operation,
H : inhibit charge / discharge,
M (VDD × 1 / 2) : shorten test time)
Input pin for negative power supply,
5
VSS
Connection pin for negative voltage of battery 3
Connection pin for negative voltage of battery 2,
6
VC2
for positive voltage of battery 3
Connection pin for negative voltage of battery 1,
7
VC1
for positive voltage of battery 2
Input pin for positive power supply,
8
VDD
Connection pin for positive voltage of battery 1
Remark Refer to the package drawings for the external views.
MM
EN
Pin No.
Table 4
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Absolute Maximum Ratings
Table 5
Symbol
Applicable Pins
Absolute Maximum Ratings
DE
SI
G
Item
N
(Ta = 25°C unless otherwise specified)
Unit
Input voltage between VDD and VSS
VDS
⎯
Input pin voltage
VIN
VC1, VC2
VMP pin input voltage
VVMP
VMP
VSS − 0.3 to VSS + 26
V
DOP pin output voltage
VDOP
DOP
VSS − 0.3 to VDD + 0.3
V
COP pin output voltage
VCOP
COP
VSS − 0.3 to VVMP + 0.3
V
CTL input pin voltage
VIN_CTL
CTL
Power dissipation
PD
⎯
Operating ambient temperature
Topr
⎯
VSS − 0.3 to VDD + 0.3
300 (When not mounted on board)
700*1
− 40 to + 85
V
mW
mW
°C
Storage temperature
Tstg
⎯
− 40 to + 125
°C
NE
W
V
V
FO
R
*1. When mounted on board
[Mounted board]
(1) Board size :
114.3 mm × 76.2 mm × t1.6 mm
(2) Board name : JEDEC STANDARD51-7
VSS − 0.3 to VSS + 26
VSS − 0.3 to VDD + 0.3
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
D
DE
700
600
500
MM
EN
Power Dissipation (PD) [mW]
800
400
300
200
100
CO
0
50
100
150
Ambient Temperature (Ta) [°C]
Power Dissipation of Package (When Mounted on Board)
RE
Figure 4
0
NO
T
Seiko Instruments Inc.
7
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Electrical Characteristics
1.
Except Detection Delay Time
Table 6 (1 / 2)
Item
Symbol
Conditions
Min.
DETECTION VOLTAGE
Overcharge detection voltage n
VCUn
3.90 V to 4.40 V, Adjustable
Overcharge release voltage n
VCLn
3.80 V to 4.40 V,
Adjustable
VCL ≠ VCU
VDLn
2.0 V to 3.0 V, Adjustable
Overdischarge release voltage n
VDUn
2.0 V to 3.40 V,
Adjustable
VDL ≠ VDU
VCLn
VCLn
VDLn
NE
Overdischarge detection voltage n
VCUn
W
VCL = VCU
VCUn
−0.025
VCLn
−0.05
VCLn
−0.025
VDLn
−0.080
VDUn
−0.10
VDUn
−0.08
VIOV1
−0.025
0.40
0.9
−1.0
−0.5
DE
SI
G
N
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
condicircuit
tion
R
VDL = VDU
VDUn
VDUn
VCUn
V
+0.025
VCLn
V
+0.05
VCLn
V
+0.025
VDLn
V
+0.080
VDUn
V
+0.10
VDUn
V
+0.08
VIOV1
V
+0.025
0.60
V
1.5
V
1.0
mV / °C
0.5
mV / °C
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
⎯
⎯
1
1
⎯
⎯
VIOV1
Overcurrent detection voltage 2
Overcurrent detection voltage 3
Temperature coefficient 1 *1
Temperature coefficient 2 *2
0 V BATTERY CHARGE FUNCTION
0 V battery charge starting charger voltage
0 V battery charge inhibition battery
voltage
INTERNAL RESISTANCE
Resistance between VMP and VDD
Resistance between VMP and VSS
VIOV2
VIOV3
TCOE1
TCOE2
0.05 V to 0.30 V, Adjustable
Based on VDD
Based on VDD
Based on VDD
*3
Ta = 0°C to 50°C
*3
Ta = 0°C to 50°C
V0CHA
0 V battery charging available
⎯
0.8
1.5
V
12
5
V0INH
0 V battery charging unavailable
0.4
0.7
1.1
V
12
5
70
450
95
900
120
1800
kΩ
kΩ
6
6
2
2
MM
EN
DE
D
FO
Overcurrent detection voltage 1
V1 = V2 = V3 = 3.5 V, VVMP = VSS
*4
V1 = V2 = V3 = 1.8 V, VVMP = VDD
*4
NO
T
RE
CO
RVMD
RVMS
8
Seiko Instruments Inc.
VIOV1
0.50
1.2
0
0
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Table 6 (2 / 2)
INPUT VOLTAGE
Operating voltage
between VDD and VSS
VDSOP
Conditions
Min.
Output voltage of DOP and COP fixed
2
VCTLH
⎯
VDD
−0.5
CTL input voltage “L”
VCTLL
⎯
⎯
⎯
24
V
⎯
⎯
⎯
⎯
V
7
1
⎯
VSS
+0.5
V
7
1
W
CTL input voltage “H”
N
Symbol
DE
SI
G
Item
(Ta = 25°C unless otherwise specified)
Test
Test
Typ.
Max.
Unit
condicircuit
tion
NO
T
RE
CO
MM
EN
DE
D
FO
R
NE
INPUT CURRENT
*4
IOPE
V1 = V2 = V3 = 3.5 V
⎯
μA
Current consumption on operation
14
28
5
2
*4
IPDN
V1 = V2 = V3 = 1.5 V
⎯
⎯
0.1
Current consumption at power down
μA
5
2
*4
IVC1
V1 = V2 = V3 = 3.5 V
−0.3
0
0.3
VC1 pin current
μA
9
3
*4
IVC2
V1 = V2 = V3 = 3.5 V
−0.3
0
0.3
VC2 pin current
μA
9
3
*4
I
V1
=
V2
=
V3
=
3.5
V,
V
=
V
⎯
⎯
0.1
CTL pin current “H”
μA
8
3
CTLH
CTL1
DD
*4
ICTLL
V1 = V2 = V3 = 3.5 V, VCTL1 = VSS
−0.4
–0.2
⎯
CTL pin current “L”
μA
8
3
OUTPUT CURRENT
ICOH
VCOP = 24 V
⎯
⎯
0.1
μA
COP pin leakage current
10
4
ICOL
VCOP = VSS + 0.5 V
10
⎯
⎯
COP pin sink current
μA
10
4
I
V
=
V
−
0.5
V
10
⎯
⎯
DOP pin source current
μA
11
4
DOH
DOP
DD
IDOL
VDOP = VSS + 0.5 V
10
⎯
⎯
DOP pin sink current
μA
11
4
*1. Voltage temperature coefficient 1 : Overcharge detection voltage
*2. Voltage temperature coefficient 2 : Overcurrent detection voltage 1
*3. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
*4. Because S-8253A Series are the protection ICs for 2-serial cell, there is no V3 for them.
Seiko Instruments Inc.
9
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
(1)
Detection Delay Time
S-8253AAA, S-8253AAB, S-8253AAC, S-8253AAD, S-8253AAE, S-8253AAF, S-8253AAG, S-8253BAA,
S-8253BAC, S-8253BAD, S-8253BAE, S-8253BAH
N
2.
Item
Symbol
Condition
Min.
Typ.
DELAY TIME (Ta = 25°C)
tCU
⎯
0.92
1.15
Overdischarge detection delay time
Overcurrent detection delay time 1
Overcurrent detection delay time 2
Overcurrent detection delay time 3
tDL
tIOV1
tIOV2
tIOV3
⎯
⎯
⎯
⎯
115
7.2
3.6
220
144
9
4.5
300
1
1
1
1
0.92
1.15
1.38
s
3
1
115
3.6
0.89
220
144
4.5
1.1
300
173
5.4
1.4
380
ms
ms
ms
μs
3
4
4
4
1
1
1
1
Condition
Min.
Typ.
Max.
Unit
Test
Condition
Test
Circuit
tCU
⎯
0.92
1.15
1.38
s
3
1
tDL
tIOV1
tIOV2
tIOV3
⎯
⎯
⎯
⎯
115
14.5
3.6
220
144
18
4.5
300
173
22
5.4
380
ms
ms
ms
μs
3
4
4
4
1
1
1
1
FO
⎯
⎯
⎯
⎯
D
tDL
tIOV1
tIOV2
tIOV3
MM
EN
Symbol
Table 9
NO
T
RE
CO
Min.
DE
Overdischarge detection delay time
Overcurrent detection delay time 1
Overcurrent detection delay time 2
Overcurrent detection delay time 3
10
1
3
4
4
4
Test
Circuit
⎯
Overdischarge detection delay time
Overcurrent detection delay time 1
Overcurrent detection delay time 2
Overcurrent detection delay time 3
3
ms
ms
ms
μs
Test
Condition
tCU
Overcharge detection delay time
s
173
10.8
5.4
380
Unit
Overcharge detection delay time
DELAY TIME (Ta = 25°C)
1.38
Max.
Condition
DELAY TIME (Ta = 25°C)
Item
Test
Circuit
Typ.
Symbol
S-8253AAH
Test
Condition
R
Table 8
(3)
Unit
NE
S-8253BAB, S-8253BAF, S-8253BAG, S-8253BAI
Item
Max.
W
Overcharge detection delay time
DE
SI
G
Table 7
(2)
Rev.5.0_00
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Test Circuits
Overcharge Detection Voltage 1, Overcharge Release Voltage 1, Overdischarge Detection Voltage 1,
Overdischarge Release Voltage 1
(Test Condition 1, Test Circuit 1)
N
1.
1. 1
DE
SI
G
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the
COP and DOP pins are “L” (VDD × 0.1 V or lower) (this status is referred to as the initial status).
Overcharge Detection Voltage 1 (VCU1), Overcharge Release Voltage 1 (VCL1)
Overdischarge Detection Voltage 1 (VDL1), Overdischarge Release Voltage 1 (VDU1)
NE
1. 2
W
Overcharge detection voltage 1 (VCU1) is the voltage of V1 when the voltage of the COP pin is “H” (VDD × 0.9 V or
more) after the V1 voltage has been gradually increased starting at the initial status. Overcharge release voltage
1 (VCL1) is the voltage of V1 when the voltage at the COP pin is low after the V1 voltage has been gradually
decreased.
R
Overdischarge detection voltage 1 (VDL1) is the voltage of V1 when the voltage of the DOP pin is high after the V1
voltage has been gradually decreased starting at the initial status. Overdischarge release voltage 1 (VDU1) is the
voltage of V1 when the voltage at the DOP pin is low after the V1 voltage has been gradually increased.
Overcurrent Detection Voltage 1, Overcurrent Detection Voltage 2, Overcurrent Detection Voltage 3
(Test Condition 2, Test Circuit 1)
D
2.
FO
By changing Vn (n = 2: S-8253A Series, n = 2, 3: S-8253B Series) the overcharge detection voltage (VCUn),
overcharge release voltage (VCLn), overdischarge detection voltage (VDLn), and overdischarge release voltage (VDUn)
can be measured in the same way as when n = 1.
Overcurrent Detection Voltage 1 (VIOV1)
MM
EN
2. 1
DE
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
Overcurrent detection voltage 1 (VIOV1) is the voltage of V5 when the voltages of the COP pin and DOP pin are
high after the V5 voltage has been gradually increased starting at the initial status.
2. 2
Overcurrent Detection Voltage 2 (VIOV2)
2. 3
CO
Overcurrent detection voltage 2 (VIOV2) is the voltage of V5 when the voltages of the COP pin and DOP pin are
high within the minimum and maximum values of overcurrent detection time 2 (tIOV2) after the voltage of V5 was
instantaneously increased (within 10 μs) starting at the initial status.
Overcurrent Detection Voltage 3 (VIOV3)
RE
Overcurrent detection voltage 3 (VIOV3) is the voltage of V5 when the voltages of the COP pin and DOP pin are
high within the minimum and maximum values of overcurrent detection time 3 (tIOV3) after the voltage of V5 was
instantaneously increased (within 10 μs) starting at the initial status.
NO
T
Seiko Instruments Inc.
11
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
3.
Rev.5.0_00
Overcharge Detection Delay Time, Overdischarge Detection Delay Time
(Test Condition 3, Test Circuit 1)
3. 1
DE
SI
G
N
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
Overcharge Detection Delay Time (tCU)
The overcharge detection delay time (tCU) is the time it takes for the voltage of the COP pin to change from low to
high after the voltage of V1 is instantaneously changed from overcharge detection voltage 1 (VCU1) − 0.2 V to
overcharge detection voltage 1 (VCU1) + 0.2 V (within 10 μs) starting at the initial status.
Overdischarge Detection Delay Time (tDL)
W
3. 2
4.
NE
The overdischarge detection delay time (tDL) is the time it takes for the voltage of the DOP pin to change from low
to high after the voltage of V1 is instantaneously changed from overdischarge detection voltage 1 (VDL1) + 0.2 V to
overdischarge detection voltage 1 (VDL1) − 0.2 V (within 10 μs) starting at the initial status.
Overcurrent Detection Delay Time 1, Detection Delay Time 2, Detection Delay Time 3
(Test Condition 4, Test Circuit 1)
4. 1
Overcurrent Detection Delay Time 1 (tIOV1)
FO
R
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
Overcurrent Detection Delay Time 2 (tIOV2)
DE
4. 2
D
Overcurrent detection delay time 1 (tIOV1) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 0.35 V (within 10 μs) starting at the initial status.
4. 3
MM
EN
Overcurrent detection delay time 2 (tIOV2) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 0.7 V (within 10 μs) starting at the initial status.
Overcurrent Detection Delay Time 3 (tIOV3)
Overcurrent detection delay time 3 (tIOV3) is the time it takes for the voltage of the DOP pin to change from low to
high after the voltage of V5 is instantaneously changed to 1.6 V (within 10 μs) starting at the initial status.
Consumption on Operation, Power Consumption at Power-down
(Test Condition 5, Test Circuit 2)
5. 1
CO
5.
Power Consumption on Operation (IOPE)
5. 2
RE
The power consumption during operation (IOPE) is the current of the VSS pin (ISS) when V1 = V2 = 3.5 V (S-8253A
Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), S1 = ON, and S2 = OFF.
Power Consumption at Power-down (IPDN)
NO
T
The power consumption at power-down (IPDN) is the current of the VSS pin (ISS) when V1 = V2 = 1.5 V (S-8253A
Series), V1 = V2 = V3 = 1.5 V (S-8253B Series), S1 = OFF, and S2 = ON.
12
Seiko Instruments Inc.
Rev.5.0_00
6.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Resistance between VMP and VDD, Resistance between VMP and VSS
(Test Condition 6, Test Circuit 2)
6. 1
DE
SI
G
N
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), S1 = ON, and S2 = OFF (this
status is referred to as the initial status).
Resistance between VMP and VDD (RVMD)
The resistance between VMP and VDD (RVMD) is determined based on the current of the VMP pin (IVMD) after S1
and S2 are switched to OFF and ON, respectively, starting at the initial status.
S-8253A Series : RVMD = (V1 + V2) / IVMD
S-8253B Series : RVMD = (V1 + V2 + V3) / IVMD
Resistance between VMP and VSS (RVMS)
W
6. 2
NE
The resistance between VMP and VSS (RVMS) is determined based on the current of the VMP pin (IVMS) after V1 =
V2 = 1.8 V (S-8253A Series) or V1 = V2 = V3 = 1.8 V (S-8253B Series) are set starting at the initial status.
S-8253A Series : RVMS = (V1 + V2) / IVMS
S-8253B Series : RVMS = (V1 + V2 + V3) / IVMS
R
CTL Pin Input Voltage “H”
(Test Condition 7, Test Circuit 1)
FO
7.
7. 1
CTL Pin Input Voltage “H” (VCTLH)
D
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the
COP pin and DOP pin are low (this status is referred to as the initial status).
CTL Pin Input Voltage “L”
(Test condition 7, Test circuit 1)
MM
EN
8.
DE
The CTL pin input voltage “H” (VCTLH) is the voltage of V4 when the voltages of the COP pin and DOP pin are high
after the voltage of V4 has been gradually increased starting at the initial status.
Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0.35 V, and
the COP pin and DOP pin are high (this status is referred to as the initial status).
8. 1
CTL Pin Input Voltage “L” (VCTLL)
CTL Pin Current “H”, CTL Pin Current “L”
(Test Condition 8, Test Circuit 3)
9. 1
CTL Pin Current “H” (ICTLH), CTL Pin Current “L” (ICTLL)
RE
9.
CO
The CTL pin input voltage “L” (VCTLL) is the voltage of V4 when the voltages of the COP pin and DOP pin are low
after the voltage of V4 has been gradually increased starting at the initial status.
NO
T
The CTL pin current “H” (ICTLH) is the current that flows through the CTL pin when V1 = V2 = 3.5 V (S-8253A
Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), and S3 = ON, S4 = OFF. The CTL current “L” (ICTLL) is the
current that flows through the CTL pin when S3 = OFF and S4 = ON after that.
Seiko Instruments Inc.
13
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
VC1 Pin Current, VC2 Pin Current
(Test Condition 9, Test Circuit 3)
10. 1
N
10.
Rev.5.0_00
VC1 Pin Current (IVC1), VC2 Pin Current (IVC2)
11.
DE
SI
G
The VC1 pin current (IVC1) is the current that flows through the VC1 pin when V1 = V2 = 3.5 V (S-8253A Series),
V1 = V2 = V3 = 3.5 V (S-8253B Series), and S3 = OFF, S4 = ON. Similarly, the VC2 pin current (IVC2) is the
current that flows through the VC2 pin under these conditions (S-8253B Series only).
COP Pin Leakage Current, COP Pin Sink Current
(Test Condition 10, Test Circuit 4)
11. 1
COP Pin Leakage Current (ICOH)
11. 2
NE
W
The COP pin leakage current (ICOH) is the current that flows through the COP pin when V1 = V2 = 12 V (S-8253A
Series), V1 = V2 = V3 = 8 V (S-8253B Series), S6 = S7 = S8 = OFF, and S5 = ON.
COP Pin Sink Current (ICOL)
DOP Pin Source Current, DOP Pin Sink Current
(Test Condition 11, Test Circuit 4)
12. 1
FO
12.
R
The COP pin sink current (ICOL) is the current that flows through the COP pin when V1 = V2 = 3.5 V (S-8253A
Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V6 = 0.5 V, S5 = S7 = S8 = OFF, and S6 = ON.
DOP Pin Source Current (IDOH)
DOP Pin Sink Current (IDOL)
DE
12. 2
D
The DOP pin source current (IDOH) is the current that flows through the DOP pin when V1 = V2 = 1.8 V (S-8253A
Series), V1 = V2 = V3 = 1.8 V (S-8253B Series), V7 = 0.5 V, S5 = S6 = S8 = OFF, and S7 = ON.
13.
MM
EN
The DOP pin sink current (IDOL) is the current that flows through the DOP pin when V1 = V2 = 3.5 V (S-8253A
Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V8 = 0.5 V, S5 = S6 = S7 = OFF, and S8 = ON.
0 V Battery Charge Starting Battery Charger Voltage (Product with 0 V Battery Charge Function),
0 V Battery Charge Inhibition Battery Voltage (Product with 0 V Battery Charge Inhibition Function)
(Test Condition 12, Test Circuit 5)
13. 1
0 V Battery Charge Starting Battery Charger Voltage (V0CHA) (Product with 0 V Battery Charge
Function)
0 V Battery Charge Inhibition Battery Voltage (V0INH) (Product with 0 V Battery Charge Inhibition
Function)
RE
13. 2
CO
The COP pin voltage should be lower than V0CHA max. − 1 V when V1 = V2 = 0 V (S-8253A Series), V1 = V2 = V3
= 0 V (S-8253B Series), and V9 = VVMP = V0CHA max.
NO
T
The COP pin voltage should be higher than VVMP − 1 V when V1 = V2 = V0INH min. (S-8253A Series), V1 = V2 =
V3 = V0INH min. (S-8253B Series), and V9 = VVMP = 24 V.
14
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
S-8253A
S-8253B
V
V
1 DOP
V
VDD 8
1 DOP
V1
1 MΩ
2 COP
1 MΩ
VC1 7
V5
V5
V2
3 VMP
VC2 6
4 CTL
VSS 5
1 μF
Test Circuit 1
S-8253A
VSS 5
FO
4 CTL
4 CTL
VSS 5
A
1 μF
V3
S-8253B
VDD 8
V1
D
S2
2 COP
VC1 7
3 VMP
VC2 6
4 CTL
VSS 5
V2
1 μF
V3
A
DE
A
V2
S1
VC1 7
V2
S2
R
V1
VC2 6
VC2 6
1 DOP
VDD 8
S1
3 VMP
3 VMP
NE
Figure 5
A
VC1 7
V1
W
V4
2 COP
2 COP
1 μF
V4
1 DOP
VDD 8
DE
SI
G
V
N
Rev.5.0_00
MM
EN
Figure 6
Test Circuit 2
S-8253B
S-8253A
1 DOP
V1
S3
VC2 6
4 CTL
VSS 5
VDD 8
V1
S3
A
2 COP
VC1 7
A
3 VMP
VC2 6
A
4 CTL
VSS 5
V2
V2
1 μF
1 μF
A
V3
S4
Figure 7
Test Circuit 3
NO
T
S4
3 VMP
RE
A
VC1 7
CO
2 COP
1 DOP
VDD 8
Seiko Instruments Inc.
15
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
S5
S-8253A
S7
V7
S-8253B
V7
A
1 DOP
VDD 8
A
V8
V1
A
2 COP
1 DOP
V8
VC1 7
A
V2
V6
3 VMP
V6
VC2 6
1 μF
4 CTL
S8
R
VDD 8
VC1 7
1 MΩ
V2
VC2 6
1 μF
VSS 5
NO
T
RE
CO
MM
EN
Test Circuit 5
Seiko Instruments Inc.
V1
V2
V3
VSS 5
1 DOP
S-8253B
VDD 8
V1
2 COP
VC1 7
V2
3 VMP
VC2 6
1 μF
V9
Figure 9
16
VC2 6
1 MΩ
DE
4 CTL
V
D
V9
FO
V1
3 VMP
3 VMP
NE
Test Circuit 4
S-8253A
2 COP
VC1 7
4 CTL
S8
S6
Figure 8
V
2 COP
1 μF
VSS 5
1 DOP
VDD 8
W
S6
N
S7
DE
SI
G
S5
Rev.5.0_00
4 CTL
VSS 5
V3
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Operation
Normal Status
DE
SI
G
1.
Battery Protection IC Connection Example”.
N
Remark Refer to “
When all of the battery voltages are in the range from VDLn to VCUn and the discharge current is lower than the
specified value (the VMP pin voltage is higher than VDD − VIOV1), the charging and discharging FETs are turned on.
This condition is called the normal status, and in this condition charging and discharging can be carried out freely.
Caution
Overcharge Status
In this case,
W
2.
When the battery is connected for the first time, discharging may not be enabled.
short the VMP pin and VDD pin or connect the charger to restore the normal status.
Overdischarge Status
D
3.
FO
R
NE
When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP
pin becomes high impedance. Because the COP pin is pulled up to the EB+ pin voltage by an external resistor, the
charging FET is turned off to stop charging. This is called the overcharge status. The overcharge status is
released when one of the following two conditions holds.
(1) All battery voltages become VCLn or lower.
(2) All of the battery voltages are VCUn or lower, and the VMP pin voltage is VDD − VIOV1 or lower (since the
discharge current flows through the body diode of the charging FET immediately after discharging is started
when the charger is removed and a load is connected, the VMP pin voltage momentarily decreases by
approximately 0.6 V from the VDD pin voltage. The IC detects this voltage and releases the overcharging
status).
4.
Power-down Status
MM
EN
DE
When any one of the battery voltages becomes lower than VDLn and the state continues for tDL or longer, the DOP pin
voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is called the
overdischarging status. After discharging is stopped due to the overdischarge status, the S-8253A/B Series enters
the power-down status.
CO
When discharging has stopped due to the overdischarge status, the VMP pin is pulled down to the VSS level by the
RVMS resistor. When the VMP pin voltage is lower than Typ. 0.8 V, the S-8253A/B Series enters the power-down
status. In the power-down status, almost all the circuits of the S-8253A/B Series stop and the current consumption is
IPDN or lower. The conditions of each output pin are as follows.
(1) COP pin : High-Z
(2) DOP pin : VDD
RE
The power-down status is released when the following condition holds.
(1) The VMP pin voltage is Typ. 0.8 V or higher.
The overdischarging status is released when the following two conditions hold.
(1) All battery voltage is released at VDUn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the
VMP pin voltage is lower than VDD.
(2) All battery voltage is released at VDLn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the
VMP pin voltage is VDD or higher (when a charger is connected and VMP pin voltage is VDD or higher,
overdischarge hysteresis is released and electric discharge control FET is turned on at VDLn).
NO
T
Seiko Instruments Inc.
17
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
5.
Rev.5.0_00
Overcurrent Status
DE
SI
G
N
The S-8253A/B Series has three overcurrent detection levels (VIOV1, VIOV2, and VIOV3) and three overcurrent detection
delay times (tIOV1, tIOV2, and tIOV3) corresponding to each overcurrent detection level. When the discharging current
becomes higher than the specified value (the difference of the voltages of the VMP pin and VDD pin is greater than
VIOV1) and the state continues for tIOV1 or longer, the S-8253A/B Series enters the overcurrent status, in which the
DOP pin voltage becomes VDD level to turn off the discharging FET to stop discharging, the COP pin becomes high
impedance and is pulled up to the EB+ pin voltage to turn off the charging FET to stop charging, and the VMP pin is
pulled up to the VDD voltage by the internal resistor (RVMD). Operation of overcurrent detection levels 2, 3 (VIOV2,
VIOV3) and overcurrent detection delay times 2, 3 (tIOV2, tIOV3) are the same as for VIOV1 and tIOV1.
6.
The impedance that enables automatic restoration varies depending on the battery voltage and set
value of overcurrent detection voltage 1.
NE
Caution
W
The overcurrent status is released when the following condition holds.
(1) The VMP pin voltage is VDD − VIOV1 or higher because a charger is connected or the load is released.
0 V Battery Charge Function
When the VDD pin voltage is lower than the minimum value of VDSOP, the operation of the S8253A/B Series is not guaranteed.
NO
T
RE
CO
MM
EN
DE
Caution
D
FO
R
Regarding the charging of a self-discharged battery (0 V battery), the S-8253A/B Series has two functions from which
one should be selected.
(1) 0 V battery charging is allowed (0 V battery charging is available.)
When the charger voltage is higher than V0CHA, the 0 V battery can be charged.
(2) 0 V battery charging is prohibited (0 V battery charging is unavailable.)
When one of the battery voltages is lower than V0INH, the 0 V battery cannot be charged.
18
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
7.
Delay Circuit
The overcurrent detection delay time 2 (tIOV2) and overcurrent detection delay time 3 (tIOV3) start when the
overcurrent detection voltage 1 (VIOV1) is detected. As soon as the overcurrent detection voltage 2 (VIOV2)
or overcurrent detection voltage 3 (VIOV3) is detected over the detection delay time for overcurrent 2 (tIOV2)
or overcurrent 3 (tIOV3) after the detection of overcurrent 1 (VIOV1), the S-8253A/B turns the discharging
control FET off within tIOV2 or tIOV3 of each detection.
NE
W
Remark
280 μs
1.15 s
144 ms
9 ms
4.5 ms
DE
SI
G
(Example) Oscillator clock cycle (TCLK) :
Overcharge detection delay time (tCU) :
Overdischarge detection delay time (tDL) :
Overcurrent detection delay time 1 (tIOV1) :
Overcurrent detection delay time 2 (tIOV2) :
N
The following detection delay times are determined by dividing a clock of approximately 3.57 kHz by the counter.
VDD
DOP pin voltage
R
tD
FO
VSS
Overcurrent detection
delay time 2 (tIOV2)
VIOV1
VMP pin voltage
8.
MM
EN
DE
VIOV2
VIOV3
VSS
CTL Pin
Time
D
VDD
0 ≤ tD ≤ tIOV2
Time
Figure 10
CO
The S-8253A/B Series has a control pin for charge / discharge control and shortening the test time. The levels, “L”,
“H”, and “M”, of the voltage input to the CTL pin determine the status of the S-8253A/B Series: normal operation,
charge / discharge inhibition, or test time shortening. The CTL pin takes precedence over the battery protection
circuit. During normal use, short the CTL pin and VSS pin.
Table 10
Conditions Set by CTL Pin
NO
T
RE
CTL Pin Potential
Status of IC
Open
Charge / discharge inhibited status
High (VCTL ≥ VCTLH)
Charge / discharge inhibited status
Delay time-shortening status *1
Middle (VCTLL < VCTL < VCTLH)
Low (VCTLL ≥ VCTL)
Normal status
*1. In this status, delay times are shortened in 1 / 60 to 1 / 30 scale.
*2. The pin status is controlled by the voltage detection circuit.
Caution
1.
2.
3.
COP Pin
High-Z
High-Z
(*2)
(*2)
DOP Pin
VDD
VDD
(*2)
(*2)
If the potential of the CTL pin is middle, overcurrent detection voltage 1 (VIOV1) does not
operate.
If you use the middle potential of the CTL pin, contact SII marketing department.
Please note unexpected behavior might occur when electrical potential difference between the
CTL pin (“L” level) and VSS is generated through the external filter (RVSS and CVSS) as a result
of input voltage fluctuations.
Seiko Instruments Inc.
19
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Timing Chart
1.
Overcharge Detection and Overdischarge Detection
N
VHC
Battery
voltage
VDUn
VDLn
DE
SI
G
VCUn
VCLn
VHD
(n = 1 to 3)
W
VDD
NE
DOP
pin voltage
VSS
COP
pin voltage
DE
MM
EN
Load
connection
D
VEB+
VDD
VIOV1
VMP
pin voltage
0.8 V
VSS
Overcharge detection
delay time ( tCU )
Overdischarge detection
delay time ( tDL )
CO
Status*1
High-Z
FO
High-Z
VSS
Charger
connection
R
VEB+
RE
*1. < 1 > : Normal status
< 2 > : Overcharge status
< 3 > : Overdischarge status
< 4 > : Power-down status
NO
T
Remark The charger is assumed to charge with a constant current.
charger.
20
Figure 11
Seiko Instruments Inc.
VEB+ indicates the open voltage of the
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
2. Overcurrent Detection
DE
SI
G
Battery
voltage
N
VHC
VCUn
VCLn
VDUn
VDLn
VHD
(n = 1 to 3)
VDD
W
DOP
pin voltage
NE
VSS
VEB+
COP
pin voltage
DE
VSS
MM
EN
Overcurrent detection
delay time 1 ( tIOV1 )
Overcurrent detection
delay time 2 ( tIOV2 )
Overcurrent detection
delay time 3 ( tIOV3)
< 1 > : Normal status
< 2 > : Overcurrent status
The charger is assumed to charge with a constant current.
charger.
Figure 12
VEB+ indicates the open voltage of the
NO
T
RE
Remark
CO
*1.
High-Z
D
VDD
VIOV1
V
IOV2
VMP
V
pin voltage IOV3
Status*1
High-Z
FO
VSS
Load
connection
R
High-Z
Seiko Instruments Inc.
21
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Battery Protection IC Connection Example
N
S-8253A Series
EB+
RCOP
RDOP
S-8253A
RVMP
CTL
1 DOP
VDD 8
2 COP
VC1 7
3 VMP
VC2 6
4 CTL
VSS 5
RCTL
MM
EN
RDOP
RVMP
CTL
S-8253B
1 DOP
VDD 8
2 COP
VC1 7
3 VMP
VC2 6
4 CTL
VSS 5
Figure 14
NO
T
RE
CO
RCTL
EB−
22
RVSS
DE
RCOP
CVSS
D
S-8253B Series
EB+
RVC1
FO
Figure 13
Charging Discharging
FET
FET
CVC1
R
EB−
2.
DE
SI
G
Charging Discharging
FET
FET
W
1.
NE
Rev.5.0_00
Seiko Instruments Inc.
CVC1
RVC1
CVC2
CVSS
RVC2
RVSS
Symbol
RVC1
RVC2
RDOP
RCOP
RVMP
RCTL
RVSS
CVC1
CVC2
CVSS
Typ.
1
1
5.1
1
5.1
1
51
0.1
0.1
2.2
Range
0.51 to 1*1
0.51 to 1*1
2 to 10
0.1 to 1
1 to 10
1 to 100
5.1 to 51*1
0.1 to 0.47*1
0.1 to 0.47*1
1 to 10*1
Unit
kΩ
kΩ
kΩ
MΩ
kΩ
kΩ
Ω
μF
μF
μF
N
No.
1
2
3
4
5
6
7
8
9
10
Constants for External Components
DE
SI
G
Table 11
W
Rev.5.0_00
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
NE
*1. Please set up a filter constant to be RVSS × CVSS ≥ 51 μF • Ω and to be
RVC1 × CVC1 = RVC2 × CVC2 = RVSS × CVSS.
NO
T
RE
CO
MM
EN
DE
D
FO
R
Caution 1. The above constants may be changed without notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constant do
not guarantee proper operation. Perform through evaluation using the actual application to set the
constant.
Seiko Instruments Inc.
23
BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK
S-8253A/B Series
Rev.5.0_00
Precautions
Remark
If you are cautious about this condition, please consider to use the S-8253C/D Series.
N
• In case of designing a circuit by using the CTL pin, as seen in Figure 15, note that discharging may stop during connecting a battery
pack and the device.
Battery pack
NE
W
DE
SI
G
[Cause]
This is because the overcurrent detection voltage 3 (VIOV3) is detected due to the rush current which flows into the device while a
battery pack is in the delay time-shortening status.
[Mechanism]
As seen in Figure 15, before a battery pack is connected to the device, the battery pack may be in the charge / discharge
inhibited status in which the CTL pin is internally pulled-up. From this status, if connecting the battery pack to the device, the CTL
pin will be pulled-down in a time-constant C1 × (R1 + RPD) by a pull-down resistor in the device. If the CTL’s potential reaches
VCTLL