HI-3220
High Density 16Rx / 8Tx or 8Rx / 4Tx ARINC 429
Protocol IC with optional Integrated Line Receivers
FEATURES
The HI-3220, HI-3221, HI-3222 and HI-3223 have integrated
ARINC 429 line receivers, capable of RTCA/DO-160 level 3
lightning compliance with external 40kΩ resistors. HI-3225 and
HI-3226 utilize external line receivers, for example Holt’s octal
HI-8458 family. The HI-3222 and HI-3223 are 8-channel receive,
4-channel transmit options available in smaller package
footprints, with HI-3223 having the same slope control feature as
HI-3220. Transmit outputs interface directly to external HI-8592,
HI-8596, or integrated lightning protected HI-8597 ARINC 429
line drivers. All parts use a 40 MHz 4-wire SPI (Serial Peripheral
Interface) host connection.
HI-3220 and HI-3225 are available in an 80-pin PQFP package,
whereas HI-3221 and HI-3226 are available in a 72-pin 10mm x
10mm QFN package. The HI-3222 (8-ch. Rx, 4-ch. Tx) is
available in a very compact 48-pin 7mm x 7mm QFN.
APPLICATION
Controller
Memory
HI-3220/3221
(DS3220 Rev. K)
ARINC 429
8 x Transmit
ARINC 429
16 x Receive
CPU
· Sixteen ARINC 429 Receive channels with optional
integrated line Receivers
· Eight ARINC 429 Transmit channels
· 8-channel Rx, 4-channel Tx version available in
compact 48-pin 7mm x 7mm QFN
· 32 KB on chip user-configurable data storage
memory
· Programmable receive data filtering
· Option for programmable transmission schedulers
for periodic ARINC 429 broadcasting or CPU
directed transmission
· Auto-initialization feature allows power-on
configuration or independent operation without CPU
· 40 MHZ SPI CPU interface
· Transmitter rate and tri-state control outputs
· Supports 100kbs / 50kbs / 12.5kbs data rates
PIN CONFIGURATION
SLP7
TX3N
TX3P
MODE0/ECS
EMISO
TX7N
TX7P
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
TX6N
TX6P
SCANSHFT
SCANEN
TX2N
TX2P
SLP6
The ARINC 429 buses may operate independently - the IC can
be programmed to automatically re-format, re-label, re-packetize
and re-transmit data from ARINC 429 receive buses to ARINC
429 transmit buses. Alternatively, a host CPU can send and
receive data on multiple buses. 32KB of on-board memory allows
received data to be logically organized and automatically
updated as new ARINC 429 labels are received via ARINC 429
label mailboxes. A 64 message deep Receive FIFO is also
available for each receive channel. Each transmitter has the
option to independently enable a programmable scheduler on
the ARINC 429 bus, or to have the CPU directly send data. An
optional auto-initialization feature allows configuration information to be up-loaded from an external EEPROM on reset to
facilitate rapid start-up or operation without a host CPU.
· Fully compliant to ARINC 429 Specification
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
The HI-3220 from Holt Integrated Circuits is a family of single
chip CMOS high density application data management ICs
capable of managing, storing and forwarding avionics data
messages between sixteen ARINC 429 receive channels and
eight ARINC 429 transmit channels. Options for eight receive
and four transmit channels are also available in a compact, cost
effective 7mm x 7mm QFN package footprint.
SLP3
ARX8P-40
ARX8N-40
ARX0P-40
ARX0N-40
ARX9P-40
ARX9N-40
ARX1P-40
ARX1N-40
VDD
GND
ARX2P-40
ARX2N-40
ARX10P-40
ARX10N-40
ARX3P-40
ARX3N-40
ARX11P-40
ARX11N-40
SLP0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
HI-3220PQx
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SLP2
ARX15N-40
ARX15P-40
ARX7N-40
ARX7P-40
ARX14N-40
ARX14P-40
ARX6N-40
ARX6P-40
GND
VDD
ARX5N-40
ARX5P-40
ARX13N-40
ARX13P-40
ARX4N-40
ARX4P-40
ARX12N-40
ARX12P-40
SLP1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GENERAL DESCRIPTION
SLP4
TX0P
TX0N
HCS
HMOSI
TX4P
TX4N
HSCLK
HMISO
VDD
GND
MRST
RUN
TX5P
TX5N
INT
ACK
TX1P
TX1N
SLP5
April 2021
80 - Pin Plastic Quad Flat Pack (PQFP)
04/21
HI-3220
BLOCK DIAGRAM
Host CPU
ARINC 429
RECEIVE DATA
MEMORY 0
1K x 8
RECEIVER 0
Interrupt Handler
32 x 32
Transmit FIFO
ARINC 429
Descriptor Table 0
FILTER
TABLE 0
ARINC 429
TRANSMIT
SCHEDULER 0
Message 64
“
“
“
Message 2
Message 1
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
.............
CHANNEL 15
ECS
ESCLK
EMOSI
EMISO
EEPROM
SPI
GND
TRANSMIT TIMER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
64 x 32 FIFO
LABEL
FILTER
TRANSMITTER 0
Auto-Initialization
EEPROM
PRODUCT OPTIONS
PART NUMBER
PACKAGE
LINE RECEIVERS
TRANSMIT CHANNELS
HI-3220
HI-3221
HI-3222
HI-3223
HI-3225
HI-3226
80-pin QFP
72-pin QFN
48-pin QFN
52-pin QFP or 64-pin QFN
80-pin QFP
72-pin QFN
16 on-chip
16 on-chip
8 on-chip
8 on-chip
16 External
16 External
8 Transmitters & SLP7:0 outputs
8 Transmitters. No SLP7:0 outputs
4 Transmitters. No SLP outputs
4 Transmitters & SLP3:0 outputs
8 Transmitters & SLP7:0 outputs
8 Transmitters. No SLP7:0 outputs
HOLT INTEGRATED CIRCUITS
2
8 x ARINC 429 Transmit Buses
16 x ARINC 429 Integrated Line Receivers (HI-3220/3221 ONLY)
SPI
ACK
INT
HCS
HSCLK
HMOSI
HMISO
READY
RUN
MRST
MODE2:0
VDD
HI-3220
PIN DESCRIPTIONS (HI-3220, HI-3221, HI-3222, HI-3223)
Signal
Function
ACK
INT
ARX0N-40
ARX0P-40
ARX1N-40
ARX1P-40
ARX2N-40
ARX2P-40
ARX3N-40
ARX3P-40
ARX4N-40
ARX4P-40
ARX5N-40
ARX5P-40
ARX6N-40
ARX6P-40
ARX7N-40
ARX7P-40
ARX8N-40
ARX8P-40
ARX9N-40
ARX9P-40
ARX10N-40
ARX10P-40
ARX11N-40
ARX11P-40
ARX12N-40
ARX12P-40
ARX13N-40
ARX13P-40
ARX14N-40
ARX14P-40
ARX15N-40
ARX15P-40
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
TX4N
TX4P
TX5N
TX5P
TX6N
TX6P
TX7N
TX7P
SLP0
SLP1
SLP2
SLP3
SLP4
SLP5
SLP6
SLP7
INPUT
OUTPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
ANALOG INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Description
Internal
Pull-Up/Down
Interrupt Acknowledge. Active low.
Interrupt. Active low, open-drain.
ARINC 429 Receive bus negative line input for channel 0. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 0. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 1. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 1. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 2. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 2. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 3. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 3. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 4. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 4. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 5. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 5. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 6. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 6. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 7. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 7. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 8. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 8. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 9. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 9. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 10. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 10. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 11. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 11. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 12. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 12. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 13. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 13. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 14. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 14. Requires external 40KOhm resistor.
ARINC 429 Receive bus negative line input for channel 15. Requires external 40KOhm resistor.
ARINC 429 Receive bus positive line input for channel 15. Requires external 40KOhm resistor.
ARINC 429 Tx channel 0 negative data output to line driver
ARINC 429 Tx channel 0 positive data output to line driver
ARINC 429 Tx channel 1 negative data output to line driver
ARINC 429 Tx channel 1 positive data output to line driver
ARINC 429 Tx channel 2 negative data output to line driver
ARINC 429 Tx channel 2 positive data output to line driver
ARINC 429 Tx channel 3 negative data output to line driver
ARINC 429 Tx channel 3 positive data output to line driver
ARINC 429 Tx channel 4 negative data output to line driver
ARINC 429 Tx channel 4 positive data output to line driver
ARINC 429 Tx channel 5 negative data output to line driver
ARINC 429 Tx channel 5 positive data output to line driver
ARINC 429 Tx channel 6 positive data output to line driver
ARINC 429 Tx channel 6 positive data output to line driver
ARINC 429 Tx channel 7 positive data output to line driver
ARINC 429 Tx channel 7 positive data output to line driver
ARINC 429 Tx channel 0 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
ARINC 429 Tx channel 1 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
ARINC 429 Tx channel 2 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
ARINC 429 Tx channel 3 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
ARINC 429 Tx channel 4 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
ARINC 429 Tx channel 5 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
ARINC 429 Tx channel 6 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
ARINC 429 Tx channel 7 slew rate control (see Tx Control Register) (HI-3220 and HI-3223).
HOLT INTEGRATED CIRCUITS
3
Pull-Up
Pull-Up
HI-3220
PIN DESCRIPTIONS (HI-3220, HI-3221, HI-3222, HI-3223) continued
Signal
Function
MODE0/ECS
EMISO
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
HCS
HMISO
HMOSI
HSCLK
MCLK
MRST
READY
RUN
SCANEN
SCANSHFT
I/O
INPUT
I/O
I/O
POWER
POWER
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
Description
Internal
Pull-Up/Down
MODE0 configuration input sampled at reset / SPI chip select output for initialization EEPROM
SPI serial data input from auto-inialization EEPROM
MODE1 configuration input sampled at reset / SPI serial data output to initialization EEPROM
MODE2 configuration input sampled at reset / SPI clock for auto-initialization EEPROM
Chip 0V supply. All four pins must be connected.
3.3V power supply. All four pins must be powered.
Host chip select. Data is shifted into HMOSI and out of HMISO when HCS is low
Host CPU SPI interface serial data output
Host CPU SPI interface serial data input
Host SPI Clock. Data is shifted into or out of the SPI interface using HSCLK
Master and reference clock for ARINC 429 bus bit timing. 50MHz +/- 0.1%
Master Reset to HI-322X Active Low. 225 ns minimum pulse width.
READY goes high when post-RESET initialization is complete
Master enable signal for ARINC 429 transmit schedulers
Factory test only. Connect to GND.
Factory test only. Connect to GND.
See Note below
Pull-Down
See Note below
See Note below
Pull-Up
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
NOTE: When not using an external EEPROM, the Mode0, Mode1 and Mode2 pins must be connected to either VDD or GND through a
suitable pull-up or pull-down resistor (1K - 50K), depending on the desired power up mode. These pins do not have internal pull-up or
pull-down resistors and need to be connected to a known state to prevent possible initialization of an un-intended mode.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
SLP7
TX3N
TX3P
MODE0/ECS
EMISO
TX7N
TX7P
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
TX6N
TX6P
SCANSHFT
SCANEN
TX2N
TX2P
SLP6
PIN CONFIGURATIONS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
HI-3220PQx
SLP2
ARX15N-40
ARX15P-40
ARX7N-40
ARX7P-40
ARX14N-40
ARX14P-40
ARX6N-40
ARX6P-40
GND
VDD
ARX5N-40
ARX5P-40
ARX13N-40
ARX13P-40
ARX4N-40
ARX4P-40
ARX12N-40
ARX12P-40
SLP1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SLP4
TX0P
TX0N
HCS
HMOSI
TX4P
TX4N
HSCLK
HMISO
VDD
GND
MRST
RUN
TX5P
TX5N
INT
ACK
TX1P
TX1N
SLP5
SLP3
ARX8P-40
ARX8N-40
ARX0P-40
ARX0N-40
ARX9P-40
ARX9N-40
ARX1P-40
ARX1N-40
VDD
GND
ARX2P-40
ARX2N-40
ARX10P-40
ARX10N-40
ARX3P-40
ARX3N-40
ARX11P-40
ARX11N-40
SLP0
80 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
4
HI-3220
HI-3221PCx
ARX15N-40
ARX15P-40
ARX7N-40
ARX7P-40
ARX14N-40
ARX14P-40
ARX6N-40
ARX6P-40
GND
VDD
ARX5N-40
ARX5P-40
ARX13N-40
ARX13P-40
ARX4N-40
ARX4P-40
ARX12N-40
ARX12P-40
TX3N 1
ARX0P-40 2
ARX0N-40 3
ARX1P-40 4
ARX1N-40 5
VDD 6
GND 7
ARX2P-40 8
ARX2N-40 9
ARX3P-40 10
ARX3N-40 11
TX0P 12
HI-3222PCx
36
35
34
33
32
31
30
29
28
27
26
25
TX2P
ARX7N-40
ARX7P-40
ARX6N-40
ARX6P-40
GND
VDD
ARX5N-40
ARX5P-40
ARX4N-40
ARX4P-40
TX1N
13
14
15
16
17
18
19
20
21
22
23
24
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
TX0N
HCS
HMOSI
HSCLK
HMISO
VDD
GND
MRST
RUN
INT
ACK
TX1P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TX0P
TX0N
HCS
HMOSI
TX4P
TX4N
HSCLK
HMISO
VDD
GND
MRST
RUN
TX5P
TX5N
INT
ACK
TX1P
TX1N
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ARX8P-40
ARX8N-40
ARX0P-40
ARX0N-40
ARX9P-40
ARX9N-40
ARX1P-40
ARX1N-40
VDD
GND
ARX2P-40
ARX2N-40
ARX10P-40
ARX10N-40
ARX3P-40
ARX3N-40
ARX11P-40
ARX11N-40
48
47
46
45
44
43
42
41
40
39
38
37
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
TX3P
MODE0/ECS
EMISO
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
SCANSHFT
SCANEN
TX2N
TX3N
TX3P
MODE0/ECS
EMISO
TX7N
TX7P
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
TX6N
TX6P
SCANSHFT
SCANEN
TX2N
TX2P
PIN CONFIGURATIONS (continued)
48 - Pin Plastic QFN (Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
52
51
50
49
48
47
46
45
44
43
42
41
40
TX3N
TX3P
MODE0/ECS
EMISO
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
SCANSHFT
SCANEN
TX2N
TX2P
-
TX3P
MODE0/ECS
EMISO
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
SCANSHFT
SCANEN
TX2N
TX2P
72 - Pin Plastic QFN (Top View)
39
38
37
36
35
34
33
32
31
30
29
28
27
SLP3
ARX0P-40
ARX0N-40
ARX1P-40
ARX1N-40
VDD
GND
ARX2P-40
ARX2N-40
ARX3P-40
ARX3N-40
SLP0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HI-3223PCx
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
52 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
5
TX0P
TX0N
HCS
HMOSI
HSCLK
HMISO
VDD
GND
MRST
RUN
INT
ACK
TX1P
TX1N
-
14
15
16
17
18
19
20
21
22
23
24
25
26
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HI-3223PQx
SLP2
ARX7N-40
ARX7P-40
ARX6N-40
ARX6P-40
GND
VDD
ARX5N-40
ARX5P-40
ARX4N-40
ARX4P-40
SLP1
TX1N
TX0P
TX0N
HCS
HMOSI
HSCLK
HMISO
VDD
GND
MRST
RUN
INT
ACK
TX1P
TX3N 1
SLP3 2
ARX0P-40 3
ARX0N-40 4
ARX1P-40 5
ARX1N-40 6
VDD 7
GND 8
ARX2P-40 9
ARX2N-40 10
ARX3P-40 11
ARX3N-40 12
SLP0 13
“-” denotes “Not Connected internally”
64 - Pin Plastic QFN (Top View)
SLP2
ARX7N-40
ARX7P-40
ARX6N-40
ARX6P-40
GND
VDD
ARX5N-40
ARX5P-40
ARX4N-40
ARX4P-40
SLP1
HI-3220
PIN DESCRIPTIONS (HI-3225, HI-3226)
Signal
Function
ACK
INT
RX0N
RX0P
RX1N
RX1P
RX2N
RX2P
RX3N
RX3P
RX4N
RX4P
RX5N
RX5P
RX6N
RX6P
RX7N
RX7P
RX8N
RX8P
RX9N
RX9P
RX10N
RX10P
RX11N
RX11P
RX12N
RX12P
RX13N
RX13P
RX14N
RX14P
RX15N
RX15P
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
TX4N
TX4P
TX5N
TX5P
TX6N
TX6P
TX7N
TX7P
SLP0
SLP1
SLP2
SLP3
SLP4
SLP5
SLP6
SLP7
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Description
Internal
Pull-Up/Down
Interrupt Acknowledge. Active low.
Interrupt. Active low, open-drain.
ARINC 429 Digital input from line receiver negative signal for channel 0.
ARINC 429 Digital input from line receiver positive signal for channel 0.
ARINC 429 Digital input from line receiver negative signal for channel 1.
ARINC 429 Digital input from line receiver positive signal for channel 1.
ARINC 429 Digital input from line receiver negative signal for channel 2.
ARINC 429 Digital input from line receiver positive signal for channel 2.
ARINC 429 Digital input from line receiver negative signal for channel 3.
ARINC 429 Digital input from line receiver positive signal for channel 3.
ARINC 429 Digital input from line receiver negative signal for channel 4.
ARINC 429 Digital input from line receiver positive signal for channel 4.
ARINC 429 Digital input from line receiver negative signal for channel 5.
ARINC 429 Digital input from line receiver positive signal for channel 5.
ARINC 429 Digital input from line receiver negative signal for channel 6.
ARINC 429 Digital input from line receiver positive signal for channel 6.
ARINC 429 Digital input from line receiver negative signal for channel 7.
ARINC 429 Digital input from line receiver positive signal for channel 7.
ARINC 429 Digital input from line receiver negative signal for channel 8.
ARINC 429 Digital input from line receiver positive signal for channel 8.
ARINC 429 Digital input from line receiver negative signal for channel 9.
ARINC 429 Digital input from line receiver positive signal for channel 9.
ARINC 429 Digital input from line receiver negative signal for channel 10.
ARINC 429 Digital input from line receiver positive signal for channel 10.
ARINC 429 Digital input from line receiver negative signal for channel 11.
ARINC 429 Digital input from line receiver positive signal for channel 11.
ARINC 429 Digital input from line receiver negative signal for channel 12.
ARINC 429 Digital input from line receiver positive signal for channel 12.
ARINC 429 Digital input from line receiver negative signal for channel 13.
ARINC 429 Digital input from line receiver positive signal for channel 13.
ARINC 429 Digital input from line receiver negative signal for channel 14.
ARINC 429 Digital input from line receiver positive signal for channel 14.
ARINC 429 Digital input from line receiver negative signal for channel 15.
ARINC 429 Digital input from line receiver positive signal for channel 15.
ARINC 429 Tx channel 0 negative data output to line driver
ARINC 429 Tx channel 0 positive data output to line driver
ARINC 429 Tx channel 1 negative data output to line driver
ARINC 429 Tx channel 1 positive data output to line driver
ARINC 429 Tx channel 2 negative data output to line driver
ARINC 429 Tx channel 2 positive data output to line driver
ARINC 429 Tx channel 3 negative data output to line driver
ARINC 429 Tx channel 3 positive data output to line driver
ARINC 429 Tx channel 4 negative data output to line driver
ARINC 429 Tx channel 4 positive data output to line driver
ARINC 429 Tx channel 5 negative data output to line driver
ARINC 429 Tx channel 5 positive data output to line driver
ARINC 429 Tx channel 6 positive data output to line driver
ARINC 429 Tx channel 6 positive data output to line driver
ARINC 429 Tx channel 7 positive data output to line driver
ARINC 429 Tx channel 7 positive data output to line driver
ARINC 429 Tx channel 0 slew rate control (see Tx Control Register) (HI-3225).
ARINC 429 Tx channel 1 slew rate control (see Tx Control Register) (HI-3225).
ARINC 429 Tx channel 2 slew rate control (see Tx Control Register) (HI-3225).
ARINC 429 Tx channel 3 slew rate control (see Tx Control Register) (HI-3225).
ARINC 429 Tx channel 4 slew rate control (see Tx Control Register) (HI-3225).
ARINC 429 Tx channel 5 slew rate control (see Tx Control Register) (HI-3225).
ARINC 429 Tx channel 6 slew rate control (see Tx Control Register) (HI-3225).
ARINC 429 Tx channel 7 slew rate control (see Tx Control Register) (HI-3225).
HOLT INTEGRATED CIRCUITS
6
Pull-Up
Pull-Up
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
HI-3220
PIN DESCRIPTIONS (HI-3225, HI-3226) continued
Signal
Function
MODE0/ECS
EMISO
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
HCS
HMISO
HMOSI
HSCLK
MCLK
MRST
READY
RUN
SCANEN
SCANSHFT
I/O
INPUT
I/O
I/O
POWER
POWER
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
Description
Internal
Pull-Up/Down
MODE0 configuration input sampled at reset / SPI chip select output for EEPROM initialization
SPI serial data input from auto-inialization EEPROM
MODE1 configuration input sampled at reset / SPI serial data output for EEPROM initialization
MODE2 configuration input sampled at reset / SPI clock for EEPROM auto-initialization
Chip 0V supply. All four pins must be connected.
3.3V power supply. All four pins must be powered.
Host chip select. Data is shifted into HMOSI and out of HMISO when HCS is low
Host CPU SPI interface serial data output
Host CPU SPI interface serial data input
Host SPI Clock. Data is shifted into or out of the SPI interface using HSCLK
Master and reference clock for ARINC 429 bus bit timing. 50 MHZ +/- 0.1%
Master Reset to HI-322X Active Low. 225 ns minimum pulse width.
READY goes high when post-RESET initialization is complete
Master enable signal for ARINC 429 transmit schedulers
Factory test only. Connect to GND.
Factory test only. Connect to GND.
See Note below
Pull-Down
See Note below
See Note below
Pull-Up
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
Pull-Down
NOTE: When not using an external EEPROM, the Mode0, Mode1 and Mode2 pins must be connected to either VDD or GND through a
suitable pull-up or pull-down resistor (1K - 50K), depending on the desired power up mode. These pins do not have internal pull-up or
pull-down resistors and need to be connected to a known state to prevent possible initialization of an un-intended mode.
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
TX3N
TX3P
MODE0/ECS
EMISO
TX7N
TX7P
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
TX6N
TX6P
SCANSHFT
SCANEN
TX2N
TX2P
SLP7
TX3N
TX3P
MODE0/ECS
EMISO
TX7N
TX7P
MODE1/EMOSI
MODE2/ESCLK
GND
VDD
MCLK
READY
TX6N
TX6P
SCANSHFT
SCANEN
TX2N
TX2P
SLP6
PIN CONFIGURATIONS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RX8P
RX8N
RX0P
RX0N
RX9P
RX9N
RX1P
RX1N
VDD
GND
RX2P
RX2N
RX10P
RX10N
RX3P
RX3N
RX11P
RX11N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
HI-3226PCx
80 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
7
TX0P
TX0N
HCS
HMOSI
TX4P
TX4N
HSCLK
HMISO
VDD
GND
MRST
RUN
TX5P
TX5N
INT
ACK
TX1P
TX1N
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
HI-3225PQx
SLP2
RX15N
RX15P
RX7N
RX7P
RX14N
RX14P
RX6N
RX6P
GND
VDD
RX5N
RX5P
RX13N
RX13P
RX4N
RX4P
RX12N
RX12P
SLP1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SLP4
TX0P
TX0N
HCS
HMOSI
TX4P
TX4N
HSCLK
HMISO
VDD
GND
MRST
RUN
TX5P
TX5N
INT
ACK
TX1P
TX1N
SLP5
SLP3
RX8P
RX8N
RX0P
RX0N
RX9P
RX9N
RX1P
RX1N
VDD
GND
RX2P
RX2N
RX10P
RX10N
RX3P
RX3N
RX11P
RX11N
SLP0
72 - Pin Plastic QFN (Top View)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
RX15N
RX15P
RX7N
RX7P
RX14N
RX14P
RX6N
RX6P
GND
VDD
RX5N
RX5P
RX13N
RX13P
RX4N
RX4P
RX12N
RX12P
HI-3220
APPLICATION OVERVIEW
The HI-3220 is a flexible device for managing ARINC 429
communications and data storage in many avionics
applications. The device architecture centers around a
32K x 8 static RAM used for data storage, data filtering
tables and table-driven transmission schedulers. Once
configured, the device can operate autonomously without
a host CPU, negating the need for software development
or DO-178 certification. Configuration data may be
uploaded into the device from an external EEPROM,
following system reset.
The device supports up to sixteen ARINC 429 receive
channels. Analog line receivers are on-chip (HI-3220, HI3221 and HI-3222), or off-chip (HI-3225 and HI-3226).
Received data is stored in on-chip RAM organized by
channel number and label. The data table continually
updates as new labels arrive. Programmable interrupts
and filters alert the host subsystem to labels of interest.
Each ARINC 429 receive channel also includes a 64
message deep FIFO allowing selected label data to be
queued for subsequent host access.
The HI-3220 supports up to eight independent ARINC
429 transmit channels. Transmission may be controlled
entirely by an external CPU, or autonomously by
programming one or more of the eight on-chip ARINC
429 transmit schedulers. These allow periodic
transmission to occur without CPU. Source data for
transmission may be selected from RAM based tables of
constants and / or from the received channel data.
Powerful options exist for constructing ARINC 429 labels
as well as controlling their timing and conditional
transmission.
Even when running under the control of schedulers, the
host CPU may insert new labels for transmission at will.
The following examples show five possible configurations
of how the HI-3220 may be used:
Example 1. ARINC 429 Data reception using on-chip RAM
16 x ARINC 429
Receive Buses
RECEIVER 15
Channel 15, Label FF
“
“
“
Channel 15, Label 01
Channel 15, Label 00
RECEIVER 14
Channel 14, Label FF
“
“
“
Channel 14, Label 01
Channel 14, Label 00
RECEIVER 13
Channel 13, Label FF
“
“
“
Channel 13, Label 01
Channel 13, Label 00
RECEIVE
INTERRUPT
TABLE
INT
ACK
Host CPU
RECEIVERS 12-3
RECEIVER 2
RECEIVER 1
RECEIVER 0
Channels 12-3, Label FF
“
“
“
Channels 12-3, Label 01
Channels 12-3, Label 00
HCSB
HSCLK
HMOSI
HMISO
SPI
Channel 2, Label FF
“
“
“
Channel 2, Label 01
Channel 2, Label 00
Channel 1, Label FF
“
“
“
Channel 1, Label 01
Channel 1, Label 00
Channel 0, Label FF
“
“
“
Channel 0, Label 01
Channel 0, Label 00
16K x 8 RAM
(of 32K available)
HOLT INTEGRATED CIRCUITS
8
HI-3220
HI-3220
Example 2. ARINC 429 Data reception using on-chip filters and FIFOs
FILTER
TABLE 0
16 x ARINC 429
Receive Buses
LABEL
FILTER
RECEIVER 0
Message 64
“
“
“
Message 2
Message 1
64 x 32 FIFO
HCSB
HSCLK
HMOSI
HMISO
SPI
FIFO STATUS
Host CPU
FIFO THRESHOLD
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
...............
...............
CHANNEL 14
CHANNEL 15
ARINC 429
RECEIVE FIFO
INTERRUPT
CONTROL
INT
ACK
HI-3220
Example 3. ARINC 429 Data transmission directly from CPU
32 x 32 FIFOs
Host CPU
HCS
HSCLK
HMOSI
HMISO
FIFO 0
TRANSMITTER 0
FIFO 1
TRANSMITTER 1
FIFO 2
TRANSMITTER 2
FIFO 3
TRANSMITTER 3
FIFO 4
TRANSMITTER 4
FIFO 5
TRANSMITTER 5
FIFO 6
TRANSMITTER 6
FIFO 7
TRANSMITTER 7
8 x ARINC 429
Transmit Buses
SPI
HI-3220
Example 4. ARINC 429 Data transmission using on-chip schedulers
TRANSMITTER 0
Descriptor Table 0
Host CPU
HCS
HSCLK
HMOSI
HMISO
TRANSMIT
SCHEDULER 0
8 x ARINC 429
Transmit Buses
SPI
Descriptor Table 1
TRANSMIT TIMER
CHANNEL 0
Descriptor Tables 2-6
CHANNEL 1
..............
CHANNEL 7
Auto-Initialization
EEPROM
ECS
ESCLK
EMOSI
EMISO
EEPROM
SPI
Descriptor Table 7
RAM
HOLT INTEGRATED CIRCUITS
9
HI-3220
HI-3220
Example 5. Autonomous ARINC 429 Data Concentrator / Repeater
RECEIVER 15
RECEIVER 14
Channel 14, Label FF
“
Channel 14, Label 01
Channel 14, Label 00
RECEIVER 13
Channel 13, Label FF
“
Channel 13, Label 01
Channel 13, Label 00
RECEIVER 12
Channel 12, Label FF
“
Channel 12, Label 01
Channel 12, Label 00
RECEIVER 11
Channel 11, Label FF
“
Channel 11, Label 01
Channel 11, Label 00
RECEIVER 10
Channel 10, Label FF
“
Channel 10, Label 01
Channel 10, Label 00
RECEIVER 9
Channel 9, Label FF
“
Channel 9, Label 01
Channel 9, Label 00
RECEIVER 8
Channel 8, Label FF
“
Channel 8, Label 01
Channel 8, Label 00
RECEIVER 7
Channel 7, Label FF
“
Channel 7, Label 01
Channel 7, Label 00
RECEIVER 6
Channel 6, Label FF
“
Channel 6, Label 01
Channel 6, Label 00
RECEIVER 5
Channel 5, Label FF
“
Channel 5, Label 01
Channel 5, Label 00
RECEIVER 4
Channel 4, Label FF
“
Channel 4, Label 01
Channel 4, Label 00
RECEIVER 3
Channel 3, Label FF
“
Channel 3, Label 01
Channel 3, Label 00
RECEIVER 2
Channel 2, Label FF
“
Channel 2, Label 01
Channel 2, Label 00
RECEIVER 1
Channel 1, Label FF
“
Channel 1, Label 01
Channel 1, Label 00
RECEIVER 0
Channel 0, Label FF
“
Channel 0, Label 01
Channel 0, Label 00
TRANSMIT
SCHEDULER 6
TRANSMITTER 7
TRANSMIT TIMER
Descriptor Table 6
TRANSMIT
SCHEDULER 6
TRANSMITTER 6
TRANSMIT TIMER
Descriptor Table 5
TRANSMIT
SCHEDULER 5
TRANSMITTER 5
TRANSMIT TIMER
Descriptor Table 4
TRANSMIT
SCHEDULER 4
TRANSMITTER 4
TRANSMIT TIMER
Descriptor Table 3
TRANSMIT
SCHEDULER 3
TRANSMITTER 3
TRANSMIT TIMER
Descriptor Table 2
TRANSMIT
SCHEDULER 2
TRANSMITTER 2
TRANSMIT TIMER
Descriptor Table 1
TRANSMIT
SCHEDULER 1
TRANSMITTER 1
TRANSMIT TIMER
Descriptor Table 0
TRANSMIT
SCHEDULER 0
TRANSMITTER 0
TRANSMIT TIMER
EEPROM
SPI
HI-3220
ECS
ESCLK
EMOSI
EMISO
16 x ARINC 429
Receive Buses
Descriptor Table 7
Channel 15, Label FF
“
Channel 15, Label 01
Channel 15, Label 00
Auto-Initialization
EEPROM
HOLT INTEGRATED CIRCUITS
10
8 x ARINC 429
Transmit Buses
HI-3220
HI-3220 MEMORY MAP
0x8XXX
Configuration Registers
0x8000
0x7FFF
0x7000
0x6FFF
ARINC 429 Receive FIFO
ARINC 429 Transmit FIFO
0x6C00
0x6BFF
ARINC 429 RX Interrupt Map
0x6A00
0x69FF
ARINC 429 RX FIFO Enable Map
0x6800
0x67FF
0x6400
0x63FF
0x6000
0x5FFF
0x5C00
0x5BFF
0x5800
0x57FF
0x5400
0x53FF
0x5000
0x4FFF
0x4800
0x47FF
0x4000
0x3FFF
Tx7 Transmit Schedule Table
Tx6 Transmit Schedule Table
Tx5 Transmit Schedule Table
Tx4 Transmit Schedule Table
Tx3 Transmit Schedule Table
Tx2 Transmit Schedule Table
Tx1 Transmit Schedule Table
Tx0 Transmit Schedule Table
ARINC 429
Receive
Data
Shaded Area
User - Programmed
Non-shaded Area
Data Storage
0x0000
HOLT INTEGRATED CIRCUITS
11
HI-3220
HI-3220 REGISTER MAP
ADDRESS R/W
REGISTER
MNEMONIC
MCR
MCR
MSR
0x8000
0x8001
0x8002
0x8003
0x8004
0x8005
0x8006
0x8007
0x8008
0x8009
0x800A
0x800B
0x800C
0x800D
0x800E
0x800F
0x8010
0x8011
0x8012
0x8013
0x8014
0x8015
0x8016
0x8017
0x8018
0x8019
0x801A
0x801B
0x801C
0x801D
0x801E
0x801F
R/W
R
R
R
R*
R
R*
R
R*
R
R*
R*
R*
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
MASTER CONTROL REGISTER
MASTER CONTROL REGISTER
MASTER STATUS REGISTER
Not used
PENDING INTERRUPT REGISTER
Not used
RECEIVE PENDING INTERRUPT LOW
Not used
RECEIVE PENDING INTERRUPT HIGH
Not used
PENDING INTERRUPT REGISTER
RECEIVE PENDING INTERRUPT LOW
RECEIVE PENDING INTERRUPT HIGH
RECEIVE FIFO THRESHOLD FLAG (LOW)
RECEIVE FIFO THRESHOLD FLAG (HIGH)
TRANSMITTER FIFO THRESHOLD FLAGS
RECEIVE INTERRUPT ADDRESS 0
RECEIVE INTERRUPT ADDRESS 1
RECEIVE INTERRUPT ADDRESS 2
RECEIVE INTERRUPT ADDRESS 3
RECEIVE INTERRUPT ADDRESS 4
RECEIVE INTERRUPT ADDRESS 5
RECEIVE INTERRUPT ADDRESS 6
RECEIVE INTERRUPT ADDRESS 7
RECEIVE INTERRUPT ADDRESS 8
RECEIVE INTERRUPT ADDRESS 9
RECEIVE INTERRUPT ADDRESS 10
RECEIVE INTERRUPT ADDRESS 11
RECEIVE INTERRUPT ADDRESS 12
RECEIVE INTERRUPT ADDRESS 13
RECEIVE INTERRUPT ADDRESS 14
RECEIVE INTERRUPT ADDRESS 15
0x8020
0x8021
0x8022
0x8023
0x8024
0x8025
0x8026
0x8027
0x8028
0x8029
0x802A
0x802B
0x802C
0x802D
0x802E
0x802F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RECEIVE CONTROL REGISTER 0
RECEIVE CONTROL REGISTER 1
RECEIVE CONTROL REGISTER 2
RECEIVE CONTROL REGISTER 3
RECEIVE CONTROL REGISTER 4
RECEIVE CONTROL REGISTER 5
RECEIVE CONTROL REGISTER 6
RECEIVE CONTROL REGISTER 7
RECEIVE CONTROL REGISTER 8
RECEIVE CONTROL REGISTER 9
RECEIVE CONTROL REGISTER 10
RECEIVE CONTROL REGISTER 11
RECEIVE CONTROL REGISTER 12
RECEIVE CONTROL REGISTER 13
RECEIVE CONTROL REGISTER 14
RECEIVE CONTROL REGISTER 15
Fast Access Registers
Memory mapped register access only
PIR
DESCRIPTION
HI-3220 global configuration (write address)
HI-3220 global configuration (read address)
Indicates HI-3220 current status
Indicates Interrupt type
RPIRL
Defines channel(7-0) with pending Interrupt
RPIRH
Defines channel(15-8) with pending Interrupt
PIR
RPIRL
RPIRH
FTFL
FTFH
TFR
IAR0
IAR1
IAR2
IAR3
IAR4
IAR5
IAR6
IAR7
IAR8
IAR9
IAR10
IAR11
IAR12
IAR13
IAR14
IAR15
Indicates Interrupt type
Defines channel(7-0) with pending Interrupt
Defines channel(15-8) with pending Interrupt
Shows which Rx FIFOs hold > (thresh) words
Shows which Rx FIFOs hold > (thresh) words
Shows which Tx FIFOs hold < (thresh) words
ARINC 429 Interrupt Vector channel 0
ARINC 429 Interrupt Vector channel 1
ARINC 429 Interrupt Vector channel 2
ARINC 429 Interrupt Vector channel 3
ARINC 429 Interrupt Vector channel 4
ARINC 429 Interrupt Vector channel 5
ARINC 429 Interrupt Vector channel 6
ARINC 429 Interrupt Vector channel 7
ARINC 429 Interrupt Vector channel 8
ARINC 429 Interrupt Vector channel 9
ARINC 429 Interrupt Vector channel 10
ARINC 429 Interrupt Vector channel 11
ARINC 429 Interrupt Vector channel 12
ARINC 429 Interrupt Vector channel 13
ARINC 429 Interrupt Vector channel 14
ARINC 429 Interrupt Vector channel 15
RXC0
RXC1
RXC2
RXC3
RXC4
RXC5
RXC6
RXC7
RXC8
RXC9
RXC10
RXC11
RXC12
RXC13
RXC14
RXC15
Configures ARINC 429 receive channel 0
Configures ARINC 429 receive channel 1
Configures ARINC 429 receive channel 2
Configures ARINC 429 receive channel 3
Configures ARINC 429 receive channel 4
Configures ARINC 429 receive channel 5
Configures ARINC 429 receive channel 6
Configures ARINC 429 receive channel 7
Configures ARINC 429 receive channel 8
Configures ARINC 429 receive channel 9
Configures ARINC 429 receive channel 10
Configures ARINC 429 receive channel 11
Configures ARINC 429 receive channel 12
Configures ARINC 429 receive channel 13
Configures ARINC 429 receive channel 14
Configures ARINC 429 receive channel 15
* Register is cleared when read (auto clear)
HOLT INTEGRATED CIRCUITS
12
HI-3220
ADDRESS R/W
0x8030
0x8031
0x8032
0x8033
0x8034
0x8035
0x8036
0x8037
0x8038
0x8039
0x803A
0x803B
0x803C
0x803D
0x803E
0x803F
0x8040
0x8041
0x8042
0x8043
0x8044
0x8045
0x8046
0x8047
0x8048
0x8049
0x804A
0x804B
0x804C
0x804D
0x804E
0x804F
0x8050
0x8051
0x8052
0x8053
0x8054
0x8055
0x8056
0x8057
0x8058
0x8059
0x805A
0x805B
0x805C
0x805D
0x805E
0x805F
REGISTER
R/W
TRANSMIT CONTROL REGISTER 0
R/W
TRANSMIT CONTROL REGISTER 1
R/W
TRANSMIT CONTROL REGISTER 2
R/W
TRANSMIT CONTROL REGISTER 3
R/W
TRANSMIT CONTROL REGISTER 4
R/W
TRANSMIT CONTROL REGISTER 5
R/W
TRANSMIT CONTROL REGISTER 6
R/W
TRANSMIT CONTROL REGISTER 7
R/W
TRANSMIT REPETITION RATE 0
R/W
TRANSMIT REPETITION RATE 1
R/W
TRANSMIT REPETITION RATE 2
R/W
TRANSMIT REPETITION RATE 3
R/W
TRANSMIT REPETITION RATE 4
R/W
TRANSMIT REPETITION RATE 5
R/W
TRANSMIT REPETITION RATE 6
R/W
TRANSMIT REPETITION RATE 7
R
TRANSMIT SEQUENCE POINTER 0
R
TRANSMIT SEQUENCE POINTER 1
R
TRANSMIT SEQUENCE POINTER 2
R
TRANSMIT SEQUENCE POINTER 3
R
TRANSMIT SEQUENCE POINTER 4
R
TRANSMIT SEQUENCE POINTER 5
R
TRANSMIT SEQUENCE POINTER 6
R
TRANSMIT SEQUENCE POINTER 7
R
Not used
R/W
LOOPBACK
R/W PENDING INTERRUPT ENABLE REGISTER
R/W
RECEIVE INTERRUPT ENABLE (LOW)
R/W
RECEIVE INTERRUPT ENABLE (HIGH)
R/W RECEIVE FIFO INTERRUPT ENABLE (LOW)
R/W RECEIVE FIFO INTERRUPT ENABLE (HIGH)
R/W
TRANSMIT FIFO INTERRUPT ENABLE
R/W
RECEIVE FIFO THRESHOLD VALUE 0
R/W
RECEIVE FIFO THRESHOLD VALUE 1
R/W
RECEIVE FIFO THRESHOLD VALUE 2
R/W
RECEIVE FIFO THRESHOLD VALUE 3
R/W
RECEIVE FIFO THRESHOLD VALUE 4
R/W
RECEIVE FIFO THRESHOLD VALUE 5
R/W
RECEIVE FIFO THRESHOLD VALUE 6
R/W
RECEIVE FIFO THRESHOLD VALUE 7
R/W
RECEIVE FIFO THRESHOLD VALUE 8
R/W
RECEIVE FIFO THRESHOLD VALUE 9
R/W
RECEIVE FIFO THRESHOLD VALUE 10
R/W
RECEIVE FIFO THRESHOLD VALUE 11
R/W
RECEIVE FIFO THRESHOLD VALUE 12
R/W
RECEIVE FIFO THRESHOLD VALUE 13
R/W
RECEIVE FIFO THRESHOLD VALUE 14
R/W
RECEIVE FIFO THRESHOLD VALUE 15
MNEMONIC
DESCRIPTION
TXC0
TXC1
TXC2
TXC3
TXC4
TXC5
TXC6
TXC7
TXRR0
TXRR1
TXRR2
TXRR3
TXRR4
TXRR5
TXRR6
TXRR7
TXSP0
TXSP1
TXSP2
TXSP3
TXSP4
TXSP5
TXSP6
TXSP7
Configures ARINC 429 transmit channel 0
Configures ARINC 429 transmit channel 1
Configures ARINC 429 transmit channel 2
Configures ARINC 429 transmit channel 3
Configures ARINC 429 transmit channel 4
Configures ARINC 429 transmit channel 5
Configures ARINC 429 transmit channel 6
Configures ARINC 429 transmit channel 7
Sets sequence repeat time for ARINC 429 TX0
Sets sequence repeat time for ARINC 429 TX1
Sets sequence repeat time for ARINC 429 TX2
Sets sequence repeat time for ARINC 429 Tx3
Sets sequence repeat time for ARINC 429 Tx4
Sets sequence repeat time for ARINC 429 Tx5
Sets sequence repeat time for ARINC 429 Tx6
Sets sequence repeat time for ARINC 429 Tx7
Current address of ARINC transmit sequence 0
Current address of ARINC transmit sequence 1
Current address of ARINC transmit sequence 2
Current address of ARINC transmit sequence 3
Current address of ARINC transmit sequence 4
Current address of ARINC transmit sequence 5
Current address of ARINC transmit sequence 6
Current address of ARINC transmit sequence 7
LOOP
PIER
RIEL
RIEH
FIEL
FIEH
TFIE
FTV0
FTV1
FTV2
FTV3
FTV4
FTV5
FTV6
FTV7
FTV8
FTV9
FTV10
FTV11
FTV12
FTV13
FTV14
FTV15
Sets Loopback channels
Enables Interrupts on INT pin
Enables Interrupts (channels 7-0)
Enables Interrupts (channels 15-8)
Enables Receive Interrupts (channels 7-0)
Enables Receive Interrupts (channels 15-8)
Enables Transmit Interrupts
Sets flag value for ARINC 429 Receive FIFO 0
Sets flag value for ARINC 429 Receive FIFO 1
Sets flag value for ARINC 429 Receive FIFO 2
Sets flag value for ARINC 429 Receive FIFO 3
Sets flag value for ARINC 429 Receive FIFO 4
Sets flag value for ARINC 429 Receive FIFO 5
Sets flag value for ARINC 429 Receive FIFO 6
Sets flag value for ARINC 429 Receive FIFO 7
Sets flag value for ARINC 429 Receive FIFO 8
Sets flag value for ARINC 429 Receive FIFO 9
Sets flag value for ARINC 429 Receive FIFO 10
Sets flag value for ARINC 429 Receive FIFO 11
Sets flag value for ARINC 429 Receive FIFO 12
Sets flag value for ARINC 429 Receive FIFO 13
Sets flag value for ARINC 429 Receive FIFO 14
Sets flag value for ARINC 429 Receive FIFO 15
HOLT INTEGRATED CIRCUITS
13
HI-3220
ADDRESS R/W
REGISTER
MNEMONIC
DESCRIPTION
0x8060
0x8061
0x8062
0x8063
0x8064
0x8065
0x8066
0x8067
0x8068
0x8069
0x806A
0x806B
0x806C
0x806D
0x806E
0x806F
0x8070
0x8071
0x8072
0x8073
0x8074
0x8075
0x8076
0x8077
0x8078
0x8079
0x807A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
TRANSMIT FIFO THRESHOLD VALUE 0
TRANSMIT FIFO THRESHOLD VALUE 1
TRANSMIT FIFO THRESHOLD VALUE 2
TRANSMIT FIFO THRESHOLD VALUE 3
TRANSMIT FIFO THRESHOLD VALUE 4
TRANSMIT FIFO THRESHOLD VALUE 5
TRANSMIT FIFO THRESHOLD VALUE 6
TRANSMIT FIFO THRESHOLD VALUE 7
RX FIFO COUNT 0
RX FIFO COUNT 1
RX FIFO COUNT 2
RX FIFO COUNT 3
RX FIFO COUNT 4
RX FIFO COUNT 5
RX FIFO COUNT 6
RX FIFO COUNT 7
RX FIFO COUNT 8
RX FIFO COUNT 9
RX FIFO COUNT 10
RX FIFO COUNT 11
RX FIFO COUNT 12
RX FIFO COUNT 13
RX FIFO COUNT 14
RX FIFO COUNT 15
BIST CONTROL/STATUS
BIST FAIL ADDRESS [7:0]
BIST FAIL ADDRESS [15:8]
TFTV0
TFTV1
TFTV2
TFTV3
TFTV4
TFTV5
TFTV6
TFTV7
RFC0
RFC1
RFC2
RFC3
RFC4
RFC5
RFC6
RFC7
RFC8
RFC9
RFC10
RFC11
RFC12
RFC13
RFC14
RFC15
BISTS
BISTFL
BISTFH
0x807B
0x807C
0x807D
0x807E
0x 807F
0x8080
0x8081
0x8082
0x8083
0x8084
0x8085
0x8086
0x8087
R
R
R
R/W
R/W
R
R
R
R
R
R
R
R
AUTO-INIT FAIL LS ADDRESS [7:0]
AUTO-INIT FAIL MS ADDRESS [15:8]
Not used
WATCHDOG CHANNEL MASK [7:0]
WATCHDOG TIMER REGISTER [7:0]
TX FIFO COUNT 0
TX FIFO COUNT 1
TX FIFO COUNT 2
TX FIFO COUNT 3
TX FIFO COUNT 4
TX FIFO COUNT 5
TX FIFO COUNT 6
TX FIFO COUNT 7
AIFL
AIFH
Sets flag value for ARINC 429 Transmit FIFO 0
Sets flag value for ARINC 429 Transmit FIFO 1
Sets flag value for ARINC 429 Transmit FIFO 2
Sets flag value for ARINC 429 Transmit FIFO 3
Sets flag value for ARINC 429 Transmit FIFO 4
Sets flag value for ARINC 429 Transmit FIFO 5
Sets flag value for ARINC 429 Transmit FIFO 6
Sets flag value for ARINC 429 Transmit FIFO 7
Current FIFO message count Receiver 0
Current FIFO message count Receiver 1
Current FIFO message count Receiver 2
Current FIFO message count Receiver 3
Current FIFO message count Receiver 4
Current FIFO message count Receiver 5
Current FIFO message count Receiver 6
Current FIFO message count Receiver 7
Current FIFO message count Receiver 8
Current FIFO message count Receiver 9
Current FIFO message count Receiver 10
Current FIFO message count Receiver 11
Current FIFO message count Receiver 12
Current FIFO message count Receiver 13
Current FIFO message count Receiver 14
Current FIFO message count Receiver 15
Built-In Self-Test
Low-order failing BIST memory address
High-order failing BIST memory address
and Mode bits
Auto-initialization fail address (low-byte)
Auto-initialization fail address (high byte)
WCM
WTR
TFC0
TFC1
TFC2
TFC3
TFC4
TFC5
TFC6
TFC7
1=masked, 0=active
Defines watchdog time-out period
Current FIFO message count Transmitter 0
Current FIFO message count Transmitter 1
Current FIFO message count Transmitter 2
Current FIFO message count Transmitter 3
Current FIFO message count Transmitter 4
Current FIFO message count Transmitter 5
Current FIFO message count Transmitter 6
Current FIFO message count Transmitter 7
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14
HI-3220
HI-3220 SYSTEM CONFIGURATION
Starting at memory address 0x8000, the HI-3220
contains a set of registers that are used to configure the
device.
The configuration registers are divided into three
categories, as follows;
1. HI-3220 global configuration
2. ARINC 429 Receive channel configuration
3. ARINC 429 Transmit channel configuration
The user needs only to program the HI-3220
configuration registers to completely define the full
system operation.
HI-3220 Global Configuration
A4
AF
29
A4 RX
29
TX
LI
TX P
M
TX SK
7O
TX PT
D
L2
56
The following registers define the HI-3220 top-level configuration:
MASTER CONTROL REGISTER
(Address 0x8000 - read/write, 0x8001 - read)
7 6
MSB
X
X
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
A429RX
R/W
0
This bit must be set to a “1” to allow the HI-3220 to receive ARINC 429 data on any of the
sixteen ARINC 429 receive channels. If set to a zero, the HI-3220 will not respond to any
ARINC 429 receive bus, regardless of the state of the ARINC 429 Receive channel Control
Registers.
6
A429TX
R/W
0
This bit must be set to a “1” to allow the HI-3220 to transmit ARINC 429 data on any of the eight
channels. If set to a zero, the HI-3220 will not output ARINC 429 data and the ARINC 429
transmit sequencers will remain in their reset state. Completes the current TX message*
before entering the reset state.
5
-
R/W
0
Not Used
4
-
R/W
0
Not Used
3
AFLIP
R/W
0
When set to a “1”, this bit switches the bit order of the ARINC 429 label byte in both receive and
transmit channels. (See ARINC 429 Bit Ordering section)
2
TXMSK
R/W
0
When set to a “1”, this bit prevents the external transmission of self-test loop-back data for any
transmitter when set to loopback mode.
1
TX7OPT
R/W
0
Defines the meaning of Receive Status bit 7 in every ARINC 429 receive data block. When
TX7OPT = “1”, Status bit 7 is NEWHOST. When TX7OPT =”0”, Status bit 7 is NEWTX7. See
ARINC receive data block description for details.
0
TXDL256
R/W
0
When TXDL256 is “0” transmitter 0 and transmitter 1 descriptor length is 128.
When TXDL256 is “1” transmitter 0 and transmitter 1 descriptor length is 256.
* A message is defined as one ARINC 429 32-bit message. A frame is defined as multiple messages programmed in a Transmit
scheduler.
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15
HI-3220
HI-3220 Operational Status Information
R
EA
AC DY
T
SA IVE
F
R E
AM
PR BU
O S
AU GC Y
TO Y
IN
IT
The Master Status Register may be read at any time to determine the current operational state of the HI-3220:
X
MASTER STATUS REGISTER
(Address 0x8002)
Bit Name
7
-
R/W
R
X
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
0
Not used
6
-
R
0
Not Used
5
READY
R
0
This bit is high, when the READY output pin is high, indicating that the part is able to accept and
respond to host CPU SPI commands
4
ACTIVE
R
0
This bit is high after the RUN pin is asserted and the HI-3220 is in normal operating mode.
3
SAFE
R
0
This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or autoinitialization fail.
2
RAM BUSY
R
0
This is high during the time the RAM Integrity Check is running and RAM is clearing
1
PROGCY
R
0
Indicates that the HI-3220 is currently in the EEPROM programming cycle. Note that READY
stays low until the cycle is complete.
0
AUTOINIT
R
0
The HI-3220 is currently loading internal memory, registers and look-up tables from the Autoinitialization EEPROM
HOLT INTEGRATED CIRCUITS
16
HI-3220
ARINC 429 RECEIVE OPERATION
The HI-3220 can receive ARINC 429 messages from up to sixteen ARINC 429 receive buses. Analog line receivers are
included on-chip for HI-3220, HI-3221 and HI-3222. Each receiver input line requires only an external 40 kOhm resistor to meet
lightning protection DO-160 level 3. The HI-3225 and HI-3226 have digital receiver inputs and are used with off-chip
ARINC 429 line receivers.
ARINC 429 Receive Channel Configuration
RECEIVE CONTROL REGISTER 0 - 15
(Address 0x8020 - 0x802F)
PA
R
D ITY
EC E
N
SD OD
10 ER
SD
9
R
AT
50 E
KO
PT
EN
AB
LE
Each of the sixteen possible ARINC 429 Receive channels is configured using its own Control Register. Register address
0x8020 controls ARINC 429 Receive channel #0, register address 0x8021 controls channel #1 and so on.
X
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
ENABLE
R/W
0
This bit must be set to a “1” to enable ARINC 429 data reception on this channel.
6
-
R/W
0
Not used
5
PARITYEN
R/W
0
When this bit is a one, the 32nd received ARINC bit is overwritten with a parity flag. The flag bit
is set to a zero when the received ARINC word, including its parity bit has an odd number of
ones. When PARITYEN is a zero, all 32-bits are received without parity checking.
4
DECODER
R/W
0
When DECODER is a “1”, bits 9 and 10 of ARINC 429 words received on this channel must
match the SD9 and SD10 bits in the register. ARINC words received that do not match the SD
conditions are ignored.
3
SD10
R/W
0
If DECODER is set to a “1”, then this bit must match the received ARINC word bit 10 for the
word to be accepted.
2
SD9
R/W
0
If DECODER is set to a “1”, then this bit must match the received ARINC word bit 9 for the
word to be accepted.
1
RATE
R/W
0
Selects the ARINC 429 bit rate for the ARINC 429 receive channel. A “0” selects high-speed
(100Kb/s) and a “1” selects low-speed (12.5Kb/s). (See 50KOPT bit for non-standard 50kb/s
high-speed operation)
0
50KOPT
R/W
0
When set to a “1”, the RATE bit is ignored and ARINC 429 data rate is set to 50 Kb/s
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17
HI-3220
ARINC 429 Received Data Management
The HI-3220 supports up to sixteen ARINC 429 receive
buses using on-chip receivers to handle the protocol
validation. The sixteen Receive Control Registers, RXC0 15, define the characteristics of each receive channel.
Enable Register, the INT output pin is asserted. The label
number of the ARINC 429 message causing the interrupt
is loaded into that channel’s Receive Interrupt Address
Register (IAR0 - IAR15).
The ARINC 429 receive function of the HI-3220 is activated by setting the A429RX bit in the Master Control
Register.
Because the ARINC Receive Memory is organized by
label value, it is not necessary to store the received label
value (first eight bits of the ARINC message) in the
memory. Instead, the first byte is used to store a status
byte.
When an ARINC 429 message is received by the HI-3220
on any bus, it is checked for protocol compliance. Messages with incorrect encoding are rejected. NOTE:
Messages with incorrect parity will be stored.
The HI-3220 allocates 16K bytes of on-chip memory for
storing ARINC 429 received data. The memory is organized by channel number and ARINC 429 label value.
Four bytes of memory are dedicated to each channel /
label to store the 32-bit ARINC 429 message.
A look-up table is used to enable an interrupt on receipt of a
new ARINC 429 message. Look-up table bit positions preloaded by the user with a “1” will cause an Interrupt to be
generated.
When a message is received that triggers an Interrupt, that
channel’s Interrupt bit is set in the Receive Pending
Interrupt Register. If this bit is set in the Receive Interrupt
The eight active bits of the status byte are set to “1” when a
new ARINC word is stored in the memory. These bits flag
the ARINC word as new when the location is interrogated
by the host CPU or any of the seven ARINC 429 transmit
schedulers. (Note: Transmitter 7 operates differently from
the other 7 transmitters. The corresponding “New” bit in
the receive status word may be selected between new
data for Tx7 or new data for Host CPU as defined by the
global TX7OPT bit in the Master control Register.)
The ARINC 429 Receive memory is not filtered so messages will load unconditionally when received if the
channel is enabled in the Receive Control Register.
Message blocks are single buffered so the host should
read the message before a potential overwrite.
ARINC 429 Received Data Memory Organization
0x3FFF
Block 4096
Channel 15, Label FF
0x3FFC
“
“
0x0400
Block 256
Channel 0, Label FF
0x03FC
“
“
0x000B
Block 3
Channel 0, Label 02
0x0008
0x0007
Block 2
Channel 0, Label 01
0x0003
ARINC data byte 4
0x0002
ARINC data byte 3
Block 1
Channel 0, Label 00
0x0001
ARINC data byte 2
0x0000
Status Byte
0x0004
0x0003
0x0000
Etc.
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18
HI-3220
ARINC 429 Received Data Interrupt Look-Up Table
0x6BFF
0x6BE0
0x6A3F
0x6A20
0x6A1F
0x6A00
Label = 0xF8
Label = 0xFF
Interrupt Look-Up Table
Channel 15
Label = 0x08
Interrupt Look-Up Table
Channel 1
Label = 0x0F
Interrupt Look-Up Table
Channel 0
7
6
5
4
3
2
1
0
Label = 0x00
Label = 0x07
Label = 0x01
N
N
EW
H
EW OS
N TX T/T
EW 6 X
7
N TX
EW 5
N TX
EW 4
N TX
EW 3
N TX
EW 2
N TX
EW 1
TX
0
ARINC 429 Received Data Status Byte Definition
STATUS BYTE
7 6
MSB
Bit Name
5
4
3
2
1
0
LSB
R/W Default Description
7 NEWHOST/TX7 R/W
0
The meaning of this bit depends upon the setting of TX7OPT bit in the Master Control Register:
When TX7OPT is a ‘”1”, this bit is set when a new ARINC 429 word is received and stored in
this block. It is reset when the host CPU executes SPI instruction 0xC8 or 0xD0 to read the
block.
When TX7OPT is a “0”, this bit is set when a new ARINC 429 word is received and stored in this
block. It is reset when the ARINC 429 Transmit scheduler #7 reads any bytes from the block.
6 NEWTX6
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #6 reads any bytes from the block.
5 NEWTX5
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #5 reads any bytes from the block.
4 NEWTX4
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #4 reads any bytes from the block.
3 NEWTX3
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #3 reads any bytes from the block.
2 NEWTX2
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
theARINC 429 Transmit scheduler #2 reads any bytes from the block.
1 NEWTX1
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
theARINC 429 Transmit scheduler #1 reads any bytes from the block.
0 NEWTX0
R/W
0
This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when
the ARINC 429 Transmit scheduler #0 reads any bytes from the block.
HOLT INTEGRATED CIRCUITS
19
HI-3220
ARINC 429 Received Data Log FIFO
Sixteen FIFOs that are each 64 messages deep.
The FIFOs are empty following reset. All three status
registers are cleared. For each channel, a user-defined
RECEIVE FIFO THRESHOLD VALUE register defines the
point where the RECEIVE FIFO THRESHOLD FLAG bit is
set. That occurs when the number of words in the FIFO
exceed the threshold value. Once a FIFO is full, (i.e.
contains 64 messages), a received message will be written
to the FIFO and the oldest message lost, maintaining a
FIFO full count of 64.
A 4K x 8 block of memory located between 0x7000 and
0x7FFF is reserved for a set of sixteen ARINC 429 received
data FIFOs. There is one FIFO for each ARINC 429
received data channel. Each FIFO can hold up to 64 ARINC
429 32-bit messages.
A look-up table driven filter defines which ARINC 429
messages are stored in each FIFO. The look-up table is
initialized by the user with a “1” for each bit position
corresponding to a selected channel / label combination.
The look-up table is located at memory address 0x6800.
The user may generate an Interrupt by enabling one the
FIFO status register bits to assert the FLAG bit in the
Pending Interrupt Register. Receive Control Register bit 6
enables the triggering of the FLAG interrupt.
When a new ARINC 429 message is received that meets
the programmed conditions for acceptance (Enable lookup table bit = “1”), it is written into the channel’s Receive
Data FIFO. The contents of the FIFO may be read by the
host CPU using dedicated FIFO read SPI Instructions.
The FIFO feature is particularly useful if the application
wishes to accumulate sequential ARINC 429 messages of
the same label value before reading them. The regular
ARINC 429 receive data memory will, of course, overwrite
messages of the same label value if a new message is
received before the host CPU extracts the data.
The status of each channel’s FIFOs is monitored by a FIFO
status register: RECEIVE FIFO THRESHOLD FLAG. Each
bit of the register reflects the current status of each FIFO.
ARINC 429 Received FIFO Data Enable Look-Up Table
0x69FF
0x69E0
0x683F
0x6820
0x681F
0x6800
Label = 0xF8
Label = 0xFF
Filter Look-Up Table
Channel 15
Label = 0x08
Filter-Look-Up Table
Channel 1
Label = 0x0F
Filter Look-Up Table
Channel 0
7
6
5
4
3
2
1
0
Label = 0x00
Label = 0x07
Label = 0x01
ARINC 429
received
message
Message 1 (32-bits)
Message 2 (32-bits)
ARINC 429 Received Data FIFO (x16)
Data read by
Host CPU
SPI Instruction
FIFO THRESHOLD
FTFn
FLAGn
Select
FFSOn
From
Other 15
Channels
0 - 64 Messages (32-bits)
HOLT INTEGRATED CIRCUITS
20
}
OR
PIR
FLAG
HI-3220
Bit
Name
15:0
FTF[15:0]
R/W
R
FT
F7
FT
F6
FT
F
FT 5
F4
FT
F3
FT
F2
FT
F1
FT
F0
RECEIVE FIFO THRESHOLD REGISTER HIGH / LOW
(Address 0x800E, 0x800D)
FT
F1
FT 5
F1
FT 4
F
FT 13
F1
FT 2
F1
FT 1
F1
FT 0
F9
FT
F8
ARINC 429 Received Data FIFO Registers
7 6
MSB
7 6
MSB
5
4
3
2
1
0
LSB
5
4
3
2
1
0
LSB
Default
Description
0
Bits are set to “1” if the corresponding channel’s receive FIFO contains >
threshold number of ARINC 429 messages.
Receive FIFO Threshold Value Registers
Each Receiver has its own Receive FIFO Threshold Register
Threshold
FIFO THRESHOLD VALUE n
(Address 0x8050 - 0x805F)
Threshold Value
Default = 0x00
0
7 6
MSB
5
4
3
2
1
0
LSB
Description
0000000
Threshold flag is set if at least 1 message is in FIFO (FIFO is not empty) - Default
0000001
Threshold flag is set if more than one message is in the FIFO
0000010
Threshold flag is set if more than two messages are in the FIFO
0000011
Threshold flag is set if more than three messages are in the FIFO
0010000
Threshold flag is set if more than sixteen messages are in the FIFO
1111111
Threshold flag is set if 64 messages are in the FIFO (FIFO is full)
5
4
3
2
E6
FI
E7
E2
FO
E
FI 1
E0
0
LSB
E3
1
FI
2
E4
3
FI
4
E5
5
FI
7 6
MSB
FI
RECEIVE FIFO THRESHOLD REGISTER HIGH / LOW
(Address 0x804E, 0x804D)
FI
FI
E1
FI 5
E1
FI 4
E1
FI 3
E1
FI 2
E1
FI 1
E1
FI 0
E9
FI
E8
Receive FIFO Interrupt Enable
7 6
MSB
1
Bit
Name
R/W
Default
Description
15:0
FIE[15:0]
R/W
0
Interrupts are enabled for receive channels where the corresponding bit is set.
Receive FIFO Count Registers
RECEIVE FIFO COUNT(0-15)
(Address 0x8068 - 0x8077)
Count
Default = 0x00
0
7 6
MSB
5
4
3
2
1
0
LSB
Bit
Name
R/W
Default
Description
7:0
RFCn[7:0]
R/W
0
Reads number of words held in Receive FIFO
FIFOs may be emptied by writing 0xA5 to this register.
HOLT INTEGRATED CIRCUITS
21
0
LSB
HI-3220
ARINC 429 Loop-back Self-Test
The HI-3220 includes an ARINC 429 loop-back feature,
which allows users to exercise the ARINC 429 transmit and
receive channels for self-test purposes. The ARINC 429
Loop-Back register, LOOP, defines which receiver
channels are in loop-back mode. When a “1” is
programmed in the LOOP bit position for a receiver pair,
then their ARINC 429 bus connection to the external pins is
broken and instead the input is connected to one of the
eight ARINC 429 transmit channels. Transmit channel 0 is
connected to receive channels 0 and 1, transmit channel 1
is connected to receive channels 2 and 3, and so on.
LO
O
LO P7
O
LO P6
O
LO P5
O
LO P4
O
LO P3
O
LO P2
O
LO P1
O
P0
When in loop-back mode, incoming ARINC 429 messages
are ignored by the HI-3220. When running in loop-back
mode the ARINC 429 transmit pins may be disabled by
setting the TXMSK bit high in the Master Control Register.
This prevents test messages from being output to the
external ARINC 429 transmit buses.
SELF-TEST LOOPBACK
(Address 0x8049)
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
LOOP7
R/W
0
This bit is set to “1” to loop-back transmit channel 7 to receivers 14 and 15
6
LOOP6
R/W
0
This bit is set to “1” to loop-back transmit channel 6 to receivers 12 and 13
5
LOOP5
R/W
0
This bit is set to “1” to loop-back transmit channel 5 to receivers 10 and 11
4
LOOP4
R/W
0
This bit is set to “1” to loop-back transmit channel 4 to receivers 8 and 9
3
LOOP3
R/W
0
This bit is set to “1” to loop-back transmit channel 3 to receivers 6 and 7
2
LOOP2
R/W
0
This bit is set to “1” to loop-back transmit channel 2 to receivers 4 and 5
1
LOOP1
R/W
0
This bit is set to “1” to loop-back transmit channel 1 to receivers 2 and 3
0
LOOP0
R/W
0
This bit is set to “1” to loop-back transmit channel 0 to receivers 0 and 1
HOLT INTEGRATED CIRCUITS
22
HI-3220
ARINC 429 Bit ordering
ARINC 429 messages consist of a 32-bit sequence as
shown below. The first eight bits that appear on the ARINC
429 bus are the label byte. The next twenty three bits
comprise a data field which presents data in a variety of
formats defined in the ARINC 429 specification. The last bit
transmitted is an odd parity bit.
The ARINC 429 specifies the MSB of the label as ARINC bit
1. Conversely, the data field MSB is bit 31. So the bit
significance of the label byte and data fields are opposite.
The HI-3220 may be programmed to “flip” the bit ordering of
the label byte as soon as it is received and immediately prior
to transmission. This is accomplished by setting the FLIP bit
to a “1” in the Master Control Register. Note that once the
label byte has been flipped, the HI-3220 handles the flipped
data byte “post-flip” for the purpose of label interrupt
matching, filtering and storage.
The HI-3220 stores the received message as four bytes.
The bytes are stored in memory in little-endian order. That
is to say, the label byte (or status byte) is stored at the
lowest memory address, the byte representing received
bits 9 through 16 is stored at the next address, the byte
representing bits 17 through 24 at the next address and the
byte representing bits 25 though 32 at the highest address.
ARINC 429 Message as received / transmitted on the ARINC 429 serial bus
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16
8
17 18 19 20 21 22 23 24
ARINC 429 Message as stored in HI-3220 memory
Byte 3
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
Byte 2
24 23 22 21 20 19 18 17
24 23 22 21 20 19 18 17
Byte 1
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
1
2
3
4
5
FLIP = “0”
6
IT
25 26 27 28 29 30 31 32
time
Byte 0
Y
MSB
DATA
SD
SD
I
LSB
PA
R
LSB
LABEL
I
MSB
7
8
8
7
6
5
4
3
FLIP = “1”
HOLT INTEGRATED CIRCUITS
23
2
1
HI-3220
ARINC 429 TRANSMIT OPERATION
The HI-3220 has up to eight on-board ARINC 429 transmit channels which directly drive ARINC 429 differential line drivers
such as the Holt HI-8596. ARINC 429 words may be written to the transmitters either directly, using an SPI instruction
through a transmit FIFO, or be generated automatically using the eight ARINC 429 message schedulers.
ARINC 429 Transmit Channel Configuration
R
U
N
PR / S
E TO
PA SC P
R AL
EV ITY E
E /D
SK N / AT
IP OD A
D
TR
IS
R TA
AT T
E
50 E
KO
PT
Each of the eight available ARINC 429 Transmit channels is configured using its own register. Register address 0x8030
controls ARINC 429 Transmit channel #0, register address 0x8031 controls channel #1 and so on. The TXCn
registers may be written or read at any time.
TRANSMIT CONTROL REGISTER 0 - 7
(Address 0x8030 - 0x8037)
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
RUN / STOP
R/W
0
When zero, transmission from this ARINC 429 transmit channel is suspended after the
currently transmitting frame of messages is sent. When this bit is taken high, transmission
starts at the beginning of the descriptor table for this channel. The RUN bit can be used for onetime frame transmission (see page 25).
6
PRESCALE
R/W
0
This bit sets the LSB value for this transmit channel’s Repetition Rate Counter. A “0” set the
LSB value to 10 ms, and a “1” selects 1 ms.
5
PARITY / DATA R/W
0
When this bit is a one, the 32nd transmitted ARINC bit is overwritten with a parity flag. When
this bit is a zero, all 32-bits are transmitted as data.
4
EVEN / ODD
R/W
0
When PARITY / DATA is a “1”, this bit defines whether th 32nd transmitted bit is set for Even or
Odd Parity. A “1” selects even parity and a “0” selects odd parity.
3
SKIP
R/W
0
When set to a “1”, instructs the transmit sequencer to wait for the next Repetition Rate Counter
rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the
cycle following completion of the prior cycle.
2
TRISTATE
R/W
0
When set to a “1” the TXP and TXN output pins for this transmit channel are both forced to a
high state. When used with an ARINC 429 line driver that supports tri-state operation, such as
the Holt HI-8596, the ARINC 429 databus is forced to a high-impedance state. No ARINC 429
transmission from the HI-3220 occurs when TRISTATE is set.
1
RATE
R/W
0
Selects the transmission rate for the ARINC 429 transmit channel. A “0” selects high-speed
(100Kb/s) and a “1” selects low-speed (12.5Kb/s). High-speed data-rate is switched to
50Kb/s when the 50KOPT bit is set.
0
50KOPT
R/W
0
When this bit is set, the RATE setting is overridden and the ARINC 429 data rate defaults to 50
kb/s
SLP[0-7] Pins
The HI-3220, HI-3223 and HI-3225 device configurations have a digital output for each transmit channel that may be used to set the
slew rate on an external line driver. The SLPx output for a given channel should be connected to the SLP input on an external line
driver such as Holt’s HI-8596 or HI-8597. The SLP output slew rate depends on the values of the RATE and 50KOPT bits as follows:
RATE
0
0
1
1
50KOPT
0
1
0
1
SLPx
1
1
0
1
Bit Rate
100 Kb/s (ARINC 429 High-Speed)
50 Kb/s
12.5 Kb/s (ARINC 429 Low-Speed)
50 Kb/s
HOLT INTEGRATED CIRCUITS
24
HI-3220
ARINC 429 Transmit Scheduler
Each ARINC 429 transmit channel 0 through 7 has its
own transmit controller. The controller is userprogrammed to output ARINC labels in a predefined
order and repetition rate. A sequence of up to 128 ARINC
429 labels may be transmitted before repeating the
sequence.
A descriptor table with up to 128 entries (descriptors) is
compiled by the user to define the sequence of ARINC
429 messages transmitted on each channel. When the
RUN/STOP bit in the Transmit Control Register is
asserted, the controller compiles the first 32-bit ARINC
word from the instructions given by the first descriptor
and then transmits it. A Transmit Sequence Pointer then
increments to the next descriptor in the table and the
process is repeated for Descriptor number 2.
ARINC 429 messages continue to be compiled and
transmitted until the last descriptor in the table. The end
of the table is marked by a special descriptor if not all 128
entries are needed. The Sequence Pointer is then reset
to zero.
A Repetition Rate Counter is used to time the start of the
next transmission cycle.
The user is responsible for construction of the descriptor
table and for setting the Repetition Rate prior to asserting
RUN/STOP. Facilities exist for immediate cycle repetition
and for single-cycle operation.
The byte content of each ARINC 429 message
transmitted is user defined by the descriptor contents.
Data bytes may be sourced from the host CPU / autoinitialization EEPROM (immediate data) or from the
ARINC 429 receive memory (indexed). This allows
received ARINC data to be re-transmitted on another bus
with or without filtering, label byte re-assignment, or data
modification. It also allows data from multiple ARINC 429
receive buses to be re-packetized into new ARINC 429
transmitted messages.
Conditional transmission control allows sequenced words
to be skipped if no new data is available.
Each transmit channel is independently configured with
its own Transmit Control Register, TXCR0-7, as
previously described.
During scheduler transmissions de-asserting the RUN bit
in the Transmit Control register will stop transmissions
after the current frame. To immediately stop after the
current message transmission, either de-assert the
A429TX bit in the Master Control register or set the RUN
input pin low. Keep in mind that setting the RUN input pin
low will stop all transmitters after the current message
completes.
Transmit Descriptor table
Sequence
pointer
0x7F
0x43FF
0x43F8
0x43F0
Sequence 127 Descriptor Frame
(Maximum sequence is 256 when
TXDL256 is set in MCR)
Sequence 126 Descriptor Frame
Repetion Rate
Register
Byte 8 (TX Data 3)
0x4028
Repetition rate
counter
0x4020
(Memory Addresses shown
for Transmit channel 0)
0x4018
0x4010
Sequence
pointer
Sequence
pointer
0x01
0x4008
0x00
0x4000
Sequence 5 Descriptor Frame
Byte 7 (TX Data 2)
Sequence 4 Descriptor Frame
Byte 6 (TX Data 1 / SDI)
Sequence 3 Descriptor Frame
Byte 5 (TX Label)
Sequence 2 Descriptor Frame
Byte 4 (Packet Timer Offset)
Sequence 1 Descriptor Frame
Byte 3 (Packet Timer Period)
Sequence 0 Descriptor Frame
Byte 2 (Rx Label)
Byte 1 (op-code, RX select)
The value of each ARINC 429 label transmitted in the
sequence is defined by its eight-byte descriptor. The first
two bytes define the source of data for transmission. The
next two bytes define transmission timing parameters.
The last four bytes contain data to be transmitted as
defined by the op-code.
Different op-codes allow the data source to be host CPU
populated values, or values from specific locations within
the ARINC 429 receive memory.
The construction of Descriptor frame bytes are described in
the next section.
HOLT INTEGRATED CIRCUITS
25
HI-3220
Current Sequence number
TRANSMIT SEQUENCE POINTERS 0 - 7
(Address 0x8040 - 0x8047)
7 6
MSB
5
4
3
The transmit sequence pointer is set to zero on Master
Reset. Once the Control Register RUN / STOP bit goes
high, sequence execution begins at sequence count
zero. After the first word is sent, the pointer is
incremented by one descriptor (counts descriptor
frames).
2
1
0
LSB
This continues until the programmed sequence is
complete. The sequence pointer is then reset to the
beginning of the descriptor table and program execution
begins as soon as the channel repetition rate counter
time elapses.
Channel Repetition Period
REPETITION RATE REGISTER 0 - 7
(Address 0x8038 - 0x803F)
7 6
MSB
5
The Repetition rate register value defines the time
interval between successive starts of the programmed
transmit sequence for each ARINC 429 transmit channel.
The value is set in binary, with the LSB representing 10
ms when the PRESCALE bit in this channel’s Transmit
Control Register is a zero. When the PRESCALE bit is
set to a one, the LSB represents 1 ms. Repetition rate
time periods may therefore be set from 0 ms to 2.55
seconds
4
3
2
1
0
LSB
One-time Sequence Transmission
To transmit a frame of messages only once (One-time
transmission), set the RUN bit high then low in the
Transmit Control Register before the current frame ends.
If the repetition rate is shorter than the minimum time
needed to transmit all ARINC 429 words in the sequence
(but not zero), the transmit sequence will begin again
immediately if the Control Register SKIP bit is a zero. If
the SKIP bit is a one, the sequencer will wait until the
next rollover of the Repetition Rate Counter before
starting a new cycle.
HOLT INTEGRATED CIRCUITS
26
HI-3220
ARINC 429 TRANSMIT DESCRIPTOR
Data Byte 3 (ARINC 429 bits 32-25)
Descriptor Byte 8
Data Byte 2 (ARINC 429 bits 24-17)
Descriptor Byte 7
Data Byte 1 (ARINC 429 bits 16-9)
S
Descriptor Byte 6
S
Transmit Label (ARINC 429 bits 1-8)
Descriptor Byte 5
Packet Timer Offset (PTO)
Descriptor Byte 4
O
O
O
O
O
O
O
O
Packet Timer Period (PTP)
Descriptor Byte 3
P
P
P
P
P
P
P
P
L
L
L
RX Label
Descriptor Byte 2
L
L
L
L
L
Op-Code
RX Select
Descriptor Byte 1
7 6
MSB
Op-Code
5
4
R
R
R
R
3
2
1
0
LSB
Description
0000
End of sequence. When op-code 0000 is encountered by the sequencer before it reaches sequence number
127, the sequencer resets to zero and begins the next transmission cycle starting at descriptor number 0 as
soon as the repetition rate counter rolls over. Note that the descriptor table is cleared following Master Reset,
(Mode 0 - Mode 3) so no ARINC 429 transmissions are possible until the sequence table has been
configured.
0001
Delay. Delays the transmission of the next ARINC 429 word by the value of the Packet Timer Period byte in
milliseconds. Except for PTP, the value of other descriptor bytes are “don’t care”. A delay with PTP=0 is
equivalent to a no-op.
0010
Immediate data. The value contained descriptor bytes 5 through 8 is transmitted on the ARINC 429 bus.
0011
Immediate data conditional. Bytes 5 through 8 are transmitted only if the RX packet selected by receive
channel “RRRR” and label ”LLLLLLLL” has new data. The NEWTXn bit is sampled to determine if this
location has new data. NEWTXn is then reset.
0100
Indexed data. Transmits descriptor byte 5 as the label appended to the 24 bits of data stored at Receive
channel “RRRR” and label “LLLLLLLL”.
0101
Indexed data conditional. Same as op-code 0100, but transmits only if new data exists at the specified
location as indicated by the NEWTXn bit. NEWTXn is then reset.
0110
Indexed SDI. Same as op-code 0100 except the ARINC 429 SDI bits are replaced with those loaded in
descriptor byte 6, bits 10-9 (”SS”).
0111
Indexed SDI conditional. Same as op-code 0101 except the ARINC 429 SDI bits are replaced with those
loaded in descriptor byte 6, bits 10-9 (”SS”).
1XXX
Reserved. Do not use.
HOLT INTEGRATED CIRCUITS
27
HI-3220
PACKET TIMER
Descriptor flow using the Packet Timer
Descriptor entry
PTP or PTO != 0
Packet Timer Period (PTP) and Packet Timer Offset
(PTO) are used in conjunction with the Repetition Rate
counter to make individual ARINC 429 word transmission
timing possible. The Repetition Rate Counter is
programmable from 0 ms to 2.55 s as defined by the
PRESCALE bit and Repetition Rate Register contents.
PTO = 0
?
If PTO is zero, the word message is transmitted and PRO
is reloaded with PTP. If PTO is non-zero it is
decremented and the word message is skipped.
Yes
Transmit Message
Reload PTO with PTP
No
Decrement PTO
An initial non-zero value in PTO provides an offset prior
to the first transmission. The period between subsequent
transmissions is controlled by PTP. A value of all 1’s in
PTP indicates that the word will be transmitted once
(one-shot mode).
Next Descriptor
Repetition Rate (RR) = Repetition Rate Timer (10ms or
1ms) x Repetition Rate Register value.
See examples 1-4 below.
Descriptor message rate = (PTP+1) x Repetition Rate.
When PTO is non-zero, the message is skipped until
PTO = 0. Each pass of the descriptor block decrements
the PTO count.
Example 1.
0
80
RR = 80 ms, PTP = 3 and PTO = 1
Transmission in 2nd pass and subsequently
every 4th pass (every 320 ms).
Example 2.
240
320
400
XMIT
0
RR = 10 ms, PTP = 2 and PTO = 0
Transmission in 1st pass and subsequently
every third pass (every 30 ms).
160
10
Time ms
XMIT
20
30
XMIT
40
50
Time ms
XMIT
Example 3.
RR = 10 ms, PTP = 1 and PTO = 2
Transmission in 3rd pass and subsequently
every 2nd pass (every 20 ms).
XMIT
XMIT
Example 4.
RR = 1 (10 ms), PTP = 4 and PTO = 0
Transmission in 1st pass and subsequently
every 5th pass (60 ms).
XMIT
Pass 1
XMIT
Pass 2
Pass 3
HOLT INTEGRATED CIRCUITS
28
Pass 4
Pass 5
Pass 6
HI-3220
ARINC 429 Immediate Transmit Option
The Host CPU may instruct the HI-3220 to transmit an
ARINC 429 message immediately using a special SPI
command. The SPI command selects the transmit
channel and provides the four bytes of data to be sent as
a 32-bit ARINC 429 message.
The Transmit Interrupt Enable Register is used to
generate an interrupt at INT when selected Flags are
enabled.
If the transmit sequencer for the selected channel is
active, then the new message(s) in the FIFO are
transmitted as soon as the current message has been
sent. The sequencer then resumes operation at the next
location in the queue.
A 32-message deep FIFO for each transmitter allows
multiple ARINC 429 messages to be queued for
transmission reducing host CPU overhead.
Each transmit FIFO may be monitored by a flag which is
set when the FIFO contains less than a user-defined
number of messages. This threshold value is set in each
transmitter’s Transmit FIFO Threshold Register. The
Flags are accessed via the Transmit Flags register.
Both the RUN input and the Master Control Register
A429TX bit must be high to enable any ARINC 429
transmission.
If the transmit channel’s sequencer is not running (TCR
bit RUN/STOP = “0”), or the sequencer is waiting for the
repetition rate counter to rollover, then the new ARINC
429 message is transmitted without delay.
Table 2 lists the host CPU SPI instruction format.
TF
R
TF 7
R
TF 6
R
TF 5
R
TF 4
R
TF 3
R
TF 2
R
1
TF
R
0
Host writes to a full FIFO will be ignored.
TRANSMIT FIFO THRESHOLD REGISTER
(Address 0x800F)
Bit Name
R/W
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
7
TFR7
R
1
This bit is set when Transmit FIFO 7 contains less than the programmed threshold number of
ARINC 429 messages .
6
TFR6
R
1
This bit is set when Transmit FIFO 6 contains less than the programmed threshold number of
ARINC 429 messages .
5
TFR5
R
1
This bit is set when Transmit FIFO 5 contains less than the programmed threshold number of
ARINC 429 messages .
4
TFR4
R
1
This bit is set when Transmit FIFO 4 contains less than the programmed threshold number of
ARINC 429 messages .
3
TFR3
R
1
This bit is set when Transmit FIFO 3 contains less than the programmed threshold number of
ARINC 429 messages .
2
TFR2
R
1
This bit is set when Transmit FIFO 2 contains less than the programmed threshold number of
ARINC 429 messages .
1
TFR1
R
1
This bit is set when Transmit FIFO 1 contains less than the programmed threshold number of
ARINC 429 messages .
0
TFR0
R
1
This bit is set when Transmit FIFO 0 contains less than the programmed threshold number of
ARINC 429 messages .
NOTE: This register may be read using fast-access SPI Command Op-code 00111100 (0x3C).
Transmit FIFO Count Registers
TRANSMIT FIFO COUNT(0-7)
(Address 0x8080 - 0x8087)
Bit
Name
7:0
TFCn[7:0]
R/W
R
0
Count
Default = 0x00
0
7 6
MSB
5
4
3
2
1
0
LSB
Default
Description
0
Read current transmit message count.
HOLT INTEGRATED CIRCUITS
29
HI-3220
Transmit FIFO Threshold Value Registers
Each Transmitter has its own Transmit FIFO Threshold Register
Threshold
TRANSMIT FIFO THRESHOLD VALUE n
(Address 0x8060 - 0x8067)
Threshold Value
00000
0
0
0
7 6
MSB
5
Default = 0x00
4
3
2
1
0
LSB
Description
Threshold flag is set there are no messages in FIFO (FIFO is empty) (Default)
Threshold flag is set if no more than one message is in the FIFO
Threshold flag is set if no more than two messages are in the FIFO
00011
Threshold flag is set if no more than three messages are in the FIFO
10000
Threshold flag is set if no more than sixteen messages are in the FIFO
11111
Threshold flag is set if no more than 31 messages are in the FIFO (FIFO is not full)
TX
IE
TX 7
IE
TX 6
IE
TX 5
IE
TX 4
IE
TX 3
IE
TX 2
IE
TX 1
IE
0
00001
00010
TRANSMIT FLAG INT ENABLE
(Address 0x804F)
7 6
MSB
5
4
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
TXIE7
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 7 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
6
TXIE6
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 6 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
5
TXIE5
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 5 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
4
TXIE4
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 4 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
3
TXIE3
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 3 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
2
TXIE2
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 2 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
1
TXIE1
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 1 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
0
TXIE0
R/W
0
Setting this bit generates an interrupt when ARINC 429 Transmitter 0 FIFO Flag is set. The
TXFLAG bit in the Pending Interrupt Register will be set and the INT pin will be asserted if the
TXFLAGIE bit is set in the Pending Interrupt Enable Register.
HOLT INTEGRATED CIRCUITS
30
HI-3220
Transmit Watchdog Timer
The Transmit Watchdog Timer (TWDT) is a fail-safe
automatic shutdown mechanism that when enabled
terminates the automatic transmission of scheduled
messages in the event that the host does not refresh the
TWDT 8-bit timer value before reaching zero count. The
TWDT does not halt any transmit messages currently from
the transmit FIFOs. The TWDT is disabled by default after
Master Reset.
The TWDT is now active and WTR begins decrementing
every 20ms.
4. The host must refresh the WTR timer value before it
decrements to zero or a Watchdog Timer event will occur
and automatic transmit scheduler transmissions will stop
after the current frame of message(s) is transmitted as
defined in the transmit descriptor tables. Only those
channels [TX7:TX0] enabled by corresponding WMR low
bits are stopped.
Two 8-bit registers control the TWDT: The Watchdog Mask
Register (WMR), and Watchdog Timer Register (WTR).
5. Normal ARINC 429 transmissions will resume if a nonzero timer value is written to WTR.
Use the following sequence to use the TWDT. The steps
must be sequential:
6.Once the TWDT is enabled it cannot be disabled
except by a Master Reset or a Software Reset SPI
Opcode command.
1. Write 0xFF to WMR
2. Write an 8-bit timer value to WTR.
5
4
4
M
W R3
M
R
W 2
M
R
W 1
M
R
0
7 6
MSB
W
R
5
W
M
6
R
W
M
R
R
M
W
W
M
7
3. Write a non-0xFF value to WMR. Transmit channels
with Watchdog Timer enabled must have 0’s in the
corresponding bit position [TX7:TX0].
Default = 0xFF
WATCHDOG MASK REGISTER
(Address 0x807E)
3
2
1
0
LSB
Bit Name
R/W
Default Description
7
WMR7
R/W
1
Watchdog is enabled for transmitter 7 if WMR7=0 or disabled if WMR7=1.
6
WMR6
R/W
1
Watchdog is enabled for transmitter 6 if WMR6=0 or disabled if WMR6=1.
5
WMR5
R/W
1
Watchdog is enabled for transmitter 5 if WMR5=0 or disabled if WMR5=1.
4
WMR4
R/W
1
Watchdog is enabled for transmitter 4 if WMR4=0 or disabled if WMR4=1.
3
WMR3
R/W
1
Watchdog is enabled for transmitter 3 if WMR3=0 or disabled if WMR3=1.
2
WMR2
R/W
1
Watchdog is enabled for transmitter 2 if WMR2=0 or disabled if WMR2=1.
1
WMR1
R/W
1
Watchdog is enabled for transmitter 1 if WMR1=0 or disabled if WMR1=1.
0
WMR0
R/W
1
Watchdog is enabled for transmitter 0 if WMR0=0 or disabled if WMR0=1.
Time-out period
WATCHDOG TIMER REGISTER
(Address 0x807F)
Default = 0x00
7 6
MSB
5
4
3
2
1
0
LSB
WTR7:0 sets the time-out period for the Watchdog Timer. The LSB is 20ms. The maximum time-out period of 5.1s is programmed by
writing 0xFF to the WTR.
HOLT INTEGRATED CIRCUITS
31
HI-3220
RESET AND START-UP MODES
After power-on, the HI-3220 is in an undefined state. The
MRST pin must be taken low to begin device initialization.
The MRST pin may be asserted at any time. Taking
MRST low immediately stops all execution and sets the
READY output low, indicating that the part is in the reset
state. MRST requires a minimum 225 ns pulse.
On the rising edge of MRST the HI-3220 samples the
state of the MODE2-0 input pins. This is the only
occasion these inputs are sampled. Once MRST goes
high, the MODE2-0 pins become outputs ESCLK, EMOSI
and ECS. The MODE setting is readily accomplished
using pull-up/down resistors at the three pins (NOTE:
when using an external EEPROM with a pull-up resistor
on the ECS (Mode0) pin, the series pull-down resistor on
Mode0 needs to be low enough to drive the Mode0 signal
to a low state. Holt recommends a 10K:1K ratio).
The state of the MODE pins determines one of six
possible initialization sequences (Mode 0 through Mode
5). MODE[2:0] = 000 sets Mode 0, MODE[2:0] = 001 sets
Mode 1, MODE[2:0] = 101 sets Mode 5, etc. Note Mode
7 is reserved for factory test and must not be used.
These six initialization modes allow the user to customize
the start-up configuration of the device. See Figure 1,
Reset and Start-up Operation Flow Chart.
The total time from MRST rising edge to READY pin high
depends on the total number of MCLK cycles (50MHz
clock input) and is summarized in Table 2 for each mode.
Once the initialization is complete, the device enters the
Idle State when the ready pin goes high. In Idle State, the
host CPU may communicate with the HI-3220 memory
and registers using the host CPU SPI link. When in the
Idle State, the HI-3220 does not transmit or receive any
messages on any of the ARINC 429 buses.
To begin data bus operation, the user must transition the
RUN input from a low to high state. Immediately following
the rising edge of RUN, the part enters the Active State
and bus message processing begins.
During initialization, various device configuration tasks
are performed according to the Mode selection set at the
MODE2:0 input pins. The available options are described
below in sub-sections 1-4.
MODE[2:0] status bits can be examined by reading the
upper three bits in the UPPER BIST FAIL
ADDRESS REGISTER 0x807A.
MODE 6 is reserved for RAM BIST.
Software Reset Opcode
The SPI software reset opcode 0xFA5(8+mmm) resets the
Configuration registers and Transmit descriptor tables, RX
Interrupt Map and RX Enable Map areas according to the
chart shown in Figure 1 depending on the mmm bit field
(mode selection) used in the SPI opcode. See table 2.
TABLE 1. Start-up Time for each Mode
MODE[2:0]
PINS
MODE
MCLK Cycles
Start-up Time*
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
RESERVED
8,204
555,386
73,745
620,927
53,388
9
-
164.080 µs
11.107720 ms
1.4749 ms
12.41854 ms
107.760 µs
180 ns
-
* The time (±1 MCLK) from rising edge of MRST to READY pin high.
HOLT INTEGRATED CIRCUITS
32
HI-3220
RESET AND START-UP MODES
(cont.)
1. RAM Integrity Check
In Modes 2 and 3, the HI-3220 performs a RAM integrity
check. A read/write check is performed on the entire
RAM space. An incrementing pattern is written to
sequential RAM locations, then this pattern is read and
verified. Each RAM location is re-written with the 1s
complement of its current contents then this pattern is
read and verified. The incrementing pattern followed by
its 1s complement ensures that each RAM location can
store both a 1 and 0 state. If the RAM integrity check
fails, the INT pin is asserted and the Pending Interrupt
Register RAMFAIL bit is set. The part enters the “Safe”
state, in which the HI-3220 is able to accept and respond
to Host CPU SPI Instructions, but cannot enter Normal
Operating mode until the MRST input is taken low to
repeat the initialization sequence. The RAMFAIL Interrupt
is not maskable.
2. Clear Data Memory
In Modes 0 - 4, the HI-3220 automatically clears all
memory locations in the address range 0x0000 to
0x3FFF and 0x6C00 to 0x7FFF. This is the space
reserved for ARINC 429 message data. Configuration
tables and HI-3220 registers are not affected.
4. Auto-Initialize from EEPROM
The contents of the Auto-Initialization EEPROM are
copied into the HI-3220 memory and registers via the
EEPROM SPI interface. The part verifies the integrity of
the data transfer from the EEPROM by running through a
byte-by-byte compare routine and a checksum validation.
If a compare error is detected, the AUTOERR bit is set in
the Pending Interrupt Register, the INT output is
asserted. The location of the error is captured in the
AUTO-INIT FAIL ADDRESS registers 0x807B (Auto-Init
Fail LS address) and 0x807C (Auto-Init Fail MS address)
and the part enters the Safe state. If a checksum error is
detected, the CHKERR bit is set in the Pending Interrupt
Register, the INT output is asserted and the part enters
the Safe state. The AUTOERR and the CHKERR
interrupts are not maskable.
Once initialization is successful, the part enters the Idle
state. The host CPU may read and write HI-3220 internal
memory and registers in all Modes. If not using the autoinitialization feature, the host CPU should configure the
device at this time.
NOTE: Mode 7 is reserved and must not be selected.
3. Initialize Registers and Clear all memory
In addition to clearing data memory (0x0000 to 0x3FFF
and 0xc00 to 0x7FFF), Modes 0, 1, 2, and 3 also clear all
configuration and look-up tables (0x4000 to 0x6BFF) as
well as setting all configuration registers (0x8000 to
0x807F) to their default states. All registers default to
zero unless otherwise noted.
HOLT INTEGRATED CIRCUITS
33
HI-3220
MRST driven to “0”
Stop execution, READY => 0
RESET STATE
Delay 225ns minimum before raising MRST high
MRST driven to “1”
Sample MODE2:0 inputs
MODE 0
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
No
No
Yes
Yes
No
No
RESERVED
Clear data memory
(0x0000 - 0x3FFF)
Yes
Yes
Yes
Yes
Yes
No
RAM
BIST
ENABLE *
Initialize Registers and
Clear Configuration Tables
(0x4000 - 0x6BFF)
Yes
Yes
Yes
Yes
No
No
RESERVED
Auto-Initialize from
EEPROM
No
Yes
No
Yes
No
No
RESERVED
Perform
RAM Integrity Check
RAM Pass
?
No
Set RAMFAIL
INT = 0
No
Set AUTOERROR
INT = 0
RESERVED
Yes
Copy OK
?
Yes
READY => 1
SAFE STATE
IDLE STATE
RUN driven 0 - 1
* See RAM BIST details is section
RAM BUILT-IN SELF-TEST.
ACTIVE STATE
Figure 1. Reset and Start-up Operation flow chart.
HOLT INTEGRATED CIRCUITS
34
HI-3220
INTERRUPTS
The HI-3220 includes a simple, user-selectable Interrupt
Handler. Two types of Interrupt are possible - Message
Event Driven (ARINC 429 Bus), and Fault Driven.
ARINC 429 Receive Interrupts
As described earlier, the user can elect to generate an
interrupt upon receipt of an ARINC 429 message on any
combination of the sixteen available channels and for any
of the possible 256 label byte (ARINC message bits 1-8)
values. Interrupts are enabled when the Receive
Interrupt look-up bit is a “1”.
When a message arrives that is flagged to generate an
Interrupt, that channel’s bit is set in the Receive Pending
Interrupt Register RPIRH, RPIRL. The Interrupt Address
Register (IAR) for that channel is updated with the ARINC
429 8-bit label value.
For example, if ARINC Receive channel 7 is enabled for
Interrupts when messages with ARINC label 0xD4 arrive,
then on receipt of such a message, RPIRL bit 7 is set to a
“1” and the value 0xD4 is written to IAR7.
If the corresponding bit in the Receive Interrupt Mask
Register is a “1” the INT interrupt output will go low and
stay low until the ACK input pin is driven low. Driving ACK
low, causes the INT pin to return to one.
A special Indexed SPI read instruction is available to
allow the host to efficiently retrieve ARINC 429 messages
which have Interrupts Enabled (see SPI instruction set
section).
ARINC 429 Transmit Interrupts
The user can elect to generate an interrupt when sending
ARINC 429 messages using the transmit FIFOs. The
Transmit Flag Interrupt Enable Register is programmed
to define which transmit channels may generate an
interrupt. If enabled, each time a bit is set in the Transmit
FIFO Threshold Flag Register for an enabled channel,
INT will be asserted.
Fault Interrupts
There are four fault Interrupt bits in the PIR. Fault
Interrupts are not maskable, and their Interrupt Mask bits
are fixed at a “1”.
COPYERR is set when the HI-3220 detects a mismatch
between RAM and EEPROM after attempting to program
the Auto-initialization EEPROM.
AUTOERR is set when the Auto-Initialization EEPROM
read verification cycle detects a mismatch between the
on-chip memory and EEPROM following autoinitialization.
CHKERR is set when an auto-initialization checksum
error is detected.
The RAMFAIL bit is set if the Built-In Self Test sequence
fails.
Note that if ACK is tied low permanently, the INT pin will
go low for approximately 1 us before returning to one. A
host CPU read of the RPIRH or RPIRL register reads the
current value and resets it to 0x00.
HOLT INTEGRATED CIRCUITS
35
RECEIVE PENDING INTERRUPT REGISTER HIGH / LOW
(Address 0x8008, 0x8006)
(Alternate Address 0x800C, 0x800B)
Bit
Name
15:0
PIR[15:0]
R/W
R
7 6
MSB
5
4
3
2
1
0
LSB
R
7
PI
R
6
PI
R
5
PI
R
4
PI
R
3
PI
R
2
PI
R
1
PI
R
0
PI
PI
R
1
PI 5
R
1
PI 4
R
1
PI 3
R
1
PI 2
R
1
PI 1
R
1
PI 0
R
9
PI
R
8
HI-3220
7 6
MSB
5
4
3
2
1
Default
Description
0
When a message is received on a given channel that triggers an interrupt, that
channel’s corresponding bit is set, e.g. if a message received on Rx channel 5
triggers an interrupt, the bit PIR5 will be set. If this bit is unmasked in the Receive
Interrupt Mask Register (see below), the INT output pin is asserted.
0
LSB
7 6
MSB
7 6
MSB
5
4
3
2
1
0
LSB
IE
7
R
IE
6
R
IE
5
R
IE
4
R
IE
3
R
IE
2
R
IE
1
R
IE
0
R
RECEIVE INTERRUPT ENABLE REGISTER HIGH / LOW
(Address 0x804C, 0x804B)
R
IE
1
R 5
IE
1
R 4
IE
1
R 3
IE
1
R 2
IE
1
R 1
IE
1
R 0
IE
9
R
IE
8
Note: This register pair is automatically cleared when read.
5
4
3
2
1
Name
R/W
Default
Description
15:0
RIE[15:0]
R/W
0
Each bit in this register, RIE[15:0], is a mask for a corresponding bit in the
Receive Pending Interrupt Register (PIR[15:0], described above). Writing a “1”
to an IMR bit results in assertion of the INT output pin when the corresponding
PIR bit is set (ARINC 429 message received). Writing a “0” to an IMR bit will
mask the corresponding PIR bit in the Receive Pending Interrupt Register,
resulting in non-assertion of the INT pin when an ARINC 429 message is
received.
IA
R
n
IA 7
R
n
IA 6
R
n
IA 5
R
n
IA 4
R
n
IA 3
R
n
IA 2
R
n
IA 1
R
n0
Bit
RECEIVE INTERRUPT ADDRESS REGISTERS 0 - 15
(Address 0x8010 - 0x801F)
Bit Name
7:0 IAR0[7:0]
R/W
R
n = 0 - 15
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
0
The label number of the ARINC 429 message causing an interrupt is loaded into this
register. Each channel has a corresponding Receive Interrupt Address Register
(IAR0 - IAR15).
HOLT INTEGRATED CIRCUITS
36
0
LSB
EE
A
C BO
O R
P T
AU YE ER
T RR R
C OE
H R
K R
R ER
AM R
R FA
XR IL
R AM
XF N
E
TX LAG W
FL
AG
HI-3220
PENDING INTERRUPT REGISTER
(Address 0x8004)
(Alternate Address 0x800A)
7 6
MSB
5
4
3
2
1
0
LSB
The INT will be asserted when any of the bits in this register are set.
Bit Name
R/W
Default Description
7
EEABORTERR R
0
EE Abort programming error
6
COPYERR
0
EE copy error. RAM - EEPROM mismatch
R
5
AUTOERR
R
0
Auto-inititailization RAM read error
4
CHKERR
R
0
Auto-initialization checksum fail
3
RAMFAIL
R
0
Power-On Reset RAM Integrity Check fail
2
RXRAMNEW
R/W
0
Asserted high with any new message reception, all channels
1
RXFLAG
R
0
Logical OR of ARINC 429 Receive FIFO FLAG signals
0
TXFLAG
R
0
A Transmit FIFO Flag is set
EE
A
C BO
O R
P T
AU YE ER
T RR R
C OE
H R
K R
R ER
AM R
R FA
XR IL
R AM
XF N
E
TX LAG W
E
FL
AG
NOTE: This register is cleared when read.
PENDING INTERRUPT ENABLE REGISTER
(Address 0x804A)
Bit Name
R/W
7 6
MSB
5
4
3
2
1
0
LSB
Default Description
7
EEABORTERR R
1
EE Abort programming error
6
COPYERR
R
1
COPYERR is not maskable
5
AUTOERR
R
1
AUTOERR is not maskable
4
CHKERR
R
1
CHKERR is not maskable
3
RAMFAIL
R
1
RAMFAIL is not maskable
2
RXRAMNEWE R/W
0
Enable for RXRAMNEW
1
RXFLAGIE
R/W
0
INT pin is asserted if this bit is a “1” and the Pending Interrupt Register RXFLAG bit is set
0
TXFLAGIE
R/W
0
INT pin is asserted if this bit is a “1” and the Pending Interrupt Register TXFLAG bit is set
HOLT INTEGRATED CIRCUITS
37
HI-3220
INTERRUPT HANDLING
The static state of ACK determines if INT is a level or pulse
signal.
Op-codes for single 8-bit pending register
reads
INT Level Mode:
(SPI clocking = 8 Op-code clocks + 8 data clocks)
When an interrupt occurs, the INT pin is asserted low if the
ACK pin is high. When ACK is asserted low, the INT pin
returns to a high state. ACK should be a negative pulse so
it is normally in the inactive state.
OP-code
Register Address Name
0x10
0x18
0x20
8004
8006
8008
INT Pulse Mode:
If ACK is held low, this causes the INT to pulse negative for
approximately 1 microsecond when an interrupt occurs.
Host Interrupt Servicing Options
When an interrupt occurs, the host typically reads one or
more interrupt pending registers to determine the source of
the interrupt. Depending on system requirements a small
or large number of interrupts can be supported. If there are
several interrupt sources that span across the three
pending interrupt registers (PIR, RPIRH and RPIRL) then
all three registers need to be read to determine the
interrupt source(s). In a simpler system where there may
be eight or less receiver interrupts grouped into either the
higher or lower RPIRx registers it is possible to detect the
interrupt sources by reading a single pending interrupt
register. Reading one register is faster than reading three
registers so this is a good way to reduce host interrupt
processing time. Although the HI-3220 has a very fast SPI
port, some SPI masters insert unwanted delays between
bytes, so this helps reduce the time the host takes to
determine the interrupt source.
PIR
RPIRL
RPIRH
Op-codes for multiple pending interrupt
registers
To read all three registers issue an 8-bit op-code 0x28 + 24
data clocks. This returns three consecutive bytes
representing PIR + RPIRH + RPIRL. This is the fastest
method to read in all three interrupt registers. Another way
to use op-codes 0x2C or 0x30 may be beneficial
depending on the user requirements. For example , to only
read the first and second pending interrupt registers, issue
the op-code 0x28 and only 16 data clocks. The two
returned bytes represent PIR and RPIRH. If op-code 0x2C
was used with 16 data clocks then the two returned bytes
represent RPIRH and RPIRL. As with any op-code
sequence HCS must remain low during the whole time until
all the data is fully clocked.
Op-code Data Register
Bytes Address
0x28
0x2C
0x30
3
2
1
Two op-code groups are available for reading pending
interrupt registers so host interrupt servicing can be
optimized based on the number of system interrupts.
HOLT INTEGRATED CIRCUITS
38
Name
800A, 800B, 800C PIR+RPIRL+RPIRH
800B, 800C
RPIRL+RPIRH
800C
RPIRH
HI-3220
RAM BUILT-IN SELF-TEST
The HI-3220 offers a built-in self-test (BIST) feature which can be used to check RAM integrity. The BIST Control/Status
Register is used to control the BIST function. All tests are destructive, overwriting data present before test commencement.
NOTE: To use BIST self-test, the part needs to be in Mode 6 with the RUN pin low.
To use RAM BIST follow these steps:
R
BF
R AIL
BS
R EL
BS 2
R EL
BS 1
R EL
BS 0
TA
RT
R
BF
R AIL
BP
AS
S
1. Power up the part in MODE 6. This can be accomplished by having MODE2 and MODE1 input pins high and
MODE0 input pin low while powering up the part. Alternatively, configure the part in MODE-6 by executing the SPI
Software Reset Opcode in Mode 6 (mmm=6 in Opcode Byte 2).
2. Set the RUN input pin low.
3. Write to the BIST control/status register with the desired RAM test (RBSEL2:0) and the RBSTRT bit high to
initiate the test.
4. Wait for READY to be asserted high by polling the READY pin or by examining READY bit-5 in the MSR register
using SPI.
5. After READY is asserted high examine bits 0 and 1 for the RAM BIST Fail or Pass result.
BIST CONTROL/STATUS REGISTER
(Address 0x8078)
X
7 6
MSB
5
4
3
2
1
0
LSB
This register controls RAM built-in self-test. Bits 0,1 are Read Only. The remaining bits in this register are Read-Write but can
be written only in MODE2:0 = 0x06.
BIST Control Register bits provide a means for the host to perform RAM self-test at other times. Register bits 6:4 select RAM
test type. Then bit 3 starts the selected RAM test, and bits 1:0 report a fail/pass result after test completion.
Bit No.
Mnemonic Interrupt Type
7
RBFFAIL
6:4
RBSEL2-0 RAM BIST Select Bits 2-0.
This 3-bit field selects the RAM BIST test mode applied when the RBSTART bit is set:
RAM BIST Force Failure.
When this bit is asserted, RAM test failure is forced to verify that RAM BIST logic is functional.
RBSEL2:0
000
001
010
011
100
101
110
111
SELECTED RAM TEST
Idle
Pattern Test, described below
Write 0x00 to RAM address range 0x0000 - 0x7FFF
Read and verify 0x00 over RAM address range 0x0000 - 0x7FFF
Write 0xFF to RAM address range 0x0000 - 0x7FFF
Read and verify 0xFF over RAM address range 0x0000 - 0x7FFF
Inc / Dec Test performs only steps 5 - 8 of the Pattern Test below
Idle
Description of the RAM BIST “PATTERN” test selected when register bits RBSEL2:0 =
001:
1. Write 0x00 to all RAM locations, 0x0000 through 0x7FFF
2. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF:
a. Read and verify 0x00
b. Write then read and verify 0x55
HOLT INTEGRATED CIRCUITS
39
HI-3220
c.
d.
e.
f.
g.
h.
I.
j.
Write then read and verify 0xAA
Write then read and verify 0x33
Write then read and verify 0xCC
Write then read and verify 0x0F
Write then read and verify 0xF0
Write then read and verify 0x00
Write then read and verify 0xFF
Write 0x00 then increment RAM address and go to step (a)
3. Write 0xFF to all RAM locations, 0x0000 through 0x7FFF
4. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF:
a. Read and verify 0xFF
b. Write then read and verify 0x55
c. Write then read and verify 0xAA
d. Write then read and verify 0x33
e. Write then read and verify 0xCC
f. Write then read and verify 0x0F
g. Write then read and verify 0xF0
h. Write then read and verify 0x00
I. Write then read and verify 0xFF
j. Write 0xFF then increment RAM address and go to step (a)
5.
6.
7.
8.
Write an incrementing pattern into sequential RAM locations from 0x0000 to 0x7FFF
Read each memory location from 0x0000 to 0x7FFF and verify the contents
Write 1s complement of each cell’s current contents, into each RAM location (same addr range)
Read each memory location and verify the contents
3
RBSTRT
RAM BIST Start.
Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT
bit can only be set in MODE2:0 = 0x04. This bit is automatically cleared upon test completion.
Register bits 1:0 indicate fail / pass test result.
2
---------
Not Used.
1
RBFAIL
RAM BIST Fail.
Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is
automatically cleared when RBSTRT bit 3 is set. When BIST failure occurs, a clue to the failing RAM
address can be read at register addresses 0x8079 and 0x807A. For speed, the RAM BIST
concurrently tests four consecutive RAM addresses in parallel. If a test failure occurs, register
addresses 0x8079 and 0x807A can be used to determine the four RAM addresses tested.
0
RBPASS
RAM BIST Pass.
Device logic asserts this bit when the selected RAM test completes without error. This bit is
automatically cleared when RBSTRT bit 3 is set.
BISTFL
LOWER BIST FAIL ADDRESS REGISTER
(Address 0x8079)
7 6
MSB
5
4
3
2
1
0
LSB
BISTFH
UPPER BIST FAIL ADDRESS
AND MODE BITS REGISTER
(Address 0x807A)
m m m
15 14 13 12 11 10 9 8
LSB
MSB
Bits in Register BISTFH
are Mode[2:0] Status Bits
HOLT INTEGRATED CIRCUITS
40
HI-3220
HOST SERIAL PERIPHERAL INTERFACE
HSCK, and output data for each device changes on the
falling edge. These are known as SPI Mode 0 (CPHA = 0,
CPOL = 0) and SPI Mode 3 (CPHA = 1, CPOL = 1). Be sure
to set the host SPI logic for one of these modes.
In the HI-3220, internal RAM and registers occupy a (32K +
128) x 8 address space. The lowest 32K addresses access
RAM locations and the remaining addresses access
registers. Timing is identical for register operations and
RAM operations via the serial peripheral interface, and
read and write operations have likewise identical timing.
As seen in Figure 2, the difference between SPI Modes 0
and 3 is the idle state for the HSCK signal. There is no
configuration setting in the HI-3220 to select SPI Mode 0 or
Mode 3 because compatibility is automatic. Beyond this
point, the HI-3220 data sheet only shows the SPI Mode 0
HSCK signal in timing diagrams.
Host access is only allowed when the part is READY or in
SAFE mode. NOTE: writes will be blocked and reads will
return the Master Status Register value until either of these
modes occur.
The SPI protocol transfers serial data as 8-bit bytes. Once
HCS chip select is asserted, the next 8 rising edges on
HSCK latch input data into the master and slave devices,
starting with each byte’s most-significant bit. The HI-3220
SPI can be clocked at 40 MHz. To achieve reliable 40 MHz
SPI the hardware should be optimized for low PCB
capacitance with a short distance from the device to the
host.
Serial Peripheral Interface (SPI) Basics
The HI-3220 uses an SPI synchronous serial interface for
host access to registers and RAM. Host serial
communication is enabled through the Chip Select (HCS)
pin, and is accessed via a three-wire interface consisting of
Serial Data Input (HMOSI) from the host, Serial Data
Output (HMISO) to the host and Serial Clock (HSCK). All
programming cycles are completely self-timed, and no
erase cycle is required before write.
Multiple bytes may be transferred when the host holds
HCS low after the first byte transferred, and continues to
clock HSCK in multiples of 8 clocks. A rising edge on HCS
chip select terminates the serial transfer and reinitializes
the HI-3220 SPI for the next transfer. If HCS goes high
before a full byte is clocked by HSCK, the incomplete byte
clocked into the device HMOSI pin is discarded.
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-3220 Host CPU
interface operates as an SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOLCPHA combinations define four possible "SPI Modes."
Without describing details of the SPI modes, the HI-3220
operates in the two modes where input data for each
device ( master and slave) is clocked on the rising edge of
In the general case, both master and slave simultaneously
send and receive serial data (full duplex) as shown in
Figure 2 below. When the HI-3220 is sending data on
HMISO during read operations, activity on its HMOSI input
is ignored. Figures 3 and 4 show actual behavior for the HI3220 HMISO output.
HSCK (SPI Mode 0)
0
1
2
3
4
5
6
7
HSCK (SPI Mode 3)
0
1
2
3
4
5
6
7
HMOSI
HMISO
High Z
MSB
LSB
MSB
LSB
High Z
HCS
FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol, HSCK is Shown for SPI Modes 0 and 3
HOLT INTEGRATED CIRCUITS
41
HI-3220
0
1
3
2
5
4
7
6
0
1
3
2
5
4
7
6
HSCK
SPI Mode 0
MSB
LSB
HMOSI
Command Byte
HMISO
LSB MSB
MSB
High Z
High Z
Data Byte
HCS
Host may continue to assert HCS
here to read sequential byte(s)
when allowed by the instruction.
Each byte needs 8 HSCK clocks.
FIGURE 3. Single-Byte Read From RAM or a Register
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
HSCK
SPI Mode 0
MSB
LSB MSB
LSB
LSB MSB
HMOSI
Command Byte
HMISO
Data Byte 0
Data Byte 1
High Z
HCS
Host may continue to assert HCS
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
FIGURE 4. 2-Byte Write To RAM or a Register Pair
HOLT INTEGRATED CIRCUITS
42
HI-3220
HI-3220 SPI COMMANDS
Refer to the HI-3220 SPI command set shown in Table 2.
For the HI-3220, each SPI read or write operation begins
with an 8- or 16-bit command byte(s) transferred from the
host to the device after assertion of HCS. Since HI-3220
command byte reception is half-duplex, the host discards
the dummy byte(s) it receives while serially transmitting
the command byte(s).
Fast Access Commands for Registers 0-31
The SPI command set includes directly-addressed read
and write commands for registers 0 through 31 (Memory
Address 0x8000 to 0x801F). The 8-bit pattern for these
commands has the general form
0-R-R-R-R-R-0-0
where RRRRR is the 4-bit register number. All registers
within this address range are read-only, with the exception
of the Master Control Register, which utilizes two
addresses, one for read and one for write operations.
initialized before any indirect read or write operation. Two
dedicated SPI instructions are used to write and read the
MAP. SPI Instruction 0x98 followed by two data bytes is
used to write MAP. SPI instruction 0x90 reads two data
bytes from MAP. The first byte is the most significant eight
bits of the address. For example, SPI sequence 0x98,
0x12, 0x34 write the value 0x1234 into the MAP.
Two SPI instructions read and write data bytes to memory
or registers using the MAP as an address pointer. Single or
multi-byte reads and writes may be performed. MAP is
incremented after each byte access.
Two command bytes cannot be “chained”; HCS must
be de-asserted after the command, then reasserted for the
following Read or Write command.
Note: When the primary or fast-access address pointer is
used for auto-incrementing multi-word read/write and
reaches the top of the memory address range (0x7FFF), or
the top of the register address range (0xFFFF) attempts to
read further bytes will result the terminal address (0x7FFF
or 0xFFFF) being output again. The host should avoid this
situation.
Figures 3 and 4 show read and write timing as it appears
for fast-access register operations. The command byte is
immediately followed by a data byte comprising the 8-bit
data word read or written. For a single register read or
write, HCS is de-asserted after the
data byte is
transferred.
Two single-byte SPI commands use the current address
pointer value in MAP without first loading or otherwise
modifying it:
Command
0x80
Read Operation
read location addressed by pointer value
Multiple register read or write cycles may be performed by
transferring more than one byte before HCS is deasserted. Multiple register access occur in address order
starting with the register specified in the SPI instruction.
Command
0x88
Write Operation
write location addressed by pointer value
Note: Register locations not shown in table 2 are
“reserved” and cannot be written using any SPI command.
Further, these register addresses will not provide
meaningful data in response to read commands.
Either of these commands can be used to read or write a
single location, or may be used when starting a multi-byte
read or write by using the pointer’s auto-increment feature.
MAP is only used with opcodes 0x80 and 0x84.
Register Direct Addressing
Special Purpose Commands
Two 2-byte SPI instructions read and write data bytes to
registers anywhere in the register address space from
0x8000 through 0x807F for writes or 0x8000 through
0x8087 for reads. The explicit register address is included
in the op-code bit sequence. The opcodes take the form:
Write: 11011AAA AAAA0000
Read: 1110AAAA AAAA0000
Where AAA AAAA is the least significant seven or eight
bits of the register address.
Several other HI-3220 SPI commands load or otherwise
modify the memory address pointer before initiating a read
or write process. These commands are designed to allow
speedy access to messages received on the ARINC 429
buses.
RAM and Register Indirect Addressing
To access the entire address range of the part, SPI
commands are included that use an address pointer to
indicate the address for read or write transactions. This
sixteen-bit memory address pointer (MAP) must be
Using a 2-byte SPI command, the address pointer can be
directly loaded with the memory address for the last
received ARINC 429 message which triggered an
interrupt.
Op Code 11001000 CCCC0000
The HI-3220 will retrieve the current ARINC Receive
Interrupt Vector for a given receive channel (CCCC),
calculate the memory address for the first word of the
corresponding receive memory data block, and then
read the location at that address.
HOLT INTEGRATED CIRCUITS
43
HI-3220
This command can be used to read just the most recent
ARINC 429 Receive Status Byte, or may be used to start a
four-byte read because memory pointer auto-increment
occurs after the Status Byte is read.
Op Code 11010000 CCCC0000
The HI-3220 will retrieve the current ARINC Receive
Interrupt Vector for a given channel (CCCC), calculate the
memory address for the first word of the corresponding
receive memory data block, then output the value of the
Receive Interrupt Vector (ARINC 429 label byte).
This command can be used to read just the most recent
ARINC 429 label value received, or may be used to start a
four-byte read to output the entire four-byte ARINC
message, because memory pointer auto-increment
occurs after the label byte is output.
Op Code 10100TTT
Writes an ARINC 429 message to ARINC 429 transmit
scheduler TTT for immediate transmission, where TTT
represents the transmit channel number.
Op Code 11111010 01011010
This op-code forces a reset of the HI-3220. The part will reinitialize in exactly the same manner as if the MRST pin
had been asserted.
TABLE 2. DEFINED SPI COMMANDS
OP CODE
byte 1
OP CODE
byte 2
Auto
Increment
Number of
Data Bytes
0RRRRR00
10000000
10001000
10010000
10011000
10100TTT
11000000
11001000
None
None
None
None
None
None
CCCC0000
CCCC0000
Yes
Yes
Yes
No
No
No
Yes
No
1++*
1++*
1++*
2
2
4, 8, 12...
4, 8, 12...
4
11010000
CCCC0000
No
4
11011AAA
1110AAAA
11111010
AAAA0000
AAAA0000
01011mmm
Yes
Yes
No
1++*
1++*
0
DESCRIPTION
Fast Register access at register RRRRR
Read memory at address MAP
Write memory at address MAP
Read MAP
Write MAP
Transmit ARINC 429 message on transmit bus TTT
Read ARINC 429 FIFO # CCCC. Read multiples of four bytes
Read ARINC block at receive channel CCCC, label
(Reads status word plus data). See Note 3 below.
Read ARINC message at receive channel CCCC, label
(Reads label plus data). See Note 3 below.
Write register number AAA AAAA (0x8000 - 0x807F)
Read register number AAAA AAAA (0x8000 - 0x8087)
Software Reset with mode 0 - mode 6, 000-110
*NOTE: Supports multi-byte transfer during auto-increment.
FAST-ACCESS SPI COMMANDS FOR REGISTERS 0-31
Command Bits 6:2 Convey the 5-Bit Register Address
COMMAND BITS
7 6 5 4 3 2 1 0
HEX
BYTE
FUNCTION
COMMAND BITS
7 6 5 4 3 2 1 0
HEX
BYTE
FUNCTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
Write MCR
Read MCR
Read MSR
Reserved
Read PIR
Reserved
Read RPIRL
Reserved
Read RPIRH
Reserved
Read PIR+RPIRL/H
Read RPIRL/H
Read RPIRH
Read FTFL
Read FTFH
Read TFR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
Read IAR0
Read IAR1
Read IAR2
Read IAR3
Read IAR4
Read IAR5
Read IAR6
Read IAR7
Read IAR8
Read IAR9
Read IAR10
Read IAR11
Read IAR12
Read IAR13
Read IAR14
Read IAR15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Notes:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1. Op-code 0x28 is used to read PIR, RPIRL and RPIRH as a three-byte data field.
2. Op-code 0x02C is used to read RPIRL and RPIRH as a two-byte data field.
3. To use OpCodes 11000000 CCCC 0000 and 11010000 CCCC 0000 the corresponding Received Data
Interrupt Look-Up Table bits must be set for the desired channels and labels. Enabling interrupts in the
interrupt enable registers are not required.
HOLT INTEGRATED CIRCUITS
44
HI-3220
PROGRAMMING THE AUTO-INITIALIZATION EEPROM.
Following reset, the HI-3220 may be completely
configured by automatically copying the contents of an
external EEPROM into HI-3220 memory and registers. An
SPI enabled 64KByte EEPROM is used for this purpose.
The EEPROM memory space is mapped to the HI-3220.
All configuration memory blocks are copied. The ARINC
429 Received Data Memory contents and ARINC 429
Receive log FIFO contents are not copied to or from the
EEPROM.
The HI-3220 can be used to program the Auto-Initialization
EEPROM. When the HI-3220 is in its IDLE state (RUN
input = “0”), a five step sequence must be performed to
begin the EEPROM programming cycle:
1. Write data value 0x5A to HI-3220 memory address
0x8FFE.
2. Write data value 0x96 to HI-3220 memory address
0x8FFA. Step 2 must occur within 1ms of step 1.
3. Write data value 0xF0 to memory address 0x8FF8 within
10ms.
programming cycle is aborted.
Step 5 initiates the cycle. The READY pin goes low, and
the contents of the HI-3220 memory and registers are
copied to the EEPROM. When copying is complete, the HI3220 executes a byte-by-byte comparison of the EEPROM
and its own register / memory contents. If the verification
completes successfully, the READY pin goes high.
A 2’s complement of the checksum is also written to the
EEPROM at location 0x8080. The total read back
checksum should be zero. The following locations are
excluded from the checksum because they are either readonly or unused locations:
0x8001 - 0x800F
0x8010 - 0x801F
0x8040 - 0x8047
0x8068 - 0x807C.
If the comparison of the EEPROM contents and HI-3220
memory / register contents results in a discrepancy, the HI3220 enters the SAFE state, the PROGERR bit is set in the
Pending Error Register and the INT output is asserted.
The user must clear the PROGERR issue before normal
operation can resume.
4. Wait > 1ms, but less than 10ms.
5. Write 0xC3 to 0x8FFC
If the five step sequence is interrupted by any intervening
host activity or improper timing between the steps the
If an error occurs during programming the EEABORTERR
flag is set in the PIR register. The EE programming time on
the Holt ADK-3220 development board using an Atmel
EEPROM is approximately 278ms.
HOLT INTEGRATED CIRCUITS
45
HI-3220
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
RECOMMENDED CONDITIONS
Operating Supply Voltage
-0.3 V to +5.0 V
Logic input voltage range
X
VDD....................................... 3.3 VDC ±5%
-0.3 V DC to +3.6 V
X
ARINC 429 input voltage
-120 V to +120 V
Power dissipation at 25°C
1.0 W
Reflow Solder Temperature
260°C
Junction Temperature
175°C
Storage Temperature
-65°C to +150°C
Operating Temperature Range
X
Industrial ......................... -40°C to +85°C
Extended ....................... -55°C to +125°C
NOTE: Stresses above absolute maximum ratings or
outside recommended operating conditions may cause
permanent damage to the device. These are stress
ratings only. Operation at the limits is not
recommended.
DC ELECTRICAL CHARACTERISTICS
Digital Pins
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
Operating Voltage
VDD
Supply Current
IDD
Min. Input Voltage
(HI)
Max. Input Voltage
VIH
CONDITION
Digital inputs
(LO)
VIL
Digital inputs
Pull-Up / Pull-Down Current
IPUD
See pin definitions table
Output Current (HI)
IOH
VOH = 0.8 VDD
MIN
TYP
MAX
3.15
3.30
3.45
V
75
mA
70%
UNITS
VDD
30
30%
VDD
100
µA
-6.0
mA
6.0
mA
90%
VDD
VDD = 3.15 - 3.45 V
Output Current (LO)
IOL
VOL = 0.4 V
VDD = 3.15 - 3.45 V
Min. Output Voltage
(HI)
VOH
IOUT = -1.0mA, Digital outputs
Max. Output Voltage
(LO)
VOL
IOUT = 1.0mA, Digital outputs
10%
VDD
Input Capacitance
CI
5
pF
Output Capacitance
CO
5
pF
ARINC 429 Receiver Inputs (ARXxx-40)
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). Measured at ARINC 429 bus with required 40KOhm
isolation resistors installed.
PARAMETER
Input Voltage
Input Resistance
ONE or ZERO
CONDITION
MIN
TYP
MAX
UNITS
VDIN
Differential input voltage
6.5
10
13
V
NULL
VNIN
Differential input voltage
2.5
V
Common mode
VCOM
With respect to GND
+/-5.0
V
ARXnP-40 to ARXnN-40
RDIFF
Supplies floating
Input to GND or VDD
RSUP
Supplies floating
Input Hysteresis
Input Capacitance
SYMBOL
VHYS
ARINC bus differential
CAD
ARINC single ended to GND
CAS
HOLT INTEGRATED CIRCUITS
46
0.5
90
kΩ
45
kΩ
1.0
V
5
10
pF
10
pF
HI-3220
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
SPI Host Bus Interface
HSCK clock period
HSC set-up time to first HSCK rising edge
HSC hold time after last HSCK falling edge
HSC inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI HMOSI Data hold time after HSCK rising edge
HMISO valid after HSCK falling edge
HMISO high-impedance after HSC inactive
tCYC
tCES
tCEH
tCPH
tDS
tDH
tDV
tCHZ
25
15
15
100
10
10
10
90
ns
ns
ns
ns
ns
ns
ns
ns
SERIAL INPUT TIMING DIAGRAM
t CPH
t CEH
t CYC
HSC
t CES
HSCLK
t DS
t DH
MSB
HMOSI
LSB
SERIAL OUTPUT TIMING DIAGRAM
t CPH
HSC
HSCLK
t CHZ
t DV
HMISO
Hi Impedance
MSB
LSB
Power Supply Recommended bypass capacitors (near the device)
Provide a 0.1µF ceramic bypass capacitor on GND and VDD power pins (2-4 capacitors).
Provide a single 22µF ceramic or tantalum bypass capacitor on any GND and VDD power pins.
HOLT INTEGRATED CIRCUITS
47
Hi Impedance
HI-3220
ORDERING INFORMATION
HI-322xPQ x x
PART
NUMBER
Blank
F
PART
NUMBER
PACKAGE
DESCRIPTION
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
LINE DRIVER
SLOPE CONTROL
INTERNAL
#
LINE
RX/TX
RECEIVERS Channels
3220PQ
80-PIN PLASTIC QFP (80PQTS)
Y
Y
16 / 8
3223PQ
52-PIN PLASTIC QFP (52PQS)
Y
Y
8/4
3225PQ
80-PIN PLASTIC QFP (80PQTS)
Y
N
16 / 8
PART
NUMBER
PACKAGE
DESCRIPTION
HI-322xPC x x
Blank
F
PART
NUMBER
NiPdAu
NiPdAu (Pb-free RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
LINE DRIVER
SLOPE CONTROL
3221PC
72-PIN PLASTIC QFN (72PCS)
N
Y
16 / 8
3222PC
48-PIN PLASTIC QFN (48PCS7)
N
Y
8/4
3223PC
64-PIN PLASTIC QFN (64PCS)
Y
Y
8/4
3226PC
72-PIN PLASTIC QFN (72PCS)
N
N
16 / 8
HOLT INTEGRATED CIRCUITS
48
INTERNAL
#
RX/TX
LINE
RECEIVERS Channels
HI-3220
REVISION HISTORY
Document
Rev.
Date
Description of Change
DS3220
New
A
01-12-18
05-01-18
B
10-15-18
C
12-14-18
D
03-04-19
E
03-11-19
F
G
H
08-22-19
03-04-2020
04-22-2020
J
K
07/24/2020
04/21/2021
Initial Release.
Add HI-3223 device and related package and ordering information. .
Correct typo in 80PTQS drawing. Correct other typos and add
additional clarification notes.
Add “Fully compliant to ARINC 429 Specification” to Features. Correct
typo in 3225PQ ordering information (slope control should be “Y”).
Update package lead finish. Correct other numerous typos.
Add ARINC input voltage to “Absolute Maximum Ratings Table”.
Correct typos.
Remove non-annunciated fault protection statement. Clarify pullup/pull-down resistor values when using external EEPROM. Correct
minor typos.
Update Note on pull-ups/pull-downs (p. 4) to make it consistent with
Note on p. 7 for HI-3225 and HI-3226.
Update Ordering Information for QFN lead finish to NiPdAu.
Correct typo in Ordering Information.
Correct typos in package pinouts (BMODE should be MODE). Correct
typo on p. 43, section “Register Direct Addressing”. Read register
range should be 0x8000 to 0x8087.
Clarify HI-3223 has integrated, lightning protected line receivers.
Clarify operation of SLP pins.
HOLT INTEGRATED CIRCUITS
49
PACKAGE DIMENSIONS
80 PIN PLASTIC QUAD FLAT PACK (PQFP)
millimeters (inches)
Package Type: 80PTQS
0.40
BSC
(0.0157)
10.00
BSC SQ
(0.394)
12.00
(0.472) BSC SQ
0.22 ± 0.05
(0.009 ± 0.002)
0.60 ± 0.15
(0.024 ± 0.006)
1.40 ± 0.05
(0.055 ± 0.002)
See Detail A
1.60 max
(0.0630)
0.10 ± 0.05
(0.004 ± 0.002)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
72-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
millimeters (inches)
Package Type: 72PCS
Electrically isolated heat
sink pad on bottom of
package
10.00
BSC
(0.394)
Connect to any ground or
power plane for optimum
thermal dissipation
5.95 ± 0.20
(0.234 ± 0.008)
0.50
BSC
(0.0197)
10.00
BSC
(0.394)
5.95 ± 0.20
(0.234 ± 0.008)
Top View
Bottom
View
0.20
typ
(0.008)
0.40 ± 0.05
(0.016 ± 0.002)
0.20
typ
(0.008)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
1.00
max
(0.039)
HOLT INTEGRATED CIRCUITS
50
PACKAGE DIMENSIONS
48-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
7.000
BSC
(0.276)
millimeters (inches)
Package Type: 48PCS7
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
5.550 ± 0.050
(0.218 ± 0.002)
0.50 BSC
(0.0197)
7.000
BSC
(0.276)
0.80
max
(0.031)
Bottom
View
5.550 ± 0.050
(0.218 ± 0.002)
Top View
0.250
typ
(0.010)
0.400 ± 0.050
(0.016 ± 0.002)
0.200
typ
(0.008)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
millimeters (inches)
Package Type: 64PCS
Electrically isolated heat
sink pad on bottom of
package
9.00
BSC
(0.354)
Connect to any ground or
power plane for optimum
thermal dissipation
7.25 ± 0.50
(0.285 ± 0.020)
0.50
BSC
(0.0197)
9.00
BSC
(0.354)
7.25 ± 0.50
(0.285 ± 0.020)
Top View
Bottom
View
0.25
typ
(0.10)
0.40 ± 0.10
(0.016 ± 0.004)
0.20
typ
(0.008)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
1.00
max
(0.039)
HOLT INTEGRATED CIRCUITS
51
PACKAGE DIMENSIONS
52-PIN PLASTIC QUAD FLAT PACK (PQFP)
millimeters (inches)
Package Type: 52PQS
0.65
BSC
(0.026)
13.200
BSC SQ
(.520)
10.000
BSC SQ
(0.394)
0.310 ± 0.090
(0.012 ± 0.004)
0.880 ± 0.150
(0.035 ± 0.006)
1.60
typ
(0.063)
0.20
min
(0.008)
See Detail A
2.70
MAX.
(0.106)
0.30
(0.012)R max
2.00 ± 0.20
(0.079 ± 0.008)
0.13
R min
(0.005)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
DETAIL A
HOLT INTEGRATED CIRCUITS
52
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