GD25WD40CEIGR

Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C DATASHEET 1 GD25WD40C/20C Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C CONTENTS 1. FEATURES ................................................................................................................................................................ 4 2. GENERAL DESCRIPTION ..................................................................................................................................... 5 3. MEMORY ORGANIZATION .................................................................................................................................. 8 4. DEVICE OPERATION ........................................................................................................................................... 10 5. DATA PROTECTION ............................................................................................................................................. 11 6. STATUS REGISTER ............................................................................................................................................... 12 7. COMMANDS DESCRIPTION............................................................................................................................... 13 7.1. WRITE ENABLE (WREN) (06H) ......................................................................................................................... 15 7.2. WRITE DISABLE (WRDI) (04H) ......................................................................................................................... 15 7.3. READ STATUS REGISTER (RDSR) (05H)............................................................................................................. 16 7.4. WRITE STATUS REGISTER (WRSR) (01H) .......................................................................................................... 16 7.5. READ DATA BYTES (READ) (03H)..................................................................................................................... 17 7.6. READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH)................................................................................ 17 7.7. DUAL OUTPUT FAST READ (3BH) ...................................................................................................................... 18 7.8. PAGE PROGRAM (PP) (02H)................................................................................................................................ 18 7.9. SECTOR ERASE (SE) (20H) ................................................................................................................................. 19 7.10. 32KB BLOCK ERASE (BE) (52H) ....................................................................................................................... 20 7.11. 64KB BLOCK ERASE (BE) (D8H) ...................................................................................................................... 20 7.12. CHIP ERASE (CE) (60/C7H)................................................................................................................................ 21 7.13. DEEP POWER-DOWN (DP) (B9H) ....................................................................................................................... 22 7.14. RELEASE FROM DEEP POWER-DOWN / READ DEVICE ID (ABH) ........................................................................ 22 7.15. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ........................................................................................ 23 7.16. READ IDENTIFICATION (RDID) (9FH) ................................................................................................................ 24 7.17. READ UNIQUE ID (4BH) .................................................................................................................................... 25 8. ELECTRICAL CHARACTERISTICS .................................................................................................................. 26 8.1. POWER-ON TIMING ....................................................................................................................................... 26 8.2. INITIAL DELIVERY STATE ............................................................................................................................ 26 8.3. ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 26 8.4. CAPACITANCE MEASUREMENT CONDITIONS ........................................................................................ 27 8.5. DC CHARACTERISTICS................................................................................................................................. 28 8.6. AC CHARACTERISTICS................................................................................................................................. 31 9. ORDERING INFORMATION ............................................................................................................................... 37 9.1. 10. VALID PART NUMBERS........................................................................................................................................ 38 PACKAGE INFORMATION ............................................................................................................................. 40 10.1. PACKAGE SOP8 150MIL .................................................................................................................................... 40 10.2. PACKAGE SOP8 208MIL .................................................................................................................................... 41 10.3. PACKAGE TSSOP8 173MIL ............................................................................................................................... 42 2 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 10.4. PACKAGE DIP8 300MIL ..................................................................................................................................... 43 10.5. PACKAGE USON8 (1.5*1.5MM) ......................................................................................................................... 44 10.6. PACKAGE USON8 (3*2MM, THICKNESS 0.45MM) ............................................................................................... 45 10.7. PACKAGE WLCSP .............................................................................................................................................. 46 11. REVISION HISTORY ........................................................................................................................................ 47 3 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 1. FEATURES ◆ 4M/2M-bit Serial Flash ◆ Fast Program/Erase Speed -512K/256K-byte -Page Program time: 1.6ms typical -256 bytes per programmable page -Sector Erase time: 150ms typical -Block Erase time: 0.5/0.8s typical ◆ Standard, Dual Output -Chip Erase time: 6/3s typical -Standard SPI: SCLK, CS#, SI, SO, WP# -Dual Output: SCLK, CS#, IO0, O1, WP# ◆ Flexible Architecture -Uniform Sector of 4K-byte ◆ Clock Frequency -Uniform Block of 32/64K-byte -100MHz for fast read on 3.0~3.6V power supply ◆ ◆ Dual Output Data Transfer up to 160Mbits/s -70MHz for fast read on 2.1~3.0V power supply ◆ Low Power Consumption -0.1uA typical standby current -0.1uA typical power down current Dual Output Data Transfer up to 120Mbits/s -50MHz for fast read on 1.65~2.1V power supply ◆ ◆ Dual Output Data Transfer up to 80Mbits/s Advanced Security Features -128-bit Unique ID for each device ◆ Software/Hardware Write Protection -Write protect all/portion of memory via software ◆ -Enable/Disable protection with WP# Pin ◆ Single Power Supply Voltage -Full voltage range: 1.65~3.6V Minimum 100,000 Program/Erase Cycles ◆ Package option -SOP8 150mil ◆ Data Retention -SOP8 208mil -20-year data retention typical -TSSOP8 173mil -DIP8 300mil -USON8 1.5*1.5mm -USON8 3*2mm -WLCSP 4 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 2. GENERAL DESCRIPTION The GD25WD40C/20C (4M/2M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual Output: Serial Clock, Chip Select, Serial Data I/O0 (SI), O1 (SO). The Dual Output data is transferred with maximum speed of 160Mbits/s. CONNECTION DIAGRAM CS# 1 8 VCC CS# 1 SO (O1) 2 7 NC SO (O1) 2 WP# 3 6 SCLK WP# VSS 4 5 SI (IO0) VSS Top View 8 VCC 7 NC 3 6 SCLK 4 5 SI (IO0) Top View 8–LEAD SOP/TSSOP/DIP 8–LEAD USON TOP VIEW BOTTOM VIEW A1 A2 A2 A1 VCC CS# CS# VCC B1 B2 B2 B1 SCLK SO (IO1) SO (IO1) SCLK C1 C2 C2 C1 SI (IO0) VSS VSS SI (IO0) WLCSP PIN DESCRIPTION Table 1. Pin Description for SOP/TSSOP/DIP/USON package Pin Name I/O Description CS# I Chip Select Input SO (O1) O Data Output (Data Output 1) WP# I Write Protect Input Ground VSS SI (IO0) I/O Data Input (Data Input Output 0) SCLK I Serial Clock Input NC No Connection VCC Power Supply 5 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C Table 2. Pin Description for WLCSP package Pin Name Ball Name I/O Description CS# A2 I Chip Select Input SO (IO1) B2 I/O Data Output (Data Input Output 1) VSS C2 SI (IO0) C1 I/O Data Input (Data Input Output 0) SCLK B1 I Serial Clock Input VCC A1 Ground Power Supply Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. 6 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C BLOCK DIAGRAM Write Control Logic Status Register SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Protect Logic and Row Decode WP# Flash Memory Column Decode And 256-Byte Page Buffer SI(IO0) SO(O1) Byte Address Latch/Counter 7 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 3. MEMORY ORGANIZATION GD25WD40C Each device has Each block has Each sector has Each page has 512K 64/32K 4K 256 bytes 2K 256/128 16 - pages 128 16/8 - - sectors 8/16 - - - blocks Each device has Each block has Each sector has Each page has 256K 64/32K 4K 256 bytes 1K 256/128 16 - pages 64 16/8 - - sectors 4/8 - - - blocks GD25WD20C UNIFORM BLOCK SECTOR ARCHITECTURE GD25WD40C 64K Bytes Block Sector Architecture Block 7 6 …… …… 2 1 0 Sector Address range 127 07F000H 07FFFFH …… …… …… 112 070000H 070FFFH 111 06F000H 06FFFFH …… …… …… 96 060000H 060FFFH …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 8 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C GD25WD20C 64K Bytes Block Sector Architecture Block 3 2 1 0 Sector Address range 63 03F000H 03FFFFH …… …… …… 48 030000H 030FFFH 47 02F000H 02FFFFH …… …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH 9 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 4. DEVICE OPERATION SPI Mode Standard SPI The GD25WD40C/20C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25WD40C/20C supports Dual Output operation when using the “Dual Output Fast Read” (3BH) commands. These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using the Dual Output command the SI and SO pins become bidirectional I/O pins: IO0 and O1. 10 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 5. DATA PROTECTION The GD25WD40C/20C provides the following data protection methods: Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will ◆ reset to 0 in the following situations: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected memory area ◆ which is read-only and unalterable. ◆ Hardware Protection Mode: WP# goes low to protect the BP0~BP2 bits and SRP bits. ◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI. ◆ Table3(a) GD25WD40C Protected area size Status Register Content Memory Content BP2 BP1 BP0 Blocks Addresses Density Portion 0 0 0 NONE NONE NONE NONE 0 0 1 Sector 0 to 125 000000H-07DFFFH 504KB Lower126/128 0 1 0 Sector 0 to 123 000000H-07BFFFH 496KB Lower 124/128 0 1 1 Sector 0 to 119 000000H-077FFFH 480KB Lower 120/128 1 0 0 Sector 0 to 111 000000H-06FFFFH 448KB Lower 112/128 1 0 1 Sector 0 to 95 000000H-05FFFFH 384KB Lower 96/128 1 1 0 Sector 0 to 63 000000H-03FFFFH 256KB Lower 64/128 1 1 1 All 000000H-07FFFFH 512KB ALL Density Portion Table3(b) GD25WD20C Protected area size Status Register Content BP2 Memory Content BP1 BP0 Blocks Addresses 0 0 0 NONE NONE NONE NONE 0 0 1 Sector 0 to 61 000000H-03DFFFH 248KB Lower 62/64 0 1 0 Sector 0 to 59 000000H-03BFFFH 240KB Lower 60/64 0 1 1 Sector 0 to 55 000000H-037FFFH 224KB Lower 56/64 1 0 0 Sector 0 to 47 000000H-02FFFFH 192KB Lower 48/64 1 0 1 Sector 0 to 31 000000H-01FFFFH 128KB Lower 32/64 1 1 X All 000000H-03FFFFH 256KB ALL 11 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 6. STATUS REGISTER S7 S6 S5 S4 S3 S2 S1 S0 SRP Reserved Reserved BP2 BP1 BP0 WEL WIP The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress. when WIP bit is cleared to 0, it means the device is not in program/erase/write status register progress. The default value of WIP is 0. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. The default value of WEL is 0. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table3).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, BP0) bits are all 0. The default value of BP2:0 are 0s. SRP bit The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status Register(SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is not execution. The default value of SRP is 0. 12 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device by the host system, with the most significant bit first. On the first rising edge of SCLK after CS# is driven low, the one-byte command code must be shifted into the device, with the most significant bit first on SI, and each bit being latched on the rising edges of SCLK. See Table4, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or data bytes, or dummy bytes. CS# must be driven high after the last bit of the command sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to deselected status. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, which means the clock pulse number should be an exact multiple of eight. Otherwise the command is rejected to executed. Especially for Page Program command, if at any time the input end is not a completed byte, nothing will be written into the memory array, neither would WEL bit be reset. Table4. Commands Command Name Byte 1 Byte 2 Write Enable Write Disable Read Status Register Write Status Register Read Data Fast Read Dual Output Fast Read Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase Deep Power-Down Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Manufacturer/ Device ID Read Identification 06H 04H 05H 01H 03H 0BH 3BH (S7-S0) S7-S0 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 (D7-D0) dummy dummy (Next byte) (D7-D0) (D7-D0)(1) A23-A16 A23-A16 A23-A16 A23-A16 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 D7-D0 Next byte dummy dummy dummy (DID7DID0) 90H 00H 00H 00H (MID7MID0) 9FH (MID7MID0) (JDID15JDID8) (JDID7JDID0) Read Unique ID 4BH 00H 00H 00H 02H 20H 52H D8H C7/60 H B9H ABH Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes (continuous) (continuous) (continuous) (continuous) (continuous) ABH (DID7DID0) (continuous) dummy (UID7UID0) NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) O1 = (D7, D5, D3, D1) 13 (continuous) (continuous) Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C TABLE OF ID DEFINATION: GD25WD40C Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH C8 64 13 90H C8 12 ABH 12 GD25WD20C Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH C8 64 12 90H C8 11 ABH 11 14 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit to 1. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes high. Figure1. Write Enable Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 06H High-Z SO 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit to 0. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. The Write Disable command sequence: CS# goes lowSending the Write Disable command CS# goes high. Figure2. Write Disable Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 Command 04H High-Z 15 6 7 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 7.3. Read Status Register (RDSR) (05H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. Figure3. Read Status Register Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 Command 05H High-Z S7~S0 out 5 4 3 2 MSB 1 0 7 6 5 S7~S0 out 4 3 2 1 0 7 MSB 7.4. Write Status Register (WRSR) (01H) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write Enable (WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can be accepted. The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (DI). The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (the duration is tW) is initiated. While the Write Status Register cycle is in progress, reading Status Register to check the Write In Progress (WIP) bit is achievable. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the completion of the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, which are utilized to define the size of the read-only area. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode. The Write Status Register (WRSR) instruction is not executed once enter into the Hardware Protected Mode. 16 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C Figure4. Write Status Register Sequence Diagram CS# 1 0 SCLK 2 3 4 5 6 7 8 Command SI 9 10 11 12 13 14 15 Status Register in 7 01H MSB SO 4 5 6 3 2 1 0 High-Z 7.5. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure5. Read Data Bytes Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 SCLK 24-bit address Command SI SO 03H High-Z 23 22 21 3 2 1 0 MSB MSB 7 6 5 Data Out1 4 3 2 1 Data Out2 0 7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fC, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. 17 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C Figure6. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 0BH 3 23 22 21 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 7 6 MSB SO Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 7.7. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure7. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure7. Dual Output Fast Read Sequence Diagram CS# 0 1 2 3 4 5 6 8 7 9 10 28 29 30 31 SCLK 24-bit address Command SI SO 3 23 22 21 3BH 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks SI SO 6 4 2 0 6 4 2 0 6 Data Out1 Data Out2 7 5 3 1 7 5 3 1 MSB MSB 7 7.8. Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. 18 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI  at least 1 byte data on SI  CS# goes high. The command sequence is shown in Figure8. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command is not executed when it is applied to a page protected by the Block Protect (BP2, BP1, BP0). Figure8. Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 24-bit address 23 22 21 3 2 Data Byte 1 1 0 7 MSB 6 5 4 3 2 1 0 2078 2079 6 2076 7 2077 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB CS# 2075 02H 2074 SI 1 0 SCLK Data Byte 3 Data Byte 2 SI 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 MSB 2 Data Byte 256 1 0 5 4 3 2 MSB 7.9. Sector Erase (SE) (20H) The Sector Erase (SE) command is for erasing the all data of the specific sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure9. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status 19 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP2, BP1, BP0) bit (see Table3) is not executed. Figure9. Sector Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 29 30 31 24 Bits Address 23 22 MSB 20H 2 1 0 7.10. 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure10. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table3) is not executed. Figure10. 32KB Block Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 9 29 30 31 24 Bits Address Command 52H 8 23 22 MSB 2 1 0 7.11. 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the 20 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C sequence. The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure11. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table3) is not executed. Figure11. 64KB Block Erase Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 Command SI 29 30 31 24 Bits Address 2 23 22 MSB D8H 1 0 7.12. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The command sequence is shown in Figure12. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are all 0. The Chip Erase (CE) command is not executed if any sector is under protection. Figure12. Chip Erase Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 Command 60H or C7H 21 6 7 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 7.13. Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to enter the lowest consumption mode (the Deep Power-Down Mode). Unlike deselecting the device by driving CS# high, or entering into the Standby Mode (if there is no internal cycle currently in progress), the Deep Power-Down Mode provides an extra software protection mechanism while the device is not in active use. The only access to this mode is by executing the Deep Power-Down (DP) command. Since in the Deep Power-Down mode, the device ignores all Write, Program and Erase commands. Once the device is in the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS# must be driven low for the entire duration of the sequence. The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high. The command sequence is shown in Figure13. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep PowerDown (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure13. Deep Power-Down Sequence Diagram CS# SCLK SI tDP 0 1 2 3 4 5 6 7 Command Stand-by mode Deep Power-down mode B9H 7.14. Release from Deep Power-Down / Read Device ID (ABH) The Release from Power-Down and Read Device ID command is a multi-purpose command, which can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. When used to release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure14. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other comm and are accepted. The CS# pin must keep high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure15. The Device ID value for the GD25WD40C/20C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure15, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other 22 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C command will be accepted. If the Release from Power-Down and Read Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure14. Release Power-Down Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 t RES1 7 Command SI ABH Deep Power-down mode Stand-by mode Figure15. Release Power-Down and Read Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 SCLK SI SO ABH High-Z t RES2 3 Dummy Bytes Command 23 22 2 1 0 MSB 7 MSB 6 Device ID 5 4 3 2 1 0 Deep Power-down Mode Stand-by Mode 7.15. Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After that, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure16. If the 24-bit address is initially set to 000001H, the Device ID will be read first. 23 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C Figure16. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 90H 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI 7 SO 6 Manufacturer ID 5 4 3 2 1 MSB Device ID 0 7 6 5 4 3 2 1 0 MSB 7.16. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The command sequence is shown in Figure17. The Read Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure17. Read Identification ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 SCLK 9FH Command SI SO Manufacturer ID 5 4 3 2 1 MSB CS# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI SO 7 MSB 6 5 4 3 2 1 Memory Type JDID15-JDID8 0 7 MSB 24 6 5 4 3 2 Capacity JDID7-JDID0 1 0 0 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 7.17. Read Unique ID (4BH) The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3-Byte Address (000000H) Dummy Byte128bit Unique ID Out CS# goes high. Figure18. Read Unique ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 23 22 21 4BH 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 7 6 MSB 25 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Figure19. Power-On Timing Sequence Diagram VCC VCC(max.) Chip Selection is not allowed VCC(min.) tVSL VPWD(max.) Full Device Access Allowed tPWD Time Table 5. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min. tVSL VCC (min.) to device operation VWI Write Inhibit Voltage VPWD VCC voltage needed to below VPWD for ensuring initialization will occur tPWD The minimum duration for ensuring initialization will occur Max. 0.3 1 300 Unit ms 1.55 V 0.5 V us 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 8.3. ABSOLUTE MAXIMUM RATINGS Parameter Value Ambient Operating Temperature -40 to 85 Unit ℃ -40 to 105 -40 to 125 ℃ Storage Temperature -65 to 150 Applied Input/Output Voltage -0.6 to VCC+0.4 V Transient Input/Output Voltage (note: overshoot) -2.0 to VCC+2.0 V -0.6 to 4.2 V VCC 26 Uniform Sector Standard and Dual Serial Flash GD25WD40C/20C Figure20. Maximum Negative/positive Overshoot Diagram Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns 8.4. CAPACITANCE MEASUREMENT CONDITIONS Symbol Parameter Min Typ. Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 pF Input Rise And Fall time 5 ns Input Pulse Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure 21. Input Test Waveform and Measurement Level Input timing reference level 0.8VCC 0.7VCC 0.1VCC 0.2VCC Output timing reference level AC Measurement Level Note: Input pulse rise and fall time are 80MHz) tested at VCC = 3.3V. Icc3 (80MHz) tested at VCC = 3.3V. Icc3 (80MHz) tested at VCC = 3.3V. Icc3 (