Rev.4.2_00
S-24CS64A
2-WIRE CMOS SERIAL E2PROM
The S-24CS64A is a 2-wired, low power and wide
range operation 64 K-bit E2PROM organized as 8192
words × 8 bits.
Page write and sequential read are available.
Features
• Low power consumption Standby : 5.0 µA Max. (VCC = 5.5 V)
Read :
0.8 mA Max. (VCC = 5.5 V)
• Operating voltage range Read :
1.8 to 5.5 V
Write :
2.7 to 5.5 V
• Page write :
32 bytes / page
• Sequential read
• Operating Frequency :
400 kHz (VCC = 2.7 to 5.5 V)
• Write disable function when power supply voltage is low
• Endurance:
106 cycles / word*1 (at +25°C) write capable,
105 cycles / word*1 (at +85°C)
*1. For each address (Word: 8 bits)
• Data retention:
10 years (after rewriting 105 cycles / word at +85°C)
• Write protection :
100 %
• Lead-free products
Packages
Package name
8-Pin SOP (JEDEC)
8-Pin TSSOP
WLP
Drawing code
Package
Tape
Reel
FJ008-A
FJ008-D
FJ008-D
FT008-A
FT008-E
FT008-E
Please contact our sales office regarding the product with WLP package.
Caution This product is intended to use in general electronic devices such as consumer electronics,
office equipment, and communications devices. Before using the product in medical
equipment or automobile equipment including car audio, keyless entry and engine control
unit, contact to SII is indispensable.
Seiko Instruments Inc.
1
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Pin Configurations
8-Pin SOP (JEDEC)
Top view
Table 1
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
Figure 1
S-24CS64A0I-J8T1G
Pin No.
1
2
3
4
5
6
Symbol
A0
A1
A2
GND
SDA
SCL
7
WP
8
VCC
Description
Slave address input
Slave address input
Slave address input
Ground
Serial data input / output
Serial clock input
Write protection input
Connected to VCC: Protection valid
Connected to GND: Protection invalid
Power supply
Remark See Dimensions for details of the package drawings.
8-Pin TSSOP
Top view
A0
A1
A2
GND
8
7
6
5
1
2
3
4
Figure 2
S-24CS64A0I-T8T1G
Table 2
VCC
WP
SCL
SDA
Pin No.
1
2
3
4
5
6
Symbol
A0
A1
A2
GND
SDA
SCL
7
WP
8
VCC
Description
Slave address input
Slave address input
Slave address input
Ground
Serial data input / output
Serial clock input
Write protection input
Connected to VCC: Protection valid
Connected to GND: Protection invalid
Power supply
Remark See Dimensions for details of the package drawings.
2
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
WLP
Bottom view
2
1
3
A0 VCC WP
8
4
SCL
A1
7
5
6
A2 GND SDA
Figure 3
Table 3
Pin No.
1
2
Symbol
A0
VCC
3
WP
4
5
6
7
8
SCL
SDA
GND
A2
A1
Description
Slave address input
Power supply
Write protection input
Connected to VCC: Protection valid
Connected to GND: Protection invalid
Serial clock input
Serial data input / output
Ground
Slave address input
Slave address input
S-24CS64A0I-H8Tx
Remark Please contact our sales office regarding the product with WLP package.
Seiko Instruments Inc.
3
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Block Diagram
WP
SCL
Start / Stop
Detector
SDA
Serial Clock
Controller
VCC
GND
Voltage Detector
High-Voltage Generator
LOAD
COMP
Device Address
Comparator
Data Register
LOAD
INC
A2
R/W
A1
A0
Address
Counter
Y Decoder
2
E PROM
Selector
Data Output
ACK Output
Controller
DIN
DOUT
Figure 4
4
X Decoder
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Absolute Maximum Ratings
Table 4
Item
Symbol
Ratings
Unit
V
Power supply voltage
VCC
−0.3 to +7.0
V
Input voltage
VIN
−0.3 to +7.0
Output voltage
VOUT
V
−0.3 to +7.0
Operating ambient temperature
Topr
°C
−40 to +85
°C
Storage temperature
Tstg
−65 to +150
Caution The absolute maximum ratings are rated values exceeding which the
product could suffer physical damage. These values must therefore not
be exceeded under any conditions.
Recommended Operating Conditions
Item
Symbol
Power supply voltage
VCC
High level input voltage
VIH
Low level input voltage
VIL
Table 5
Conditions
Read Operation
Write Operation
VCC = 2.5 to 5.5 V
VCC = 1.8 to 2.5 V
VCC = 2.5 to 5.5 V
VCC = 1.8 to 2.5 V
Min.
1.8
2.7
0.7×VCC
0.8×VCC
0.0
0.0
Typ.
Max.
5.5
5.5
VCC
VCC
0.3×VCC
0.2×VCC
Unit
V
V
V
V
V
V
Pin Capacitance
Table 6
Item
Symbol
Input capacitance
CIN
Input / output capacitance CI / O
(Ta = 25°C, f = 1.0 MHz, VCC = 5 V)
Conditions
Min. Typ. Max. Unit
—
—
10
pF
VIN = 0 V (SCL, A0, A1, A2, WP)
—
—
10
pF
VI / O = 0 V (SDA)
Endurance
Table 7
Item
Symbol Operation temperature
Endurance
NW
−40 to +85°C
*1. For each address (Word: 8 bits)
Min.
105
Seiko Instruments Inc.
Typ.
—
Max.
—
Unit
cycles / word*1
5
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
DC Electrical Characteristics
Table 8
VCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V VCC = 1.8 to 2.7 V
Symbol Conditions
Unit
f = 400 kHz
f = 100 kHz
f = 100 kHz
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Item
Current consumption
(READ)
Current consumption
(WRITE)
Item
0.8
0.5
0.3
mA
ICC2
4.0
3.0
mA
Symbol
Standby current consumption ISB
Input leakage current
ILI
Output leakage current
ILO
Low level output voltage
VOL
Current address hold voltage
VAH
6
ICC1
Conditions
VIN = VCC or GND
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3.2 mA
IOL = 1.5 mA
Table 9
VCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V VCC = 1.8 to 2.7 V
Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
5.0
3.0
3.0 µA
0.1
1.0 µA
0.1 1.0
0.1 1.0
0.1
1.0 µA
0.1 1.0
0.1 1.0
V
0.4
0.3
0.3
0.3
V
1.5
1.5
5.5
4.5 1.5
2.7
V
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
AC Electrical Characteristics
VCC
Table 10 Measurement Conditions
Input pulse voltage
0.1×VCC to 0.9×VCC
Input pulse rising / falling time 20 ns
Output judgement voltage
0.5×VCC
Output load
100 pF+ Pull-up resistor 1.0 kΩ
R=1.0 kΩ
SDA
C=100 pF
Figure 5 Output Load Circuit
Item
Symbol
SCL clock frequency
SCL clock time “L”
SCL clock time “H”
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL, SDA rising time
SCL, SDA falling time
Bus release time
Noise suppression time
fSCL
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tI
Table 11
VCC = 4.5 to 5.5 V
Min. Typ. Max.
0
400
1.0
0.9
0.1
0.9
50
0.6
0.6
100
0
0.6
0.3
0.3
1.3
50
tF
tHIGH
VCC = 2.7 to 4.5 V
Min. Typ. Max.
0
400
1.0
0.9
0.1
0.9
50
0.6
0.6
100
0
0.6
0.3
0.3
1.3
100
tLOW
VCC = 1.8 to 2.7 V
Min. Typ. Max.
0
100
4.7
4.0
0.1
3.5
100
4.7
4.0
200
0
4.0
1.0
0.3
4.7
100
Unit
kHz
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
µs
µs
ns
tR
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 6 Bus Timing
Seiko Instruments Inc.
7
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Item
Write time
Rev.4.2_00
Table 12
VCC = 2.7 to 5.5 V
Symbol
Min.
Typ.
Max.
tWR
—
6.0
10.0
Unit
ms
tWR
SCL
SDA
D0
Stop Condition
Write data
Acknowledge
Figure 7 Write Cycle Timing
8
Seiko Instruments Inc.
Start Condition
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Pin Functions
1. A0, A1 and A2 (Slave Address Input) Pins
The slave address is assigned by connecting pins A0, A1 and A2 to the GND or to the VCC respectively.
One of the eight different slave address can be assigned by the combination of pins A0, A1 and A2.
The given slave address, which is compared with the slave address transmitted from the master device, is
used to select the one among the multiple devices connected to the bus. The address input pin should be
connected to the GND or to the VCC.
2. SDA (Serial Data Input / Output) Pin
The SDA pin is used for bi-directional transmission of serial data. It consists of a signal input pin and an
Nch open-drain output pin.
The SDA line is usually pulled up to the VCC, and OR-wired with other open-drain or open-collector output
devices.
3. SCL (Serial Clock Input) Pin
The SCL pin is used for serial clock input. Since signals are processed at the rising or falling edge of the
SCL clock input signal, attention should be paid to the rising time and falling time to conform to the
specifications.
4. WP (Write Protection Input) Pin
The write protection is enabled by connecting the WP pin to the VCC. When there is no need for write
protection, connect the pin to the GND.
Seiko Instruments Inc.
9
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Operation
1. Start Condition
Start is identified by a high to low transition of the SDA line while the SCL line is stable at high.
Every operation begins from a start condition.
2. Stop Condition
Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high.
When a device receives a stop condition during a read sequence, the read operation is interrupted, and
the device enters standby mode.
When a device receives a stop condition during a write sequence, the reception of the write data is halted,
and the E2PROM initiates a write cycle.
tSU.STA
tSU.STO
tHD.STA
SCL
SDA
Start Condition
Figure 8 Start / Stop Conditions
10
Seiko Instruments Inc.
Stop Condition
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
3. Data Transmission
Changing the SDA line while the SCL line is low, data is transmitted.
Changing the SDA line while the SCL line is high, a start or stop condition is recognized.
tSU.DAT
tHD.DAT
SCL
SDA
Figure 9 Data Transmission Timing
4. Acknowledge
The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down
the SDA line to acknowledge the receipt of the 8-bit data.
When a internal write cycle is in progress, the device does not generate an acknowledge.
SCL
2
(E PROM Input)
1
8
9
SDA
(Master Output)
SDA
(E PROM Output)
2
Acknowledge
Output
Start Condition
tAA
tDH
Figure 10 Acknowledge Output Timing
Seiko Instruments Inc.
11
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
5. Device Addressing
To start communication, the master device on the system generates a start condition to the bus line. Next,
the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus.
The 4 most significant bits of the device address are called the “Device Code”, and are fixed to “1010”.
Successive 3 bits are called the “Slave Address”. These 3 bits are used to identify a device on the system
bus and are compared with the predetermined value which is defined by the address input pins (A0, A1
and A2). When the comparison result matches, the slave device responds with an acknowledge during the
9th clock cycle.
Device Code
1
0
1
Slave Address
0
A2
A1
A0
R/W
MSB
LSB
Figure 11 Device Address
6. Write
6.1 Byte Write
When the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following
a start condition, the E2PROM acknowledges it. The E2PROM then receives the upper 8 bits of the word
address and responds with an acknowledge. And the E2PROM receives the lower 8 bits of the word
address and responds with an acknowledge. After the E2PROM receives 8-bit write data and responds
with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed
memory.
During the write cycle all operations are forbidden and no acknowledge is generated.
S
T
A
R
T
SDA LINE
W
R
I
T
E
DEVICE
ADDRESS
1
M
S
B
0
1
0
A2 A1 A0
0
L R A
S / C
B W K
UPPER WORD ADDRESS
X
X
X W12W11W10W9 W8
LOWER WORD ADDRESS
DATA
W7 W6 W5 W4 W3 W2 W1 W0
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
A
A
C
C
K
K
S
T
O
P
A
C
K
ADR INC
(ADDRESS INCREMENT)
Figure 12 Byte Write
12
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
6.2 Page Write
The page write mode allows up to 32 bytes to be written in a single wire operation in the S-24CS64A.
Basic data transmission procedure is the same as that in the “Byte Write”. However, when the E2PROM
receives 8-bit write data which corresponds to the page size, the page can be written.
When the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “0”,
following a start condition, it generates an acknowledge. Then the E2PROM receives the upper 8 bits of
the word address and responds with an acknowledge. And the E2PROM receives the lower 8 bits of the
word address and responds with an acknowledge. After the E2PROM receives 8-bit write data and
responds with an acknowledge, it receives 8-bit write data corresponding to the next word address, and
generates an acknowledge. The E2PROM repeats reception of 8-bit write data and generation of
acknowledge in succession. The E2PROM can receive as many write data as the maximum page size.
Receiving a stop condition initiates a write cycle of the area starting from the designated memory address
and having the page size equal to the received write data.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
DEVICE
ADDRESS
1
M
S
B
0
1
0
A2 A1 A0
0
L R A
S / C
B W K
DATA (n)
UPPER WORD ADDRESS (n) LOWER WORD ADDRESS (n)
X
X
X W12W11W10W9 W8
D7
W7 W6 W5 W4 W3 W2 W1 W0
A
C
K
A
C
K
S
T
O
P
DATA (n+x)
D7
D0
A
C
K
ADR INC
D0
A
C
K
ADR INC
Figure 13 Page Write
The lower 5 bits of the word address are automatically incremented every time when the E2PROM
receives 8-bit write data. If the size of the write data exceeds 32 bytes, the upper 8 bits of the word
address remain unchanged, and the lower 5 bits are rolled over and previously received data will be
overwritten.
Seiko Instruments Inc.
13
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
6.3 Write Protection
Write protection is available in the S-24CS64A. When the WP pin is connected to the VCC, write operation
to memory area is forbidden at all.
When the WP pin is connected to the GND, the write protection is invalid, and write operation in all
memory area is available.
Fix the level of the WP pin from the rising edge of SCL for loading the last write data (D0) until the end of
the write time (10 ms max.). If the WP pin changes during this time, the address data being written at this
time is not guaranteed.
There is no need for using write protection, the WP pin should be connected to the GND. The write
protection is valid in the operating voltage range.
tWR
SCL
D0
SDA
Write Data
Acknowledge
Stop
Condition
Start
Condition
WP
WP Pin Fixed Period
Figure 14 WP Pin Fixed Period
6.4 Acknowledge Polling
Acknowledge polling is used to know the completion of the write cycle in the E2PROM.
After the E2PROM receives a stop condition and once starts the write cycle, all operations are forbidden
and no response is made to the signal transmitted by the master device.
Accordingly the master device can recognize the completion of the write cycle in the E2PROM by
detecting a response from the slave device after transmitting the start condition, the device address and
the read / write instruction code to the E2PROM, namely to the slave devices.
That is, if the E2PROM does not generate an acknowledge, the write cycle is in progress and if the
E2PROM generates an acknowledge, the write cycle has been completed.
Keep the level of the WP pin fixed until acknowledge is confirmed.
It is recommended to use the read instruction “1” as the read / write instruction code transmitted by the
master device.
14
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
7. Read
7.1 Current Address Read
Either in writing or in reading the E2PROM holds the last accessed memory address, internally
incremented by one. The memory address is maintained as long as the power voltage is higher than the
current address hold voltage VAH.
The master device can read the data at the memory address of the current address pointer without
assigning the word address as a result, when it recognizes the position of the address pointer in the
E2PROM. This is called “Current Address Read”.
In the following the address counter in the E2PROM is assumed to be “n”.
When the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1”
following a start condition, it responds with an acknowledge.
Next an 8-bit data at the address “n” is sent from the E2PROM synchronous to the SCL clock. The
address counter is incremented at the falling edge of the SCL clock for the 8th bit data, and the content of
the address counter becomes n+1.
The master device outputs stop condition not an acknowledge, the reading of E2PROM is ended.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
R
E
A
D
1 0 1 0 A2 A1 A0 1
M
S
B
NO ACK from
Master Device
S
T
O
P
D7 D6 D5 D4 D3 D2 D1 D0
L R A
S / C
B W K
DATA
ADR INC
Figure 15 Current Address Read
Attention should be paid to the following point on the recognition of the address pointer in the E2PROM.
In the read operation the memory address counter in the E2PROM is automatically incremented at every
falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand,
the upper 8 bits of the memory address are left unchanged and are not incremented at the falling edge of
the SCL clock for the 8th bit of the received data.
Seiko Instruments Inc.
15
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
7.2 Random Read
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “0”
following a start condition, it responds with an acknowledge. The E2PROM then receives an 8-bit upper
word address and responds with an acknowledge. Next the E2PROM then receives an 8-bit lower word
address and responds with an acknowledge. The memory address is loaded to the address counter in the
E2PROM by these operations. Reception of write data does not follow in a dummy write whereas reception
of write data follows in a byte write and in a page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device
can read the data starting from the arbitrary memory address by transmitting a new start condition and
performing the same operation in the current address read.
That is, when the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to
“1”, following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted
from the E2PROM in synchronous to the SCL clock. The master device outputs stop condition not an
acknowledge, the reading of E2PROM is ended.
S
T
A
R
T
SDA
LINE
DEVICE
ADDRESS
W
R
I
T
E
1 0 1 0 A2 A1 A0 0
M
S
B
LOWER WORD ADDRESS
UPPER WORD ADDRESS
X
X
X
A
C
K
A
C
K
DUMMY WRITE
Figure 16 Random Read
16
DEVICE
ADDRESS
R
E
A
D
1 0 1 0 A2A1 A0 1
W7 W6 W5 W4 W3 W2 W1 W0
X W12W11W10 W9 W8
L R A
S / C
B W K
S
T
A
R
T
Seiko Instruments Inc.
M
S
B
L R A
S / C
B W K
NO ACK from
Master Device
DATA
S
T
O
P
下図へ続く
D7 D6
D5 D4 D3 D2 D1 D0
ADR INC
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
7.3 Sequential Read
When the E2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1”
following a start condition both in current and random read operations, it responds with an acknowledge.
An 8-bit data is then sent from the E2PROM synchronous to the SCL clock and the address counter is
automatically incremented at the falling edge of the SCL clock for the 8th bit data.
When the master device responds with an acknowledge, the data at the next memory address is
transmitted. Response with an acknowledge by the master device has the memory address counter in the
E2PROM incremented and makes it possible to read data in succession. This is called “Sequential Read”.
The master device outputs stop condition not an acknowledge, the reading of E2PROM is ended.
Data can be read in succession in the sequential read mode. When the memory address counter reaches
the last word address, it rolls over to the first memory address.
NO ACK from
Master Device
R
E
DEVICE
ADDRESS A
D
SDA
LINE
1
R A
/ C
W K
A
C
K
A
C
K
D7
D0
D7
D0
D7
DATA (n+1)
DATA(n)
ADR INC
S
T
O
P
A
C
K
D0
DATA (n+2)
ADR INC
D0
D7
DATA (n+x)
ADR INC
ADR INC
Figure 17 Sequential Read
Seiko Instruments Inc.
17
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
8. Address Increment Timing
The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the
read data in read operation and the the falling edge of the SCL clock for the 8th bit of the received data in
write operation.
SCL
SDA
8
9
R / W=1
ACK Output
1
8
D7 Output
9
D0 Output
Address Increment
Figure 18 Address Increment Timing in Reading
SCL
8
SDA
9
R / W=0
ACK Output
1
8
D7 Input
D0 Input
9
ACK Output
Address Increment
Figure 19 Address Increment Timing in Writing
Write Inhibition Function at Low Power Voltage
The S-24CS64A have a detection circuit for low power voltage. The detection circuit cancels a write
instruction when the power voltage is low or the power switch is on. The detection voltage is 1.85 V
typically and the release voltage is 1.95 V typically, the hysteresis of approximate 0.1 V thus exists. (See
Figure 20.)
When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition.
When the power voltage lowers during a data transmission or a write operation, the date at the address of
the operation is not assured.
Hysteresis width
0.1 V approximately
Power supply voltage
Release voltage (+VDET)
1.95 V typ.
Detection voltage (-VDET)
1.85 V typ.
Write Instruction
cancel
Figure 20 Operation at low power voltage
18
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Using S-24CS64A
1. Adding a pull-up resistor to SDA I/O pin and SCL input pin
Add a 1 to 5 kΩ pull-up resistor to the SCL input pin*1 and the SDA I/O pin in order to enable the functions
of the I2C-bus protocol. Normal communication cannot be provided without a pull-up resistor.
*1. When the SCL input pin of the E2PROM is connected to a tri-state output pin of the microprocessor,
connect the same pull-up resistor to prevent a high impedance status from being input to the SCL
input pin.
This protects the E2PROM from malfunction due to an undefined output (high impedance) from the tristate pin when the microprocessor is reset when the voltage drops.
2. I/O pin equivalent circuit
The I/O pins of this IC do not include pull-up and pull-down resistors. The SDA pin is an open-drain output.
The following shows the equivalent circuits.
SCL
Figure 21 SCL Pin
SDA
Figure 22 SDA Pin
Seiko Instruments Inc.
19
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
WP
Figure 23 WP Pin
A0, A1, A2
Figure 24 A0, A1, A2 Pin
20
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
3. Matching phases while E2PROM is accessed
The S-24CS64A does not have a pin for resetting (the internal circuit), therefore, the E2PROM cannot be
forcibly reset externally. If a communication interruption occurs in the E2PROM, it must be reset by
software.
For example, even if a reset signal is input to the microprocessor, the internal circuit of the E2PROM is not
reset as long as the stop condition is not input to the E2PROM. In other words, the E2PROM retains the
same status and cannot shift to the next operation. This symptom applies to the case when only the
microprocessor is reset when the power supply voltage drops. With this status, if the power supply voltage
is restored, reset the E2PROM (after matching the phase with the microprocessor) and input an instruction.
The following shows this reset method.
[How to reset E2PROM]
The E2PROM can be reset by the start and stop instructions. When the E2PROM is reading data “0” or
is outputting the acknowledge signal, 0 is output to the SDA line. In this status, the microprocessor
cannot output an instruction to the SDA line. In this case, terminate the acknowledge output operation
or read operation, and then input a start instruction. Figure 25 shows this procedure.
First, input the condition. Then transmit 9 clocks (dummy clocks) of SCL. During this time, the
microprocessor sets the SDA line to high level. By this operation, the E2PROM interrupts the
acknowledge output operation or data output, so input the start condition*1. When a start condition is
input, the E2PROM is reset. To make doubly sure, input the stop condition to the E2PROM. Normal
operation is then possible.
Start
condition
Start
condition
Dummy clock
1
2
8
Stop
condition
9
SCL
SDA
Figure 25 Resetting E2PROM
*1. After 9 clocks (dummy clocks), if the SCL clock continues to be output without a start condition
being input, a write operation may be started upon receipt of a stop condition. To prevent this, input
a start condition after 9 clocks (dummy clocks).
Remark It is recommended to perform the above reset using dummy clocks when the system is
initialized after the power supply voltage has been raised.
Seiko Instruments Inc.
21
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
4. Acknowledge check
The I2C-bus protocol includes an acknowledge check function as a handshake function to prevent a
communication error. This function allows detection of a communication failure during data communication
between the microprocessor and E2PROM. This function is effective to prevent malfunction, so it is
recommended to perform an acknowledge check on the microprocessor side.
5. Built-in power-on-clear circuit
E2PROMs have a built-in power-on-clear circuit that initializes the E2PROM. Unsuccessful initialization
may cause a malfunction. For the power-on-clear circuit to operate normally, the following conditions must
be satisfied for raising the power supply voltage.
5.1 Raising power supply voltage
Raise the power supply voltage, starting at 0.2 V maximum, so that the voltage reaches the power supply
voltage to be used within the time defined by tRISE as shown in Figure 26.
For example, when the power supply voltage to be used is 5.0 V, tRISE is 200 ms as shown in Figure 27.
The power supply voltage must be raised within 200 ms.
tRISE (Max.)
Power supply voltage (VCC)
VINIT (Max.)
0.2 V
0 V*1
tINIT*2 (Max.)
*1. 0 V means there is no difference in potential between the VCC pin and
the GND pin of the E2PROM.
*2. tINIT is the time required to initialize the E2PROM. No instructions are
accepted during this time.
Figure 26 Raising Power Supply Voltage
22
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
5.0
4.0
Power supply voltage
(VCC)
[V]
3.0
2.0
100 150 200
50
Rise time (tRISE) Max.
[ms]
For example:
If your E2PROM supply voltage = 5.0 V, raise the power supply
voltage to 5.0 V within 200 ms.
Figure 27 Raising Time of Power Supply Voltage
When initialization is successfully completed via the power-on-clear circuit, the E2PROM enters the
standby status.
If the power-on-clear circuit does not operate, the following are the possible causes.
(1) Because the E2PROM has not been initialized, an instruction formerly input is valid or an instruction
may be inappropriately recognized. In this case, writing may be performed.
(2) The voltage may have dropped due to power off while the E2PROM is being accessed. Even if the
microprocessor is reset due to the low power voltage, the E2PROM may malfunction unless the
power-on-clear operation conditions of E2PROM are satisfied. For the power-on-clear operation
conditions of E2PROM, refer to 5.1 Raising power supply voltage.
If the power-on-clear circuit does not operate, match the phase (reset) so that the internal E2PROM circuit
is normally reset. The statuses of the E2PROM immediately after the power-on-clear circuit operates and
when phase is matched (reset) are the same.
Seiko Instruments Inc.
23
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
5.2 Wait for the initialization sequence to end
The E2PROM executes initialization during the time that the supply voltage is increasing to its normal
value. All instructions must wait until after initialization. The relationship between the initialization time
(tINIT) and rise time (tRISE) is shown in Figure 28.
100 m
10 m
2
E PROM initialization
time (tINIT) Max.
[s]
1.0 m
100 µ
10 µ
1.0 µ
1.0 µ 10 µ
100 µ 1.0 m 10 m 100 m
Rise time (tRISE)
[s]
Figure 28 Initialization Time of E2PROM
24
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
6. Data hold time (tHD. DAT = 0 ns)
If SCL and SDA of the E2PROM are changed at the same time, it is necessary to prevent the start / stop
condition from being mistakenly recognized due to the effect of noise. If a start / stop condition is
mistakenly recognized during communication, the E2PROM enters the standby status.
It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µs minimum in the S-24CS64A.
This is to prevent time lag caused by the load of the bus line from generating the stop (or start) condition.
tHD. DAT = 0.3 µs Min.
SCL
SDA
Figure 29 E2PROM Data Hold Time
7. SDA pin and SCL pin noise suppression time
The S-24CS64A includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This means
that if the power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed.
The guaranteed for details, refer to noise suppression time (tI) in Table 11.
300
Noise suppression time (tI) Max.
[ns]
200
100
2
3
4
5
Power supply voltage (VCC)
[V]
Figure 30 Noise Suppression Time for SDA and SCL Pins
Seiko Instruments Inc.
25
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
8. Trap: E2PROM operation in case that the stop condition is received during write operation before
receiving the defined data value (less than 8-bit) to SCL pin
When the E2PROM receives the stop condition signal compulsorily, during receiving 1 byte of write data,
“write” operation is aborted.
When the E2PROM receives the stop condition signal after receiving 1 byte or more of data for “page
write”, 8-bit of data received normally before receiving the stop condition signal can be written.
9. Trap: E2PROM operation and write data in case that write data is input more than defined page size at
“page write”
When write data is input more than defined page size at page write operation, for example, S-24CS64A
(which can be executed 32-byte page write) is received data more than 33 byte, 8-bit data of the 33rd byte
is over written to the first byte in the same page. Data over the capacity of page address cannot be written.
10. Trap: Severe environments
Absolute maximum ratings: Do not operate these ICs in excess of the absolute max ratings, as listed on
the data sheet. Exceeding the supply voltage rating can cause latch-up.
Operations with moisture on the E2PROM pins may occur malfunction by short-circuit between pins.
Especially, in occasions like picking the E2PROM up from low temperature tank during the evaluation. Be
sure that not remain frost on E2PROM pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
26
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Precautions
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
● SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.
Precautions for WLP package
● The side of device silicon substrate is exposed to the marking side of device package. Since this portion
has lower strength against the mechanical stress than the standard plastic package, chip, crack, etc
should be careful of the handing of a package enough. Moreover, the exposed side of silicon has
electrical potential of device substrate, and needs to be kept out of contact with the external potential.
● In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it
mind that it may affect the characteristic of a device when exposed a device in the bottom of a high light
source.
Seiko Instruments Inc.
27
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Characteristics (Typical Data)
1. DC Characteristics
1.1 Current consumption (READ) ICC1
Ambient temperature Ta
1.2 Current consumption (READ) ICC1
Ambient temperature Ta
VCC=5.5 V
fSCL=100 kHz
DATA=0101
VCC=3.3 V
fSCL=100 kHz
DATA=0101
300
ICC1
(µA) 200
300
ICC1
(µA) 200
100
100
0
–40
0
Ta (°C)
0
85
–40
1.4 Current consumption (READ) ICC1
Power supply voltage VCC
Ta=25°C
fSCL=100 kHz
DATA=0101
VCC=1.8 V
fSCL=100 kHz
DATA=0101
300
ICC1
(µA) 200
300
ICC1
(µA) 200
100
100
0
2 3 4 5 6
VCC (V)
85
0
Ta (°C)
–40
1.5 Current consumption (READ) ICC1
Power supply voltage VCC
VCC=5.0 V
Ta=25°C
500
ICC1
400
(µA)
300
200
100
500
ICC1
(µA) 400
300
200
100
28
7
1.6 Current consumption (READ) ICC1
Clock frequency fSCL
Ta=25°C
fSCL=400 kHz
DATA=0101
0
85
Ta (°C)
1.3 Current consumption (READ) ICC1
Ambient temperature Ta
0
0
2
3
4
5 6
VCC (V)
7
100k
400k
fSCL (Hz)
Seiko Instruments Inc.
1M
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
1.7 Current consumption (PROGRAM) ICC2
Ambient temperature Ta
1.8 Current consumption (PROGRAM) ICC2
Ambient temperature Ta
VCC=5.5 V
VCC=3.3 V
1.5
1.5
ICC2
(mA) 1.0
ICC2
(mA) 1.0
0.5
0.5
0
–40
0
Ta (°C)
0
85
1.9 Current consumption (PROGRAM) ICC2
Ambient temperature Ta
–40
1.10 Current consumption (PROGRAM) ICC2
Power supply voltage VCC
VCC=2.7 V
Ta=25°C
1.5
1.5
ICC2
(mA) 1.0
ICC2
(mA) 1.0
0.5
0.5
0
–40
0
Ta (°C)
0
85
1.11 Standby current consumption ISB
Ambient temperature Ta
1
VCC=5.5 V
SDA, SCL, WP=0 V
2.0
ILI
(µA)
ISB
(µA)
2 3 4 5 6
VCC (V)
1.12 Input leakage current ILI
Ambient temperature Ta
VCC=5.5 V
1.0
0.5
1.0
0
85
0
Ta (°C)
–40
85
0
Ta (°C)
0
–40
Seiko Instruments Inc.
85
0
Ta (°C)
29
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
1.13 Input leakage current ILI
Ambient temperature Ta
Rev.4.2_00
1.14 Output leakage current ILO
Ambient temperature Ta
VCC=5.5 V
VCC=5.5 V
SDA=0 V
SDA, SCL, WP=5.5 V
1.0
1.0
ILI
(µA)
ILO
(µA)
0.5
0
0.5
–40
0
85
0
Ta (°C)
1.15 Output leakage current ILO
Ambient temperature Ta
–40
85
0
Ta (°C)
1.16 Low level output voltage VOL
Low level output current IOL
VCC=5.5 V
SDA=5.5 V
Ta=−40°C
0.3
VCC=1.8 V
1.0
ILO
(µA)
VOL
(V)
0.5
0.2
VCC=5.0 V
0.1
0
–40
0
85
0
Ta (°C)
VOL
(V)
VCC=5.0 V
1
2
3
4
5
0.2
VCC= 5.0 V
0.1
6
0
IOL (mA)
30
6
0.3 VCC=1.8 V
0.2
0
5
Ta=85°C
VCC=1.8 V
0.1
3 4
1.18 Low level output voltage VOL
Low level output current IOL
Ta=25°C
VOL
(V)
2
IOL (mA)
1.17 Low level output voltage VOL
Low level output current IOL
0.3
1
1
2
3
4 5 6
IOL (mA)
Seiko Instruments Inc.
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
1.19 High input inversion voltage VIH
Power supply voltage VCC
1.20 High input inversion voltage VIH
Ambient temperature Ta
Ta=25°C
SDA, SCL
VCC=5.0 V
SDA, SCL
3.0
3.0
VIH 2.0
(V)
VIH 2.0
(V)
1.0
1.0
0
0
1 2 3 4 5 6 7
–40
Ta (°C)
1.21 Low input inversion voltage VIL
Power supply voltage VCC
1.22 Low input inversion voltage VIL
Ambient temperature Ta
Ta=25°C
SDA, SCL
VIL
(V)
VCC=5.0 V
SDA, SCL
3.0
3.0
2.0
VIL 2.0
(V)
1.0
1.0
0
85
0
VCC (V)
0
1 2 3 4 5 6 7
–40
VCC (V)
85
0
Ta (°C)
1.23 Low power supply detection voltage −VDET
Ambient temperature Ta
1.24 Low power supply release voltage +VDET
Ambient temperature Ta
2.0
2.0
+VDET
(V)
−VDET
(V)
1.0
0
1.0
–40
0
85
0
–40
Ta (°C)
0
85
Ta (°C)
Seiko Instruments Inc.
31
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
2. AC Characteristics
2.2 Write time tWR Power supply voltage VCC
2.1 Maximum operating frequency fMAX.
Power supply voltage VCC
Ta=25°C
Ta=25°C
8
1M
fMAX.
(Hz) 100k
tWR
(ms)
6
4
10k
2
1
2
0
3
4 5
VCC (V)
2.3 Write time tWR Ambient temperature Ta
9
tWR
(ms)
1
9
tWR
(ms)
6
3
0
–40
0
Ta (°C)
0
85
2.5 SDA output delay time tAA
Ambient temperature Ta
–40
0
Ta (°C)
85
2.6 SDA output delay time tAA
Ambient temperature Ta
VCC=4.5 V
VCC=2.7 V
1.0
tAA
(µs)
1.0
0.5
0.5
32
6
VCC=2.7 V
VCC=4.5 V
6
0
3 4 5
VCC (V)
2.4 Write time tWR Ambient temperature Ta
3
tAA
(µs)
2
–40
0
Ta (°C)
85
0
–40
Seiko Instruments Inc.
0
Ta (°C)
85
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
2.7 SDA output delay time tAA
Ambient temperature Ta
VCC=1.8 V
tAA
(µs)
1.0
0.5
0
–40
0
Ta(°C)
85
Seiko Instruments Inc.
33
2-WIRE CMOS SERIAL E2PROM
S-24CS64A
Rev.4.2_00
Product Name Structure
1. 8-Pin SOP(JEDEC), 8-Pin TSSOP Packages
S-24CS64A
0I
- xxxx G
Package name (abbreviation) and IC packing specifications
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
Fixed
Product name
S-24CS64A: 64 Kbit
2. WLP Package
S-24CS64A
0I
- H8Tx
Package name (abbreviation) and IC packing specifications
H8Tx: WLP, Tape
Fixed
Product name
S-24CS64A: 64 Kbit
Remark Please contact our sales office regarding the product with WLP package.
34
Seiko Instruments Inc.
5.02±0.2
8
5
1
4
1.27
0.20±0.05
0.4±0.05
No. FJ008-A-P-SD-2.1
TITLE
No.
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.1
SCALE
UNIT
mm
Seiko Instruments Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
ø2.0±0.05
8.0±0.1
2.1±0.1
5°max.
6.7±0.1
1
8
4
5
Feed direction
No. FJ008-D-C-SD-1.1
TITLE
SOP8J-D-Carrier Tape
No.
FJ008-D-C-SD-1.1
SCALE
UNIT
mm
Seiko Instruments Inc.
60°
2±0.5
13.5±0.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-D-R-SD-1.1
TITLE
SOP8J-D-Reel
No.
FJ008-D-R-SD-1.1
SCALE
UNIT
QTY.
mm
Seiko Instruments Inc.
2,000
+0.3
3.00 -0.2
8
5
1
4
0.17±0.05
0.2±0.1
0.65
No. FT008-A-P-SD-1.1
TITLE
TSSOP8-E-PKG Dimensions
FT008-A-P-SD-1.1
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
4.0±0.1
2.0±0.05
ø1.55±0.05
0.3±0.05
+0.1
8.0±0.1
ø1.55 -0.05
(4.4)
+0.4
6.6 -0.2
1
8
4
5
Feed direction
No. FT008-E-C-SD-1.0
TITLE
TSSOP8-E-Carrier Tape
FT008-E-C-SD-1.0
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
13.4±1.0
17.5±1.0
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.5
No. FT008-E-R-SD-1.0
TSSOP8-E-Reel
TITLE
No.
FT008-E-R-SD-1.0
SCALE
QTY.
UNIT
mm
Seiko Instruments Inc.
3,000
•
•
•
•
•
•
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
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