XM25QH128A
XM25QH128A
preliminary
128 Megabit 3V Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
-
-
-
Single power supply operation
Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
SPI Compatible: Mode 0 and Mode 3
128 M-bit Serial Flash
128 M-bit / 16,384 KByte /65,535 pages
256 bytes per programmable page
Standard, Dual or Quad SPI
Standard SPI: CLK, CS#, DI, DO, WP#,
HOLD#/RESET#
Dual SPI: CLK, CS#, DQ0, DQ1, WP#,
HOLD#/RESET#
Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
Configurable dummy cycle number
High performance
Normal read
- 50MHz
Fast read (Single Data Rate Mode)
- Standard SPI: 104MHz with 1 dummy bytes
- Dual SPI: 104MHz with 1 dummy bytes
- Quad SPI: 104MHz with 3 dummy bytes
Write Suspend and Write Resume
Support Serial Flash Discoverable
Parameters (SFDP) signature
Low power consumption
5 mA typical active current
1A typical power down current
Uniform Sector Architecture:
4096 sectors of 4-Kbyte
512 blocks of 32-Kbyte
256 blocks of 64-Kbyte
Any sector or block can be erased individually
Software and Hardware Write Protection:
Write Protect all or portion of memory via
software
Enable/Disable protection with WP# pin
Software and Hardware Reset
High performance program/erase speed
Page program time: 0.5ms typical
Sector erase time: 40ms typical
Half Block erase time 200ms typical
Block erase time 300ms typical
Chip erase time: 60 Seconds typical
Volatile Status Register Bits.
Lockable 512 byte OTP security sector
Read Unique ID Number
Typical 100K endurance cycle
Data retention time 20years
Package Options
SOP 208mil 8L
WSON 5x6 8L
TFBGA 6x8 24ball
All Pb-free packages are compliant RoHS,
Halogen-Free and REACH.
Industrial temperature Range
GENERAL DESCRIPTION
The XM25QH128A is a 128 Megabit (16,384K-byte) Serial Flash memory, with advanced write
protection mechanisms. The XM25QH128A supports the single bit and four bits serial input and output
commands via standard Serial Peripheral Interface (SPI) pins: Serial Clock, Chip Select, Serial DQ 0 (DI)
and DQ1(DO), DQ2(WP#) and DQ3(HOLD#/RESET#). SPI clock frequencies of up to 104Mhz are
supported allowing equivalent clock rates of 416Mhz(104Mhz x 4) for Quad Output while using the Quad
Output read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page
Program instruction.
The XM25QH128A also offers a sophisticated method for protecting individual blocks against erroneous
or malicious program and erase operations. By providing the ability to individually protect and unprotect
blocks, a system can unprotect a specific block to modify its contents while keeping the remaining
blocks of the memory array securely protected. This is useful in applications where program code is
patched or updated on a subroutine or module basis or in applications where data storage segments
need to be modified without running the risk of errant modifications to the program code segments.
The XM25QH128A is designed to allow either single Sector/Block at a time or full chip erase operation.
The XM25QH128A can be configured to protect part of the memory as the software protected mode.
The device can sustain a typical of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Figure.1 CONNECTION DIAGRAMS
preliminary
CS#
1
8
VCC
DO (DQ1)
2
7
HOLD#/RESET# (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 - LEAD SOP
CS#
1
8
VCC
DO (DQ1)
2
7
HOLD#/RESET# (DQ3)
WP# (DQ2)
3
6
CLK
4
5
DI (DQ0)
VSS
8 – LEAD WSON
Top View, Balls Facing Down
24 - Ball TFBGA
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Table 1. Pin Names
Symbol
Pin Name
CLK
Serial Clock Input
DI (DQ0)
Serial Data Input (Data Input Output 0)
DO (DQ1)
Serial Data Output (Data Input Output 1)
CS#
Chip Enable
WP# (DQ2)
Write Protect (Data Input Output 2)
HOLD#/RESET# (DQ3)
*1
*1
*2
HOLD# or RESET# pin
(Data Input Output 3)
*2
Vcc
Supply Voltage (2.7-3.6V)
Vss
Ground
NC
No Connect
Note:
1. DQ0 and DQ1 are used for Dual and Quad instructions.
2. DQ0 ~ DQ3 are used for Quad instructions,
WP# & HOLD# (or RESET#) functions are only available for Standard/Dual SPI.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 2. BLOCK DIAGRAM
Flash
Memory
X-Decoder
Address
Buffer
And
Latches
Y-Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CS#
CLK
DI (DQ0)
DO (DQ1)
WP# (DQ2)
HOLD# / RESET#
(DQ3)
Note:
1. DQ0 and DQ1 are used for Dual instructions.
2. DQ0 ~ DQ3 are used for Quad instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
SIGNAL DESCRIPTION
preliminary
Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3)
The XM25QH128A support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from
the device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (SR.5, SR.4, SR.3, SR.2) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function
is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ2) for Quad I/O operation.
HOLD (HOLD#)
The HOLD# pin allows the device to be paused while it is actively selected. When WXDIS bit is “0”
(factory default) and HRSW bit is ‘0’ (factory default is ‘0’), the HOLD# pin is enabled. When HOLD# is
brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins
will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same
SPI signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during
Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation.
RESET (RESET#)
The RESET# pin allows the device to be reset by the controller. When WXDIS bit is “0” (factory default)
and HRSW bit is ‘1’ (factory default is ‘0’), the RESET# pin is enabled. The Hardware Reset function is
only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial
Data IO (DQ3) for Quad I/O operation. Set RESET# to low for a minimum period 1us (tHRST) will
interrupt any on-going instructions to have the device to initial state. The device can accept new
instructions again in 28us (tHRSL) after RESET# back to high.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
MEMORY ORGANIZATION
preliminary
The memory is organized as:
16,777,216 bytes
Uniform Sector Architecture
256 blocks of 64-Kbyte
512 blocks of 32-Kbyte
4,096 sectors of 4-Kbyte
65,536 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 2. Uniform Block Sector Architecture ( 1/4 )
418
417
208
416
3344
3343
D10000h
D0F000h
D10FFFh
D0FFFFh
3328
D00000h
D00FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
….
….
….
….
….
….
….
….
….
….
….
….
….
….
….
E20FFFh
E1FFFFh
….
449
3600
3599
E10000h
E0F000h
E10FFFh
E0FFFFh
….
448
3584
E00000h
E00FFFh
32K
Block
Sector
415
3327
….
414
3312
3311
CF0000h
CEF000h
CF0FFFh
CEFFFFh
450
224
64K
Block
207
….
CFFFFFh
411
3296
3295
CE0000h
CDF000h
CE0FFFh
CDFFFFh
410
3280
CD0000h
CD0FFFh
206
412
….
205
389
3119
C2F000h
C2FFFFh
388
3014
3103
C20000h
C1F000h
C20FFFh
C1FFFFh
194
387
385
3088
3087
C10000h
C0F000h
C10FFFh
C0FFFFh
384
3072
C00000h
C00FFFh
193
386
192
7
CFF000h
….
413
Address range
….
419
209
E20000h
E1F000h
….
D20FFFh
D1FFFFh
3616
3615
….
D20000h
D1F000h
452
451
….
….
….
3360
3359
….
420
210
….
D2FFFFh
….
D2F000h
….
3375
….
421
E2FFFFh
….
….
….
DD0FFFh
….
….
DD0000h
….
3536
….
DE0FFFh
DDFFFFh
….
DE0000h
DDF000h
….
442
3552
3551
….
443
221
….
444
E2F000h
225
DFFFFFh
….
445
222
3631
….
DF0FFFh
DEFFFFh
453
….
DF0000h
DEF000h
ED0FFFh
….
3568
3567
ED0000h
….
446
223
3792
226
Address range
DFF000h
474
237
….
3583
EE0FFFh
EDFFFFh
….
447
EE0000h
EDF000h
….
Sector
475
3808
3807
476
….
32K
Block
477
238
….
F00FFFh
EF0FFFh
EEFFFFh
….
F00000h
EF0000h
EEF000h
EFFFFFh
….
3840
240
3824
3823
EFF000h
….
….
….
480
….
F10FFFh
F0FFFFh
….
F10000h
F0F000h
….
3856
3855
….
….
….
F20FFFh
F1FFFFh
….
481
F20000h
F1F000h
….
482
3872
3871
….
483
241
….
F2FFFFh
478
239
….
F2F000h
3839
….
….
….
FD0FFFh
….
….
….
FD0000h
….
4048
….
FE0FFFh
FDFFFFh
3887
484
….
FE0000h
FDF000h
485
242
64K
Block
4064
4063
….
….
506
FF0FFFh
FEFFFFh
….
507
253
FF0000h
FEF000h
….
508
….
509
254
4080
4079
….
510
….
255
479
….
FFFFFFh
Address range
….
FFF000h
Sector
….
4095
32K
Block
….
511
64K
Block
Address range
….
Sector
….
32K
Block
….
64K
Block
preliminary
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 2. Uniform Block Sector Architecture ( 2/4 )
910FFFh
90FFFFh
2304
900000h
900FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
….
….
….
….
….
….
….
….
….
….
….
….
A2FFFFh
….
….
….
324
2592
2591
A20000h
A1F000h
A20FFFh
A1FFFFh
….
….
321
2576
2575
A10000h
A0F000h
A10FFFh
A0FFFFh
….
….
320
2560
A00000h
A00FFFh
32K
Block
Sector
287
2303
….
….
323
286
2288
2287
8F0000h
8EF000h
8F0FFFh
8EFFFFh
322
160
64K
Block
143
….
….
283
8E0000h
8DF000h
8E0FFFh
8DFFFFh
….
8FFFFFh
2272
2271
282
2256
8D0000h
8D0FFFh
142
284
….
261
2095
82F000h
82FFFFh
….
141
260
2080
2079
820000h
81F000h
820FFFh
81FFFFh
130
259
257
2064
2063
810000h
80F000h
810FFFh
80FFFFh
256
2048
800000h
800FFFh
129
258
128
8
8FF000h
….
285
Address range
….
910000h
90F000h
A2F000h
….
….
288
2320
2319
….
289
144
920FFFh
91FFFFh
….
290
920000h
91F000h
….
291
145
2336
2335
….
292
….
92FFFFh
….
92F000h
….
2351
2607
….
….
293
146
325
….
9D0FFFh
AD0FFFh
….
9D0000h
AD0000h
161
….
….
2512
….
….
….
9E0FFFh
9DFFFFh
….
9E0000h
9DF000h
….
….
2528
2527
….
314
….
315
157
9F0FFFh
9EFFFFh
….
316
9F0000h
9EF000h
….
317
158
2544
2543
2768
162
Address range
….
318
346
173
….
9FFFFFh
AE0FFFh
ADFFFFh
….
9FF000h
AE0000h
ADF000h
….
2559
347
2784
2783
348
….
319
159
349
174
….
Sector
AF0FFFh
AEFFFFh
….
32K
Block
AF0000h
AEF000h
….
B00FFFh
2800
2799
AFFFFFh
….
B00000h
350
AFF000h
….
2816
2815
….
352
176
351
Address range
….
….
B10FFFh
B0FFFFh
….
B10000h
B0F000h
….
2832
2831
….
353
B20FFFh
B1FFFFh
….
354
B20000h
B1F000h
….
355
177
2848
2847
….
356
….
B2FFFFh
….
B2F000h
Sector
….
2863
32K
Block
175
….
….
BD0FFFh
….
BD0000h
….
3024
….
BE0FFFh
BDFFFFh
357
178
….
BE0000h
BDF000h
….
….
378
….
379
189
3040
3039
….
….
BF0FFFh
BEFFFFh
….
BF0000h
BEF000h
….
3056
3055
380
BFFFFFh
….
382
382
BFF000h
….
3071
190
64K
Block
Address range
383
191
64K
Block
Sector
….
32K
Block
….
64K
Block
preliminary
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
….
160
1296
1295
510000h
50F000h
510FFFh
50FFFFh
….
161
80
1280
500000h
500FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
….
….
….
….
….
….
….
….
….
….
….
….
….
….
….
620FFFh
61FFFFh
….
193
1552
1551
610000h
60F000h
610FFFh
60FFFFh
….
192
1536
600000h
600FFFh
32K
Block
Sector
159
1279
….
195
158
1264
1263
4F0000h
4EF000h
4F0FFFh
4EFFFFh
194
96
64K
Block
79
….
4FFFFFh
155
1248
1247
4E0000h
4DF000h
4E0FFFh
4DFFFFh
154
1232
4D0000h
4D0FFFh
78
156
77
133
1071
42F000h
42FFFFh
132
1056
1055
420000h
41F000h
420FFFh
41FFFFh
66
131
129
1040
1039
410000h
40F000h
410FFFh
40FFFFh
128
1024
400000h
400FFFh
65
130
64
9
4FF000h
….
157
Address range
….
520FFFh
51FFFFh
….
162
520000h
51F000h
….
163
81
1312
1311
….
164
….
52FFFFh
….
52F000h
….
1327
620000h
61F000h
….
….
165
82
1568
1567
….
5D0FFFh
196
….
5D0000h
62FFFFh
97
….
….
1488
….
….
….
5E0FFFh
5DFFFFh
….
5E0000h
5DF000h
….
….
1504
1503
….
186
….
187
93
5F0FFFh
5EFFFFh
….
188
5F0000h
5EF000h
….
189
94
1520
1519
62F000h
98
Address range
….
190
1583
….
5FFFFFh
197
….
5FF000h
6D0FFFh
….
1535
6D0000h
….
191
95
1744
….
Sector
218
109
….
32K
Block
6E0FFFh
6DFFFFh
….
700FFFh
6E0000h
6DF000h
….
700000h
219
1760
1759
220
….
1792
221
….
224
112
6F0FFFh
6EFFFFh
….
710FFFh
70FFFFh
6F0000h
6EF000h
110
….
….
….
….
710000h
70F000h
….
1808
1807
….
….
720FFFh
71FFFFh
….
225
720000h
71F000h
….
226
1824
1823
….
227
113
….
72FFFFh
….
72F000h
1776
1775
6FFFFFh
….
….
….
7D0FFFh
….
7D0000h
….
2000
1839
228
….
7E0FFFh
7DFFFFh
229
114
64K
Block
7E0000h
7DF000h
….
….
250
2016
2015
….
251
125
….
252
….
253
126
222
111
6FF000h
….
7F0FFFh
7EFFFFh
1791
….
7F0000h
7EF000h
223
….
….
2032
2031
7FFFFFh
Address range
….
….
254
127
7FF000h
Sector
….
2047
32K
Block
….
255
64K
Block
Address range
….
Sector
preliminary
….
32K
Block
….
64K
Block
….
Table 2. Uniform Block Sector Architecture ( 3/4 )
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 2. Uniform Block Sector Architecture ( 4/4 )
4095
3FF000h
3FFFFFh
….
….
….
….
….
….
….
2D0000h
2D0FFFh
1F0FFFh
1EFFFFh
….
….
….
….
….
….
255
30
240
239
0F0000h
0EF000h
0F0FFFh
0EFFFFh
15
….
….
….
….
….
….
0FFFFFh
….
29
0FF000h
100FFFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
….
….
….
….
….
….
….
02FFFFh
4
32
31
020000h
01F000h
020FFFh
01FFFFh
2
3
1
2
1
0
0
10
….
….
100000h
02F000h
16
15
010000h
00F000h
010FFFh
00FFFFh
….
….
256
47
….
110FFFh
10FFFFh
5
….
….
110000h
10F000h
13
….
….
272
271
28
….
….
120FFFh
11FFFFh
14
….
….
….
….
31
Address range
0D0FFFh
….
….
Sector
0D0000h
120000h
11F000h
32
32K
Block
208
288
287
33
64K
Block
26
36
16
200FFFh
1D0FFFh
12FFFFh
34
200000h
1D0000h
12F000h
35
512
27
303
17
64
32
0E0FFFh
0DFFFFh
37
18
210FFFh
20FFFFh
0E0000h
0DF000h
….
464
210000h
20F000h
224
223
….
1E0FFFh
1DFFFFh
….
1E0000h
1DF000h
….
58
480
479
65
528
527
66
….
59
29
….
60
67
33
1FFFFFh
….
61
220FFFh
21FFFFh
….
1F0000h
1EF000h
220000h
21F000h
….
496
495
544
543
….
62
68
34
Address range
1FF000h
22FFFFh
….
511
22F000h
….
63
559
….
Sector
69
….
32K
Block
45
….
300FFFh
92
….
….
….
300000h
….
310FFFh
30FFFFh
….
310000h
30F000h
….
784
783
….
….
….
320FFFh
31FFFFh
….
….
320000h
31F000h
….
800
799
46
….
….
720
….
….
….
90
768
30
93
3D0FFFh
96
31
2F0FFFh
2EFFFFh
3D0000h
….
97
48
2F0000h
2EF000h
….
98
752
751
2FFFFFh
91
32FFFFh
99
94
47
2FF000h
2E0FFFh
2DFFFFh
32F000h
49
767
2E0000h
2DF000h
….
4048
95
Address range
736
735
….
3E0FFFh
3DFFFFh
815
100
….
3E0000h
3DF000h
101
50
64K
Block
4064
4063
….
….
122
3F0FFFh
3EFFFFh
….
123
61
3F0000h
3EF000h
Sector
….
124
….
125
62
4080
4079
….
126
….
63
32K
Block
….
127
64K
Block
Address range
….
Sector
….
32K
Block
….
64K
Block
preliminary
0
000000h
000FFFh
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
OPERATING FEATURES
preliminary
Standard SPI Modes
The XM25QH128A is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as
shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby
and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For
Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising
edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
Figure 3. SPI Modes
Dual SPI Instruction
The XM25QH128A supports Dual SPI operation when using the “Dual Output Fast Read and Dual I/ O
FAST_READ “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the
Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read
instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing)
or for application that cache code-segments to RAM for execution. The Dual output feature simply
allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI
instructions the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use
the standard SPI interface with single output signal.
Quad I/O SPI Modes
The XM25QH128A supports Quad input/output operation when using the Quad I/O Fast Read
(EBh).This instruction allows data to be transferred to or from the Serial Flash memory at four to six
times the rate possible with the standard SPI. The Quad Read instruction offer a significant
improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or
for application that cache code-segments to RAM for execution. When using Quad SPI instruction the
DI and DO pins become bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD#/RESET# pins
become DQ2 and DQ3 respectively.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Figure 4. Quad SPI Modes
preliminary
Full Quad SPI Modes (QPI)
The XM25QH128A also supports Full Quad SPI Mode (QPI) function while using the Enable Quad
Peripheral Interface mode (EQPI) (38h). When using Quad SPI instruction the DI and DO pins become
bidirectional I/O pins; DQ0 and DQ1, and the WP# and HOLD#/RESET# pins become DQ2 and DQ3
respectively.
Figure 5. Full Quad SPI Modes
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
12
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Page Programming
preliminary
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) or Quad Input Page Program (QPP) sequence, which consists of four bytes plus
data. This is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) or Quad Input Page Program (QPP) instruction allows
up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in
consecutive addresses on the same page of memory.
Sector Erase, Half Block Erase, Block Erase and Chip Erase
The Page Program (PP) or Quad Input Page Program (QPP) instruction allows bits to be reset from 1 to
0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can
be achieved a sector at a time, using the Sector Erase (SE) instruction, half a block at a time using the
Half Block Erase (HBE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration tSE, tHBE,, tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP, QPP) or Erase (SE,
HBE, BE or CE) can be achieved by not waiting for the worst case delay (tW , tPP, tSE, tHBE, tBE or tCE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program can
monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is
complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, Write Status Register). The device then goes into the Stand-by
Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in
this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device
ID (RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
XM25QH128A provides the following data protection mechanisms:
Power-On Reset and an internal timer (tPUW ) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the
Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP), Quad Input Page Program (QPP) instruction completion
or Sector Erase (SE) instruction completion or Half Block Erase (HBE) / Block Erase (BE)
instruction completion or Chip Erase (CE) instruction completion
– Software/Hardware Reset completion
The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode (SPM).
The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
13
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 3. Protected Area Sizes Sector Organization
Status Register Content
preliminary
Memory Content
T/B SR.5 SR.4 SR.3 SR.2
Protect Areas
Addresses
Density(KB)
Portion
Bit
Bit
Bit
Bit
Bit
0
0
0
0
0
None
None
None
None
0
0
0
0
1
Block 252 to 255
FC0000h-FFFFFFh
256KB
Upper 4/256
0
0
0
1
0
Block 248 to 255
F80000h-FFFFFFh
512KB
Upper 8/256
0
0
0
1
1
Block 240 to 255
F00000h-FFFFFFh
1024KB
Upper 16/256
0
0
1
0
0
Block 224 to 255
E00000h-FFFFFFh
2048KB
Upper 32/256
0
0
1
0
1
Block 192 to 255
C00000h-FFFFFFh
4096KB
Upper 64/256
0
0
1
1
0
Block 128 to 255
800000h-FFFFFFh
8192KB
Upper 128/256
0
0
1
1
1
Block 0 to 255
000000h-FFFFFFh
16384KB
All
0
1
0
0
0
None
None
None
None
0
1
0
0
1
Block 0 to 3
000000h-03FFFFh
256KB
Lower 4/256
0
1
0
1
0
Block 0 to 7
000000h-07FFFFh
512KB
Lower 8/256
0
1
0
1
1
Block 0 to 15
000000h-0FFFFFh
1024KB
Lower 16/256
0
1
1
0
0
Block 0 to 31
000000h-1FFFFFh
2048KB
Lower 32/256
0
1
1
0
1
Block 0 to 63
000000h-3FFFFFh
4096KB
Lower 64/256
0
1
1
1
0
Block 0 to 127
000000h-7FFFFFh
8192KB
Lower 128/256
0
1
1
1
1
Block 0 to 255
000000h-FFFFFFh
16384KB
All
1
0
0
0
0
None
None
None
None
1
0
0
0
1
Block 0 to 251
000000h-FBFFFFh
16128KB
Lower 252/256
1
0
0
1
0
Block 0 to 247
000000h-F7FFFFh
15872KB
Lower 248/256
1
0
0
1
1
Block 0 to 239
000000h-EFFFFFh
15360KB
Lower 240/256
1
0
1
0
0
Block 0 to 223
000000h-DFFFFFh
14336KB
Lower 224/256
1
0
1
0
1
Block 0 to 191
000000h-BFFFFFh
12288KB
Lower 192/256
1
0
1
1
0
Block 0 to 127
000000h-7FFFFFh
8192KB
Lower 128/256
1
0
1
1
1
Block 0 to 255
000000h-FFFFFFh
16384KB
All
1
1
0
0
0
None
None
None
None
1
1
0
0
1
Block 4 to 255
040000h-FFFFFFh
16128KB
Upper 252/256
1
1
0
1
0
Block 8 to 255
080000h-FFFFFFh
15872KB
Upper 248/256
1
1
0
1
1
Block 16 to 255
100000h-FFFFFFh
15360KB
Upper 240/256
1
1
1
0
0
Block 32 to 255
200000h-FFFFFFh
14336KB
Upper 224/256
1
1
1
0
1
Block 64 to 255
400000h-FFFFFFh
12288KB
Upper 192/256
1
1
1
1
0
Block 128 to 255
800000h-FFFFFFh
8192KB
Upper 128/256
1
1
1
1
1
Block 0 to 255
000000h-FFFFFFh
16384KB
All
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
14
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Enable Boot Lock
preliminary
The Enable Boot Lock feature enables user to lock the 64KB-block/sector on the top/bottom of the
device for protection. This feature is activated by configuring 4KBL/TB bits and programming EBL bit to
‘1’. The TB bit and 4KBL bits can only be programmed once.
The bits’ definitions are described in the following table.
Table 4. The Enable Boot Lock feature
Type
Non-volatile/
Volatile bit
Register
Description
Function
0 (default)
SR.6
Enable Boot lock
SR.3
Top/Bottom Protect
SR.4
4KB Boot Lock
1 : Lock selected
64KB-Block/Sector
0 : Top (default)
1 : Bottom
OTP/Volatile
bit
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
0 : 64KB-Block (default)
1 : Sector
15
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
INSTRUCTIONS
preliminary
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven
Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on
Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code.
Depending on the instruction, it might be followed by address bytes, or data bytes, or both or none. Chip
Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the
case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Dual Output Fast
Read (3Bh), Dual I/O Fast Read (BBh), Quad Output Fast Read (6Bh), Quad Input/Output FAST_READ
(EBh), Read Status Register (RDSR), Read Suspend Status Register (RDSSR) or Release from Deep
Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being
shifted out.
In the case of a write instruction, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High
when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight.
For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be
reset.
In the case of multi-byte commands of Page Program (PP), Quad Input Page Program (QPP), and
Release from Deep Power Down (RES ) minimum number of bytes specified has to be given,
without which, the command will be ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and HBE / BE, exact 24-bit address is a must,
any less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
16
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 5A. Instruction Set
Instruction Name
Byte 1
Code
RSTEN
RST(1)
66h
EQPI
38h
RSTQPI(2)
Write Enable (WERN)
Volatile Status Register
Write Enable (3)
FFh
Write Disable (WRDI)/
Exit OTP mode
Read Status Register
(RDSR)
Write Status Register
(WRSR)
Read Status Register 2
(RDSR2)
Read Status Register 3
(RDSR3)
Write Status Register 3
(WRSR3)
Write Suspend
preliminary
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
99h
06h
50h
04h
05h
(S7-S0)(4)
01h
S7-S0
09h
(S7-S0)(4)
95h
(S7-S0)(4)
C0h
S7-S0
continuous(5)
continuous(5)
B0h
Write Resume
30h
Deep Power-down
Release from Deep
Power-down, and read
Device ID (RES)
Release from Deep
Power-down (RDP)
Manufacturer/
Device ID
Read Identification
(RDID)
Enter OTP mode
Read SFDP mode and
Unique ID Number
B9h
(6)
dummy
dummy
90h
dummy
dummy
9Fh
(M7-M0)
(ID15ID8)
A23-A16
A15-A8
dummy
(ID7-ID0)
00h
01h
(ID7-ID0)
(M7-M0)
(ID7-ID0)
(8)
(ID7-ID0)
(M7-M0)
A7-A0
dummy
(D7-D0)
ABh
(7)
3Ah
5Ah
(Next Byte)
continuous
Notes:
1. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
2. Release Full Quad SPI or Fast Read Enhanced mode. Device accepts eight-clocks command in Standard SPI mode, or twoclocks command in Full Quad SPI mode.
3. Volatile Status Register Write Enable command must precede WRSR command without any intervening commands to write
data to Volatile Status Register.
4. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the
device on the DO pin.
5. The Status Register contents will repeat continuously until CS# terminate the instruction.
6. The Device ID will repeat continuously until CS# terminates the instruction.
7. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction.
00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.
8. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
17
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 5B. Instruction Set (Read Instruction)
Instruction Name
preliminary
Address
bits
OP Code
Dummy bits / Clocks
(Default)
Data Out
Read Data
03h
24 bits
0
(D7-D0, …)
Fast Read
0Bh
24 bits
8 bits / 8 clocks
(D7-D0, …)
Dual Output Fast Read
3Bh
24 bits
8 bits / 8 clocks
(D7-D0, …)
Dual I/O Fast Read
BBh
24 bits
8 bits / 4 clocks
(D7-D0, …)
Quad I/O Fast Read
EBh
24 bits
24 bits / 6 clocks
(D7-D0, …)
Quad Output Fast Read
6Bh
24 bits
8 bits / 8 clocks
(D7-D0, …)
Remark
(Next Byte)
continuous
(Next Byte)
continuous
(one byte
Per 4 clocks,
continuous)
(one byte
Per 4 clocks,
continuous)
(one byte
per 2 clocks,
continuous)
(one byte
per 2 clocks,
continuous)
Table 5C. Instruction Set (Program Instruction)
Instruction Name
Address
bits
OP Code
Dummy bits Clocks
(Default)
Data In
Page Program (PP)
02h
24 bits
0
(D7-D0, …)
Quad Input Page Program
(QPP)
32h
24 bits
0
(D7-D0, …)
Remark
(Next Byte)
continuous
(one byte
per 2 clocks,
continuous)
Table 5D. Instruction Set (Erase Instruction)
Instruction Name
Address
bits
OP Code
Dummy bits Clocks
(Default)
Data In
Sector Erase (SE)
20h
24 bits
0
(D7-D0, …)
32K Half Block
Erase (HBE)
52h
24 bits
0
(D7-D0, …)
64K Block Erase (BE)
D8h
24 bits
0
(D7-D0, …)
Chip Erase (CE)
C7h/ 60h
24 bits
0
(D7-D0, …)
Remark
Table 5E. Instruction Set (Read Instruction support mode and apply dummy cycle setting)
Instruction Name
OP Code
Start From SPI/QPI
(1)
Dummy Byte
(2)
SPI
QPI
Start From SPI
Start From QPI
Read Data
03h
Yes
No
N/A
N/A
Fast Read
0Bh
Yes
Yes
8 clocks
By SR3.4~5
Dual Output Fast Read
3Bh
Yes
No
8 clocks
N/A
Dual I/O Fast Read
BBh
Yes
No
4 clocks
N/A
Quad Output Fast Read
6Bh
Yes
No
8 clocks
N/A
Quad I/O Fast Read
EBh
Yes
Yes
By SR3.4~5
Note:
1. ‘Start From SPI/QPI' means if this command is initiated from SPI or QPI mode.
2. The dummy byte settings please refer to table 9
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
18
By SR3.4~5
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 6. Manufacturer and Device Identification
OP Code
(M7-M0)
(ID15-ID0)
ABh
preliminary
(ID7-ID0)
17h
90h
20h
9Fh
20h
17h
7018h
Reset-Enable (RSTEN) (66h) and Reset (RST) (99h)
The Reset operation is used as a system (software) reset that puts the device in normal operating
Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the XM25QH128A the host drives CS# low, sends the Reset-Enable command (66h), and
drives CS# high. Next, the host drives CS# low again, sends the Reset command (99h), and drives CS#
high.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any
command other than the Reset command after the Reset-Enable command will disable the ResetEnable.
A successful command execution will reset the status registers, see Figure 6 for SPI Mode and Figure
6.1 for Quad Mode. A device reset during an active Program or Erase operation aborts the operation,
which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior
operation, the reset timing may vary. Recovery from a Write operation requires more software latency
time ( tSR) than recovery from other operations.
Figure 6. Reset-Enable and Reset Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
19
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 6.1 . Reset-Enable and Reset Sequence Diagram in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
20
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Software Reset Flow
preliminary
Initial
No
Command
= 66h ?
Yes
Reset enable
No
Command
= 99h ?
Yes
Reset start
No
WIP = 0 ?
Embedded
Reset Cycle
Yes
Reset done
Note:
1. Reset-Enable (RSTEN) (66h) and Reset (RST) (99h) commands need to match standard SPI or
EQPI (quad) mode.
2. Continue (Enhance) EB mode need to use quad Reset-Enable (RSTEN) (66h) and quad Reset (RST)
(99h) commands.
3. If user is not sure it is in SPI or Quad mode, we suggest to execute sequence as follows:
Quad Reset-Enable (RSTEN) (66h) -> Quad Reset (RST) (99h) -> SPI Reset-Enable (RSTEN) (66h)
-> SPI Reset (RST) (99h) to reset.
4. The reset command could be executed during embedded program and erase process, QPI mode,
Continue EB mode and suspend mode to back to SPI mode.
5. This flow can release the device from Deep power down mode.
6. The Status Register Bit and Suspend Status Register Bit will reset to default value after reset done.
7. If user reset device during erase, the embedded reset cycle software reset latency will take about
28us in worst case.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
21
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Enable Quad Peripheral Interface mode (EQPI) (38h)
preliminary
The Enable Quad Peripheral Interface mode (EQPI) instruction will enable the flash device for Quad SPI
bus operation. Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed
input/output until a power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 7. The
device did not support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) ,Dual
Input/Output FAST_READ (BBh) and Quad output fast read (6Bh) modes while the Enable Quad
Peripheral Interface mode (EQPI) (38h) turns on.
Figure 7. Enable Quad Peripheral Interface mode Sequence Diagram
Reset Quad I/O (RSTQIO) (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. This command can’t be used in Standard SPI mode.
User also can use the FFh command to release the Quad I/O Fast Read Enhancement Mode. The
detail description, please see the Quad I/O Fast Read Enhancement Mode section.
Note:
If the system is in the Quad I/O Fast Read Enhance Mode in QPI Mode, it is necessary to execute FFh
command by two times. The first FFh command is to release Quad I/O Fast Read Enhance Mode, and
the second FFh command is to release EQPI Mode.
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Quad Input Page Program (QPP),
Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
22
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 8. Write Enable Instruction Sequence Diagram
Volatile Status Register Write Enable (50h)
This feature enable user to change memory protection schemes quickly without waiting for the typical
non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The
Volatile Status Register Write Enable (50h) command won’t set the Write Enable Latch (WEL) bit, it is
only valid for ‘Write Status Register’ (01h) command to change the Volatile Status Register bit values.
To write to Volatile Status Register, issue the Volatile Status Register Write Enable (50h) command
prior issuing WRSR (01h). The Status Register bits will be refresh to Volatile Status Register (SR[7:2])
within tSHSL2 (50ns). Upon power off or the execution of a Software/Hardware Reset, the volatile
Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored.
The instruction sequence is shown in Figure 9.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 9. Volatile Status Register Write Enable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
Write Disable (WRDI) (04h)
preliminary
The Write Disable instruction (Figure 10) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program, Sector Erase, Half Block Erase (HBE), Block Erase (BE) and Chip
Erase instructions.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 10. Write Disable Instruction Sequence Diagram
Figure 10.1 Write Enable/Disable Instruction Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
24
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Read Status Register (RDSR) (05h)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register
continuously, as shown in Figure 11.
The instruction sequence is shown in Figure 11.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 11. Read Status Register Instruction Sequence Diagram
Figure 11.1 Read Status Register Instruction Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Table 7. Status Register Bit Locations
SR.7
SRP bit
OTP_LOCK bit
SR.6
EBL bit
(Enable boot
lock)
WXDIS bit
SR.5
SR.4
SR.3
SR.2
BP3 bit
BP2 bit
BP1 bit
BP0 bit
HRSW bit
4KBL bit
(4KB Boot Lock)
TB bit
(Top / Bottom Protect)
SR.1
SR.0
WEL bit
WIP bit
Reserved
Table 7.1 Status Register Bit Locations (In Normal mode)
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
SRP
Status Register
Protect
EBL bit
(Enable Boot
Lock)
BP3 bit
(Block Protect)
BP2 bit
(Block Protect)
BP1 bit
(Block Protect)
BP0 bit
(Block Protect)
WEL bit
(Write Enable
Latch)
WIP bit
(Write In Progress
bit)
1 = status register
write disable
1 = Lock selected
64KBBlock/Sector
(note 2)
(note 2)
(note 2)
(note 2)
1 = write enable
0 = not write
enable
1 = write operation
0 = not in write
operation
Non-volatile/
Volatile bit
Non-volatile/
Volatile bit
Non-volatile/
Volatile bit
Non-volatile/
Volatile bit
Non-volatile/
Volatile bit
Non-volatile/
Volatile bit
indicator bit
indicator bit
SR.1
SR.0
WEL bit
(Write Enable
Latch)
WIP bit
(Write In Progress
bit)
1 = write enable
0 = not write
enable
1 = write operation
0 = not in write
operation
indicator bit
indicator bit
Table 7.2 Status Register Bit Locations (In OTP mode)
SR.7
SR.6
OTP_LOCK bit
1 = OTP sector is
protected
OTP bit
SR.5
SR.4
SR.3
WXDIS bit
HRSW bit
(WP# and
4KBL bit
(HOLD#/RESET#
HOLD#/RESET#
(4KB Boot Lock)
switch)
disabled)
1 = WP# and
HOLD#/RESET#
1 = RESET#
disable
enable
1 = Sector
0 = WP# and
0 = HOLD#
0 = 64KB-Block
HOLD#/RESET#
enable
(default 0)
enable
(default 0)
(default 0)
OTP / Volatile bit OTP / Volatile bit OTP / Volatile bit
SR.2
TB bit
(Top / Bottom
Protect)
1 = Bottom
0 = Top
(default 0)
OTP / Volatile bit
Reserved
bit
Note
1. In OTP mode, SR.7 bit is served as OTP_LOCK bit; SR.6 bit is served as WXDIS bit; SR.5 bit is served
as HRSW bit; SR.4 bit is served as 4KBL bit; SR.3 bit is served as TB bit; SR.1 bit is served as WEL bit
and SR.0 bit is served as WIP bit.
2. See the table 3 “Protected Area Sizes Sector Organization”.
3. When executed the (RDSR) (05h) command, the WIP (SR.0) value is the same as WIP (SR2.0) in
table 8.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP3,
BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected
against Page Program (PP), Quad Input Page Program (QPP), Sector Erase (SE) and , Half Block Erase
(HBE), Block Erase (BE), instructions. The Block Protect (BP3, BP2, BP1, BP0) bits can be written and
provided that the Hardware Protected mode has not been set. The Chip Erase (CE) instruction is
executed if and only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0 and EBL bit is 0.
EBL bit. The Enable Boot Lock (EBL) bit is used to enable the Boot Lock feature. When this bit is
programmed to ‘1’, the sector/block selected by the TB bit and 4KBL bit will be locked.
SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to
be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and
Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, SR.5,
SR.4, SR.3, SR.2) become read-only bits and the Write Status Register (WRSR) instruction is no longer
accepted for execution.
In OTP mode, SR.7, SR.6, SR.5, SR.4, SR.3, SR.1 and SR.0 are served as OTP_Lock bit, WXDIS bit,
HRSW bit, 4KBL bit, TB bit, WEL bit and WIP bit.
TB bit. The Top/Bottom Protect Bit (TB) controls if the Block Protect Bits (BP3, BP2, BP1, BP0) protect
from the Top (TB = 0) or the Bottom (TB = 1) of the array as shown in the Status Register Memory
Protection table. It also controls if the Top (TB=0) or the Bottom (TB=1) 64KB-block/sector is protected
when Boot Lock feature is enabled. The factory default setting is TB = 0. The TB bit can be set with the
Write Status Register instruction in OTP mode.
4KBL bit, The 4KB Boot Lock bit (4KBL) is set by WRSR command in OTP mode. It is used to set the
protection area size as block (64KB) or sector (4KB).
WXDIS bit. The WP# and HOLD#/RESET# Disable bit (WXDIS bit), OTP / Volatile bit, it indicates the
WP# and HOLD#/RESET# are enabled or not. When it is “0” (factory default), the WP# and
HOLD#/RESET# are enabled. On the other hand, while WXDIS bit is “1”, the WP# and HOLD#/RESET#
are disabled. If the system executes Quad mode commands, this WXDIS bit becomes no affection
since WP# and HOLD#/RESET# function will be disabled by Quad mode commands.
HRSW bit. The HOLD#/RESET# switch bit (HRSW bit), OTP / Volatile bit, the HRSW bit is used to
determine whether HOLD# or RESET# function should be implemented on the hardware pin. When it is
“0” (factory default), the pin acts as HOLD#; when it is “1”, the pin acts as RESET#. However, HOLD# or
RESET# functions are only available when WXDIS bit is “0”. If WXDIS bit is set to “1”, the HOLD# and
RESET# functions are disabled, the pin acts as a dedicated data I/O pin.
OTP_LOCK bit. This bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal sector
while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command, the OTP sector is
protected from program and erase operation. The OTP_LOCK bit can only be programmed once.
Reserved bit. Status Register bit locations SR.2 in OTP mode is reserved for future use.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Read Status Register 2 (RDSR 2) (09h)
The Read Status Register 2 (RDSR2) instruction allows the Status Register 2 to be read. The Status
Register 2 may be read at any time, even while a Write Suspend or Write Resume cycle is in progress.
When one of these bytes is in progress, it is recommended to check the Write In Progress (WIP) bit
before sending a new instruction to the device. It is also possible to read the Read Status Register 2
continuously, as shown in Figure 12.
The instruction sequence is shown in Figure 12.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 12. Read Status Register 2 Instruction Sequence Diagram
Figure 12.1 Read Status Register 2 Instruction Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Table 8. Status Register 2 Bit Locations
SR2.7
Reserved
bit
SR2.6
SR2.5
Erase Fail
Flag
Program Fail
Flag
1 = indicate
Erase failed
0 = normal
Erase
succeed
(default = 0)
volatile bit
Read Only
1 = indicate
Program failed
0 = normal
Program
succeed
(default = 0)
volatile bit
Read Only
SR2.4
SR2.3
SR2.2
SR2.1
WIP
(Write In
Progress bit)
(Note 1)
WSP
WSE
(Write Suspend (Write Suspend
Program bits) Erase status bit)
Reserved
bit
1 = Program
1 = Erase
suspended
suspended
0 = Program is 0 = Erase is not
not suspended
suspended
volatile bit
Read Only
volatile bit
Read Only
SR2.0
Reserved
bit
1 = write
operation
0 = not in
write
operation
volatile bit
Read Only
Note:
1. The default of each volatile bit is “0” at Power-up or after reset.
2. When executed the (RDSR 2) (09h) command, the WIP (SR2.0) value is the same as WIP (SR.0) in
table 7.
The status and control bits of the Suspend Status Register 2 are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WSE bit. The Write Suspend Erase Status (WSE) bit indicates when an Erase operation has been
suspended. The WSE bit is “1” after the host issues a suspend command during an Erase operation.
Once the suspended Erase resumes, the WSE bit is reset to “0”.
WSP bit. The Write Suspend Program Status (WSP) bit indicates when a Program operation has been
suspended. The WSP is “1” after the host issues a suspend command during the Program operation.
Once the suspended Program resumes, the WSP bit is reset to “0”.
Reserved bit. Status Register 3 bit locations SR2.1、SR2.4 and SR2.7 are reserved for future use.
Current devices will read 0 for these bit locations. It is recommended to mask out the reserved bit when
testing the Suspend Status Register. Doing this will ensure compatibility with future devices.
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This
bit will also be set when the user attempts to program a protected main memory region or a locked OTP
region. This bit can indicate whether one or more of program operations fail, and can be reset by
Program (PP), Quad Input Page Program (QPP) or Erase (SE, HBE/BE or CE) instructions.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. This bit will
also be set when the user attempts to erase a protected main memory region or a locked OTP region.
This bit can indicate whether one or more of erase operations fail, and can be reset by Program (PP),
Quad Input Page Program (QPP) or Erase (SE, HBE/BE or CE) instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Read Status Register 3 (RDSR 3) (95h)
The Read Status Register 3 (RDSR3) instruction allows the Status Register 3 to be read. The Status
Register 3 may be read at any time, even while a Write Suspend or Write Resume cycle is in progress.
When one of these bytes is in progress, it is recommended to check the Write In Progress (WIP) bit
before sending a new instruction to the device. It is also possible to read the Read Status Register 3
continuously, as shown in Figure 13.
The instruction sequence is shown in Figure 13.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 13. Read Status Register 3 Instruction Sequence Diagram
Figure 13.1 Read Status Register 3 Instruction Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
The status and control bits of the Status Register 3 are as follows:
Output Drive Strength. The Output Drive Strength (SR3.3 and SR3.2) bits indicate the status of output
Drive Strength in I/O pins.
Dummy Byte. The Dummy Byte (SR3.5 and SR3.4) bits indicate the status of the number of dummy
byte in high performance read.
Reserved bit. SR3.7, SR3.6, SR3.1 and SR3.0 are reserved for future use.
Table 9. Status Register 3 Bit Locations
SR3.7
SR3.6
SR3.5
SR3.4
Dummy Byte
Default = 00
volatile bit
volatile bit
SR3.2
SR3.1
SR3.0
Output Drive
Strength
00 = 3 Bytes
01 = 2 Bytes
10 = 4 Bytes
11 = 5 Bytes
Reserved Reserved
volatile bit
SR3.3
(1)
00 = Full Drive (default) Reserved
01 = 67% (2/3) Drive
10 = 50% (1/2) Drive
11 = 33% (1/3) Drive
volatile bit
volatile bit
volatile bit
volatile bit
Reserved
volatile bit
Note:
1. 2 Bytes (4 clocks in Quad mode), 3 Bytes (6 clocks in Quad mode),
4 Bytes (8 clocks in Quad mode), 5 Bytes (10 clocks in Quad mode)
Table 10. SR3.4 and SR3.5 Status (for Dummy Bytes)
Instruction Name
Op Code
Fast Read
0Bh
Quad IO Fast Read
EBh
Dummy Byte settings
sending Quad
Output Fast Read (6Bh) instruction -> 24-bit address on DQ0 -> 8 dummy clocks -> data out interleave
on DQ3, DQ2, DQ1 and DQ0 -> to end Quad Output Fast Read (6Bh) operation can use CS# to high at
any time during data out, as shown in Figure 19. The WP#(DQ2) and HOLD#/RESET#(DQ3) need to
drive high before address input if WXDIS bit in Status Register is 0.
CS#
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
CLK
Command
DQ0
3 Address bytes
(24 clocks)
6Bh
A23
A21
A3
A2
A1
A0
*
High Impedance
DQ1
A22
High Impedance
DQ2
High Impedance
DQ3
* = MSB
CS#
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
CLK
DQ0 switches from
Input to Output
Dummy Byte
DQ0
DQ1
High Impedance
A0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
D7
High Impedance
High Impedance
DQ2
High Impedance
DQ3
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data
Byte 4
Data
Byte 5
Figure 19. Quad Output Fast Read Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
37
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Quad Input / Output FAST_READ (EBh)
preliminary
The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)
instruction except that address and data bits are input and output through four pins, DQ0, DQ1, DQ2 and
DQ3 and six dummy clocks are required prior to the data output. The Quad I/O dramatically reduces
instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read
mode. The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O
pins) shift out on the falling edge of CLK at a maximum frequency F R. The first address can be any
location. The address is automatically increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single Quad Input/Output FAST_READ
instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing Quad Input/Output FAST_READ instruction, the following address/dummy/data out will perform
as 4-bit instead of previous 1-bit.
The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low -> sending
Quad Input/Output FAST_READ (EBh) instruction -> 24-bit address interleave on DQ3, DQ2, DQ1 and
DQ0 -> 6 dummy clocks -> data out interleave on DQ3, DQ2, DQ1 and DQ0 -> to end Quad Input/Output
FAST_READ (EBh) operation can use CS# to high at any time during data out, as shown in Figure 20.
The instruction sequence is shown in Figure 20.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 20. Quad Input / Output Fast Read Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
38
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 20.1. Quad Input / Output Fast Read Instruction Sequence in QPI Mode
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit
address interleave on DQ3, DQ2, DQ1 and DQ0 -> performance enhance toggling bit P[7:0] -> 4 dummy
clocks -> data out interleave on DQ3, DQ2, DQ1 and DQ0 till CS# goes high -> CS# goes low (reduce
Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit random access address, as shown in
Figure 21.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. These
commands will reset the performance enhance mode. And afterwards CS# is raised or issuing FFh
command (CS# goes high -> CS# goes low -> sending FFh -> CS# goes high) instead of no toggling,
the system then will escape from performance enhance mode and return to normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 21.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
39
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 21. Quad Input/Output Fast Read Enhance Performance Mode Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
40
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 21.1 Quad Input/Output Fast Read Enhance Performance Mode Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
41
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Write Status Register 3 (C0h)
The Write Status Register 3 (C0h) command can be used to set output drive strength in I/O pins and the
number of dummy byte in high performance read. To set the output drive strength and the number of
dummy byte to the host driver CS# low, sends the Write Status Register 3 (C0h) and one data byte,
then drivers CS# high, After power-up or reset, the output drive strength is set to full drive (00b) and the
dummy byte is set to 3 bytes (00b), please refer to Table 9 for Status Register 3 data and Figure 22 for
the sequence. In QPI mode, a cycle is two nibbles, or two clocks, long, most significant nibble first.
The instruction sequence is shown in Figure 22.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
Command
DI
1 data byte
C0h
D7
D6
D5
D4
D3
D2
D1
D0
*
High Impedance
DO
* = MSB
Figure 22. Write Status Register 3 Instruction Sequence Diagram
Figure 22.1 Write Status Register 3 Instruction Sequence Diagram in QPI mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
42
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Page Program (PP) (02h)
The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least
significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the same page (from the address whose 8 least
significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 23. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven high, the self-timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page
Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 23.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 23. Page Program Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 23.1 Program Instruction Sequence in QPI Mode
Quad Input Page Program (QPP) (32h)
The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed at
previously erased (FFh) memory locations using four pins: DQ0, DQ1, DQ2 and DQ3. The Quad Page
Program can improve performance for PROM Programmer and applications that have slow clock
speeds < 5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page
Program instruction since the inherent page program time is much greater than the time it take to clockin the data.
To use Quad Page Program (QPP) the WP# and HOLD#/RESET# Disable (WXDIS) bit in Status
Register must be set to 1. A Write Enable instruction must be executed before the device will accept the
Quad Page Program (QPP) instruction (SR.1, WEL=1). The instruction is initiated by driving the CS# pin
low then shifting the instruction code “32h” followed by a 24-bit address (A23-A0) and at least one data
byte, into the IO pins. The CS# pin must be held low for the entire length of the instruction while data is
being sent to the device. All other functions of Quad Page Program (QPP) are identical to standard
Page Program. The Quad Page Program (QPP) instruction sequence is shown in Figure 24.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
preliminary
CS#
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
CLK
Command
DQ0
32h
3 Address bytes
(24 clocks)
A23
A22
A21
A3
A2
A1
A0
*
DQ1
DQ2
DQ3
* = MSB
CS#
31
32
33
34
35
36
37
534 535 536 537 538 539 540 541 542 543
CLK
Data
Byte
1
DQ0
A0
Data
Byte
2
Data
Byte
3
Data
Byte
252
Data
Byte
253
Data
Byte
254
Data
Byte
255
Data
Byte
256
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
DQ1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
DQ2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
DQ3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
*
*
*
*
*
*
*
*
Figure 24. Quad Input Page Program Instruction Sequence Diagram (SPI Mode only)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
45
Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
Write Suspend (B0h)
preliminary
Write Suspend allows the interruption of Sector Erase, Block Erase or Page Program operations in
order to erase, program, or read data in another portion of memory. The original operation can be
continued with Write Resume command. The instruction sequence is shown in Figure 25.
Only one write operation can be suspended at a time; if an operation is already suspended, the device
will ignore the Write Suspend command. Write Suspend during Chip Erase is ignored; Chip Erase is not
a valid command while a write is suspended.
Suspend to suspend ready timing: 20us.
Resume to another suspend timing: 1ms.
Figure 25. Write Suspend Instruction Sequence Diagram
Write Suspend During Sector Erase or Block Erase
Issuing a Write Suspend instruction during Sector Erase or Block Erase allows the host to program or
read any sector that was not being erased. The device will ignore any programming commands pointing
to the suspended sector(s). Any attempt to read from the suspended sector(s) will out put unknown data
because the Sector or Block Erase will be incomplete.
To execute a Write Suspend operation, the host drives CS# low, sends the Write Suspend command
cycle (B0h), then drives CS# high. A cycle is two nibbles long, most significant nibble first. The Suspend
Status register indicates that the erase has been suspended by changing the WSE bit from “0” to “1”,
but the device will not accept another command until it is ready. To determine when the device will
accept a new command, poll the WIP bit in the Suspend Status register or after issue program suspend
command, latency time 20us is needed before issue another command. For “Suspend to Read”,
“Resume to Read”, “Resume to Suspend” timing specification please note Figure 26.1, 26.2 and 26.3.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
Write Suspend During Page Programming
preliminary
Issuing a Write Suspend instruction during Page Programming allows the host to erase or read any
sector that is not being programmed. Erase commands pointing to the suspended sector(s) will be
ignored. Any attempt to read from the suspended page will output unknown data because the program
will be incomplete.
To execute a Write Suspend operation, the host drives CS# low, sends the Write Suspend command
cycle (B0h), then drives CS# high. A cycle is two nibbles long, most significant nibble first. The Suspend
Status register indicates that the programming has been suspended by changing the WSP bit from “0”
to “1”, but the device will not accept another command until it is ready. To determine when the device
will accept a new command, poll the WIP bit in the Suspend Status register or after issue program
suspend command, latency time 20us is needed before issue another command. For “Suspend to
Read”, “Resume to Read”, “Resume to Suspend” timing specification please note Figure 26.1, 26.2 and
26.3.
Figure 26.1 Suspend to Read Latency
Figure 26.2 Resume to Read Latency
Figure 26.3 Resume to Suspend Latency
The instruction sequence is shown in Figure 27.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
Write Resume (30h)
Write Resume restarts a Write command that was suspended, and changes the suspend status bit in
the Suspend Status register (WSE or WSP) back to “0”.
The instruction sequence is shown in Figure 27. To execute a Write Resume operation, the host drives
CS# low, sends the Write Resume command cycle (30h), then drives CS# high. A cycle is two nibbles
long, most significant nibble first. To determine if the internal, self-timed Write operation completed, poll
the WIP bit in the Suspend Status register, or wait the specified time tSE, tHBE, tBE or tPP for Sector Erase,
Block Erase, or Page Programming, respectively. The total write time before suspend and after resume
will not exceed the uninterrupted write times tSE, tHBE, tBE or tPP. Resume to another suspend operation
requires latency time of 1ms.
The instruction sequence is shown in Figure 27.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
47
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 27. Write Resume Instruction Sequence Diagram
Figure 27.1. Write Suspend/Resume Instruction Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 27.2. Write Suspend/Resume Flow
Note:
1. The ‘WIP’ can be either checked by command ‘09’or ‘05’ polling.
2. ‘Wait for write cycle’ can be referring to maximum write cycle time or polling the WIP.
3. ‘Wait for suspend latency’, after issue program suspend command, latency time 20us is needed
before issue another command or polling the WIP.
4. The ‘WSP’ and ‘WSE’ can be checked by command ‘09’ polling.
5. ‘Suspend done’ means the chip can do further operations allowed by suspend spec.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Sector Erase (SE) (20h)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see
Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low
for the entire duration of the sequence.
The instruction sequence is shown in Figure 28. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) or Boot Lock feature will be ignored.
The instruction sequence is shown in Figure 30.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 28. Sector Erase Instruction Sequence Diagram
32KB Half Block Erase (HBE) (52h)
The Half Block Erase (HBE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Half Block Erase (HBE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see
Table 2) is a valid address for the Half Block Erase (HBE) instruction. Chip Select (CS#) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 29. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Half Block Erase (HBE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is tHBE) is initiated. While the Half Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Half Block Erase cycle, and is 0 when it is completed. At some unspecified time before
the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Half Block Erase (HBE) instruction applied to a block which is protected by the Block Protect (BP3,
BP2, BP1, BP0) bits (see Table 3) or Boot Lock feature will be ignored.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
The instruction sequence is shown in Figure 30.1 while using the Enable Quad Peripheral Interface
preliminary
mode (EQPI) (38h) command.
Figure 29. 32KB Half Block Erase Instruction Sequence Diagram
64K Block Erase (BE) (D8h)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see Table 2) is a
valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 30. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) or Boot Lock feature will be ignored.
The instruction sequence is shown in Figure 30.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
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Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
preliminary
Figure 30. 64K Block Erase Instruction Sequence Diagram
Figure 30.1 Block/Sector Erase Instruction Sequence in QPI Mode
Chip Erase (CE) (C7h/60h)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction
code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 31. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not executed. As
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Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose duration is tCE) is
preliminary
initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if all Block Protect (BP3, BP2, BP1, BP0) bits are 0
and EBL bit is 0. The Chip Erase (CE) instruction is ignored if one or more blocks are protected.
The instruction sequence is shown in Figure 31.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 31. Chip Erase Instruction Sequence Diagram
Figure 31.1 Chip Erase Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Deep Power-down (DP) (B9h)
preliminary
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep
Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce
the standby current (from ICC1 to ICC2, as specified in Table 17.)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down, Read Device ID (RDI) and Software Reset instruction which release
the device from this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction
also allows the Device ID of the device to be output on Serial Data Output (DO).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in
the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 32. Chip Select (CS#) must be driven High after the eighth
bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not
executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP before the supply
current is reduced to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 32. Deep Power-down Instruction Sequence Diagram
Release from Deep Power-down and Read Device ID (RDI)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the
Release from Deep Power-down and Read Device ID (RDI) instruction. Executing this instruction takes
the device out of the Deep Power-down mode.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that
is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for
reasons of backward compatibility, only, and should not be used for new designs. New designs should,
instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction.
When used only to release the device from the power-down state, the instruction is issued by driving the
CS# pin low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 33. After the
time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The CS# pin must remain high during the tRES1 time duration.
This Data Sheet may be revised by subsequent versions
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
preliminary
driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy bytes.
The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 34. The Device ID value for the XM25QH128A are listed in Table 6. The Device ID can be read
continuously. The instruction is completed by driving CS# high.
When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was
not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate.
If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power
mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2 (max), as
specified in Table 19. Once in the Stand-by Power mode, the device waits to be selected, so that it can
receive, decode and execute instructions.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep
Power-down and Read Device ID (RDI) instruction always provides access to the 8bit Device ID of the
device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read Device ID (RDI) instruction while an Erase, Program or
Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
Figure 33. Release Power-down Instruction Sequence Diagram
Figure 34. Release Power-down / Device ID Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
55
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Read Manufacturer / Device ID (90h)
preliminary
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for XMC (20h)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in Figure 35. The Device ID values for the XM25QH128A are listed in Table 6. If the 24-bit
address is initially set to 000001h the Device ID will be read first
The instruction sequence is shown in Figure 35.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
Figure 35. Read Manufacturer / Device ID Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
56
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 35.1. Read Manufacturer / Device ID Diagram in QPI Mode
Read Identification (RDID) (9Fh)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read,
followed by two bytes of device identification. The device identification indicates the memory type in the
first byte , and the memory capacity of the device in the second byte .
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction
should not be issued while the device is in Deep Power down mode.
The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the instruction
is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out
on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock . The instruction
sequence is shown in Figure 36. The Read Identification (RDID) instruction is terminated by driving Chip
Select High at any time during data output.
When Chip Select is driven High, the device is put in the Standby Power mode. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
The instruction sequence is shown in Figure 36.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 36. Read Identification (RDID)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 36.1. Read Identification (RDID) in QPI Mode
Enter OTP Mode (3Ah)
This Flash support OTP mode to enhance the data protection, user can use the Enter OTP mode (3Ah)
command for entering this mode. In OTP mode, the Status Register S7 bit is served as OTP_LOCK bit,
S6 bit is served as WXDIS bit, S5 bit is served as HRSW bit, S4 bit is served as 4KBL bit, S3 bit is
served as TB bit, S1 bit is served as WEL bit and S0 bit is served as WIP bit. They can be read by
RDSR command.
This Flash has an extra 512 bytes OTP sector, user must issue ENTER OTP MODE command to read,
program or erase OTP sector. After entering OTP mode, the OTP sector is mapping to sector 4095,
SRP bit becomes OTP_LOCK bit. The Chip Erase, Block Erase and Half Block Erase commands are
also disabled.
In OTP mode, user can read other sectors, but program/erase other sectors only allowed when they are
not protected by Block Protect (BP3, BP2, BP1, BP0) bits and Block Lock feature. The OTP sector can
only be erased by Sector Erase (20h) command. The Chip Erase (C7h/ 60h), 64K Block Erase (D8h)
and 32K Half Block Erase (52h) commands are disable in OTP mode.
Table 11. OTP Sector Address
Sector
Sector Size
Address Range
4095
512 byte
FFF000h – FFF1FFh
Note: The OTP sector is mapping to sector 4095
WRSR command is used to program OTP_LOCK bit, TB bit, 4KBL bit to ‘1‘, but these bits only can be
programmed once. User can use WRDI (04h) command to exit OTP mode.
The instruction sequence is shown in Figure 37.1 while using the Enable Quad Peripheral Interface mode
(EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 37. Enter OTP Mode
Figure 37.1 Enter OTP Mode Sequence in QPI Mode
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Read SFDP Mode and Unique ID Number (5Ah)
preliminary
Read SFDP Mode
XM25QH128A features Serial Flash Discoverable Parameters (SFDP) mode. Host system can retrieve
the operating characteristics, structure and vendor specified information such as identifying information,
memory size, operating voltage and timing information of this device by SFDP mode.
The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read SFDP
Mode is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the
rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial
Data Output (DO), each bit being shifted out, at a maximum frequency FR, during the falling edge of
Serial Clock (CLK).
The instruction sequence is shown in Figure 38. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
The whole memory can, therefore, be read with a single Serial Flash Discoverable Parameters (SFDP)
instruction. When the highest address is reached, the address counter rolls over to 0x00h, allowing the
read sequence to be continued indefinitely. The Serial Flash Discoverable Parameters (SFDP)
instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any
time during data output. Any Read Data Bytes at Serial Flash Discoverable Parameters (SFDP)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure 38. Read SFDP Mode Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH128A
Table 12. Serial Flash Discoverable Parameters (SFDP) Signature and Parameter Identification
preliminary
Data Value (Advanced Information)
Description
SFDP Signature
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers
(NPH)
Unused
ID Number(JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length (in double
word)
Parameter Table Pointer (PTP)
Unused
ID number(Manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length(in double
word)
Parameter Table Pointer(PTP)
Unused
Add (h)
(Byte)
DW Add
(Bit)
Data
00h
01h
02h
03h
04h
05h
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
15 : 08
53h
46h
44h
50h
00h
01h
06h
23 : 16
01h
07h
31 : 24
FFh
08h
07 : 00
00h
09h
15 : 08
00h
Star from 0x00
0Ah
23 : 16
01h
Star from 0x01
0Bh
31 : 24
09h
How many DWORDs in the parameter
table
0Ch
0Dh
0Eh
0Fh
10h
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
30h
00h
00h
FFh
20h
11h
15 : 08
00h
Start from 00h
12h
23 : 16
01h
Start from 01h
13h
31 : 24
04h
How many DWORDs in the parameter
table
14h
15h
16h
17h
07 : 00
15 : 08
23 : 16
31 : 24
60h
00h
00h
FFh
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
62
Comment
Fixed: 50444653h
Star from 0x00
Star from 0x01
This number is 0-based.Therefore,0
indicates 1 parameter header.
Reserved
00h:it indicates a JEDEC specified
header.
First address of JEDEC Flash
Parameter table
It indicates manufacture ID
First address of VENDOR Flash
Parameter table
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 1/9
Description
Add (h) DW Add
(Byte)
(Bit)
preliminary
Data
Comment
01 : 00
01b
00:Reserved, 01:4KB erase, 10:Reserved,
11:not supported 4KB erase
02
1b
03
0b
04
0b
07 : 05
15 : 08
111b
20h
16
1b
0 = not supported
1 = supported
18 : 17
00b
00:3Byte only, 01:3 or 4Byte
10:4Byte only, 11:Reserved
19
0b
0 = not supported
1 = supported
(1-2-2) Fast Read
20
1b
0 = not supported
1 = supported
(1-4-4) Fast Read
21
1b
(1-1-4) Fast Read
22
1b
23
31 : 24
1b
FFh
Block / Sector Erase sizes
Write Granularity
Volatile Status Register Block Protect
bits
Write Enable Instruction Select for
Writing to Volatile Status Registers
Unused
4KB Erase Instruction
(1-1-2) Fast Read
30h
31h
(1)
Address Bytes Number used in
addressing flash array
Double Transfer Rate(DTR) clocking
32h
Unused
Unused
33h
0:1Byte,1:64Byte or larger
0: Block Protect bits in device's status
register are solely non-volatile or may be
programmed either as volatile using the
50h instruction for write enable or nonvolatile using the 06h instruction for write
enable.
1: Block Protect bits in device's status
register are solely volatile.
0:use 50h instruction
1:use 06h instruction
Contains 111b and can never be changed
0 = not supported
1 = supported
0 = not supported
1 = supported
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 2/9
Description
Flash Memory Density
Add (h)
(Byte)
37h : 34h
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
DW Add
(Bit)
31 : 00
63
Data
Comment
For densities 2 gigabits or less, bit-31
is set to 0b. The field 30:0 defines the
size in bits.
Example: 00FFFFFFh = 16 megabits
For densities 4 gigabits and above,
07FFFFFFh bit-31 is set to 1b. The field 30:0
defines ‘N’ where the
density is computed as 2^N bits (N
must be >= 32).
Example: 80000021h = 2^33 = 8
gigabits
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 3/9
Description
(1-4-4)Fast Read number of Wait
(2)
states
(1-4-4)Fast Read number of Mode
(3)
Clocks
(1-4-4)Fast Read instruction
(1-1-4)Fast Read Number of Wait
states
(1-1-4)Fast Read Number of Mode
Clocks
(1-1-4)Fast Read Instruction
Add (h) DW Add
(Byte)
(Bit)
Data
04 : 00
00100b
07 : 05
010b
15 : 08
EBh
20 : 16
01000b
23 : 21
000b
31 : 24
6Bh
38h
39h
3Ah
3Bh
preliminary
Comment
00000b:Not supported;00100b:4
00110b:6 01000b:8
Mode clocks:
000b:Not supported;010: 2 clocks
00000b:Not suppoted;00100b:4
00100b:6; 01000b:8
Mode clocks:
000b:Not supported;010b:2 clocks
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 4/9
Description
Add (h) DW Add
(Byte)
(Bit)
(1-1-2)Fast Read Number of Wait
states
(1-1-2)Fast Read Number of Mode
Clocks
3Ch
(1-1-2)Fast Read Instruction
3Dh
(1-2-2)Fast Read Number of Wait
states
(1-2-2)Fast Read Number of Mode
Clocks
(1-2-2)Fast Read Instruction
Data
04 : 00
01000b
00000b:Not supported;00100b:4
00110b:6;01000b:8
07 : 05
000b
Mode clocks:
000b:Not supported;010:2 clocks
15 : 08
3Bh
20 : 16
00100b
00000b:Not supported;00100b:4 0
0110b:6;01000b:8
23 : 21
000b
Mode clocks:
000b:Not supported;010:2 clocks
31 : 24
BBh
3Eh
3Fh
Comment
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 5/9
Description
Add (h) DW Add
(Byte)
(Bit)
(2-2-2)Fast Read
Unused
40h
(4-4-4)Fast Read
Unused
Unused
43h : 41h
Data
00
0b
03 : 01
111b
04
1b
07 : 05
31 : 08
111b
FFFFFFh
Comment
0 = not supported
1 = supported
0 = not supported
1 = supported
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 6/9
Description
Unused
(2-2-2)Fast Read Number of Wait
states
(2-2-2) Fast Read Number of Mode
Clocks
(2-2-2)Fast Read Instruction
Add (h) DW Add
(Byte)
(Bit)
45h : 44h 15 : 00
Data
FFh
20 : 16
00000b
00000b:Not supported;00100b:4
00110b:6;01000b:8
23 : 21
000b
Mode Clocks:
000b:Not supported;010:2 clocks
31 : 24
FFh
46h
47h
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Comment
64
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 7/9
Description
Unused
(4-4-4)Fast Read Number of Wait
states
(4-4-4) Fast Read Number of Mode
Clocks
(4-4-4)Fast Read Instruction
Add (h) DW Add
(Byte)
(Bit)
49h : 48h 15 : 00
Data
FFFFh
20 : 16
00100b
00000b:Not supported;00100b:4
00110b:6;01000b:8
23 : 21
010b
Mode Clocks:
000b:Not supported;010:2 clocks
31 : 24
EBh
4Ah
4Bh
Comment
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 8/9
Description
Add (h) DW Add
(Byte)
(Bit)
Data
Comment
N
Erase Type 1 Size
4Ch
07 : 00
0Ch
Erase Type 1 Erase Instruction
4Dh
15 : 08
20h
Erase Type 2 Size
4Eh
23 : 16
0Fh
Erase Type 2 Erase Instruction
4Fh
31 : 24
52h
(4)
Sector/block size=2 bytes
0Ch:4KB;0Fh:32KB;10h:64KB
N
Sector/block size=2 bytes
00h:NA;0Fh:32KB;10h:64KB
Table 13. Parameter ID (0) JEDEC Flash Parameter Tables 9/9
Description
Add (h) DW Add
(Byte)
(Bit)
Data
Comment
N
Sector/block size=2 bytes
00h:NA;0Fh:32KB;10h:64KB
Erase Type 3 Size
50h
07 : 00
10h
Erase Type 3 Erase Instruction
51h
15 : 08
D8h
Erase Type 4 Size
52h
23 : 16
00h
Sector/block size=2 bytes
00h:NA;0Fh:32KB;10h:64KB
Erase Type 4 Erase Instruction
53h
31 : 24
FFh
Not support
N
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
65
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 14. Parameter ID (0) Flash Parameter Tables
Add (h) DW Add
Description
(Byte)
(Bit)
07:00
61h:60h
Vcc supply maximum voltage
15:08
Vcc supply minimum voltage
00h
36h
23:16
00h
31:24
27h
63h:62h
H/W Reset# pin
0
H/W Hold# pin
1
Deep Power Down Mode
2
S/W Reset
3
S/W Reset Instruction
preliminary
Data
65h:64h
11:04
Program suspend/resume
12
Erase suspend/resume
13
Unused
14
Wrap-Around Read mode
15
799Fh
Wrap-Around Read mode instruction
66h
23:16
00h
Wrap-Around Read data length
67h
31:24
00h
0
Individual block lock
Individual block lock
bit(Volatile/Nonvolatile)
Individual block lock Instruction
Individual block lock Volatile protect
bit default protect status
Secured OTP
1
2000h=2.000V
2700h=2.700V
3600h=3.600V
1650h=1.65V
1750h=1.75V
2250h=2.25V
2300h=2.3V
2350h=2.35V
2650h=2.65V
2700h=2.7V
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
Reset Enable(66h)should be issued
before Reset instruction
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
Not support
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
0 = not supported
1 = supported
0:Volatile 1:Nonvolatile
09:02
10
6Bh:68h
12
Permanent Lock
13
6Fh:6Ch
0:Protect 1:Unprotect
F800h
11
Read Lock
Unused
Unused
Unused
Comment
15:14
31:16
31:00
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
FFh
FFh
Note 1: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the
instruction (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),
(2-2-2),and (4-4-4)
Note 2: Wait States is required dummy clock cycles after the address bits or optional mode clocks.
Note 3: Mode clocks is optional control bits that follow the address bits. These bits are driven by the
system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 4: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 5: All unused and undefined area data is blank FFh.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
66
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Read Unique ID Number
preliminary
The Read Unique ID Number instruction accesses a factory-set read-only 96-bit number that is unique
to each XM25QH128A device. The ID number can be used in conjunction with user software methods
to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the
CS# pin low and shifting the instruction code “5Ah” followed by a three bytes of addresses, 0x80h, and
one byte of dummy clocks. After which, the 96-bit ID is shifted out on the falling edge of CLK as shown
in Figure 38.
Table 15. Unique ID Number
Description
Add (h)
(Byte)
DW Add
(Bit)
Data
Unique ID Number
80h : 8Bh
95 : 00
By die
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
67
Comment
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Power-up Timing
preliminary
All functionalities and DC specifications are specified for a VCC ramp rate of greater than 1V per 100 ms
(0V to 2.7V in less than 270 ms). See Table 16 and Figure 39 for more information.
Figure 39. Power-up Timing
Table 16. Power-Up Timing
Symbol
TPU-READ
(1)
TPU-WRITE
(1)
Parameter
Min.
Unit
VCC Min to Read Operation
100
µs
VCC Min to Write Operation
100
µs
Note:
1. This parameter is measured only for initial qualification and after a design or process change that
could affect this parameter.
.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The
Status Register contains 00h (all Status Register bits are 0).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
68
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 17. DC Characteristics
preliminary
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
ILI
Input Leakage Current
1
±2
µA
ILO
Output Leakage Current
1
±2
µA
ICC1
Standby Current
CS# = VCC, VIN = VSS or
VCC
20
µA
ICC2
Deep Power-down
Current
CS# = VCC, VIN = VSS or
VCC
20
µA
10
25
mA
CLK = 0.1 VCC / 0.9 VCC at
104MHz, DQ = open
ICC3
ICC4
ICC5
ICC6
ICC7
CLK = 0.1 VCC / 0.9 VCC at
33MHz, DQ = open
CLK = 0.1 VCC / 0.9 VCC at
104MHz, Quad Output Read,
DQ = open
CLK = 0.1 VCC / 0.9 VCC at
33MHz, Quad Output Read,
DQ = open
5
12
mA
14
35
mA
7
17
mA
Operating Current (PP)
Operating Current
(WRSR)
Operating Current (SE)
CS# = VCC
9
30
mA
25
mA
CS# = VCC
13
25
mA
Operating Current (BE)
CS# = VCC
15
Operating Current (READ)
CS# = VCC
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 100 µA, Vcc=Vcc Min.
VOH
Output High Voltage
IOH = –100 µA , Vcc=Vcc
Min.
25
mA
– 0.5
0.2 VCC
V
0.7VCC
VCC+0.4
V
0.3
V
VCC-0.2
V
Table 18. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Max.
Load Capacitance
30
Input Rise and Fall Times
Unit
pF
5
ns
Input Pulse Voltages
0.2VCC to 0.8VCC
V
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VCC / 2
V
Output Timing Reference Voltages
Figure 40. AC Measurement I/O Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
69
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Table 19. AC Characteristics
preliminary
(Ta = - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Alt
Parameter
Serial SPI Clock Frequency for:
PP, QPP, SE, HBE, BE, CE, DP, RES, RDP,
WREN, WRDI, WRSR, WRSR3, Fast Read
Serial SPI Clock Frequency for:
RDSR, RDSR2, RDSR3, RDID,
Serial Dual/Quad Clock Frequency for:
PP, QPP, SE, HBE, BE, CE, DP, RES, RDP,
FR
fC
WREN, WRDI, WRSR, WRSR3, RDSR, RDSR2,
RDSR3, RDID, Fast Read, Dual Output Fast
Min
Typ
Max
Unit
D.C.
104
MHz
D.C.
104
MHz
D.C.
104
MHz
D.C.
104
MHz
Read, Dual I/O Fast Read
D.C.
80
MHz
fR
Serial Clock Frequency for:
Quad I/O Fast Read (3.0-3.6V)
Serial Clock Frequency for:
Quad I/O Fast Read (2.7-3.0V)
Serial Clock Frequency for READ
D.C.
50 4
MHz
tCH 1
Serial Clock High Time
3.5
ns
tCL1
Serial Clock Low Time
3.5
ns
tCLCH2
tCHCL 2
Serial Clock Rise Time (Slew Rate)
0.1
V / ns
Serial Clock Fall Time (Slew Rate)
0.1
V / ns
tSLCH
tCSS
CS# Active Setup Time
5
ns
tCHSH
CS# Active Hold Time
5
ns
tSHCH
CS# Not Active Setup Time
5
ns
tCHSL
CS# Not Active Hold Time
5
ns
tSHSL
tCSH
CS# High Time for read
CS# High Time for program/erase
10
30
ns
tSHSL2
tCSH
Volatile Register Write Time
50
ns
tSHQZ 2
tDIS
Output Disable Time
tCLQX
tHO
Output Hold Time
0
ns
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
6
ns
Data In Hold Time
3
ns
tHLCH
HOLD# Low Setup Time ( relative to CLK )
5
ns
tHHCH
HOLD# High Setup Time ( relative to CLK )
5
ns
tCHHH
HOLD# Low Hold Time ( relative to CLK )
5
ns
HOLD# High Hold Time ( relative to CLK )
5
ns
tCHHL
tCLQV
tV
tWHSL3
tSHWL
tDP
3
2
Output Valid from CLK
7
ns
Write Protect Setup Time before CS# Low
20
ns
Write Protect Hold Time after CS# High
100
ns
CS# High to Deep Power-down Mode
3
µs
3
µs
1.8
µs
50
ms
tW
CS# High to Standby Mode without Electronic
Signature read
CS# High to Standby Mode with Electronic
Signature read
Write Status Register Cycle Time
tPP
Page Programming Time
0.5
3
ms
tSE
Sector Erase Time
0.04
0.7
s
tHBE
Half Block Erase Time
0.2
1
s
tBE
Block Erase Time
0.3
2
s
tCE
Chip Erase Time
60
200
s
tRES1 2
tRES2 2
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
70
10
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
tHRST
RESET# low period to reset the device
1
tHRSL
RESET# high to next instruction
28
tSHRV
Deselect to RESET# valid in quad mode
8
tSR
Software Reset
Latency
µs
preliminary
µs
ns
WIP = write operation
28
µs
WIP = not in write operation
0
µs
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.4.
4. For speed inquire high than 50MHz, please call XMC for details.
Figure 41. Serial Output Timing
Figure 42. Input Timing
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
71
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 43. Hold Timing
CS#
CLK
tSHRV
RESET#
tHRST
tHRSL
Figure 44. Reset Timing
ABSOLUTE MAXIMUM RATINGS
Stresses above the values so mentioned above may cause permanent damage to the device. These
values are for a stress rating only and do not imply that the device should be operated at conditions up
to or above these values. Exposure of the device to the maximum rating values for extended periods of
time may adversely affect the device reliability.
Parameter
Value
Storage Temperature
-65 to +150
C
Plastic Packages
-65 to +125
C
Output Short Circuit Current
1
Unit
200
mA
Input and Output Voltage
2
(with respect to ground)
-0.5 to Vcc+0.5
V
Vcc
-0.5 to Vcc+0.5
V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
72
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of
up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V.
During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods up to 20ns. See figure below.
preliminary
RECOMMENDED OPERATING RANGES 1
Parameter
Value
Ambient Operating Temperature
Industrial Devices
Unit
C
-40 to 85
Operating Supply Voltage
Vcc
Full: 2.7 to 3.6
V
Notes:
1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
V
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
Table 20. CAPACITANCE
( VCC = 2.7-3.6V)
Parameter Symbol
Parameter Description
Test Setup
Max
Unit
CIN
Input Capacitance
VIN = 0
Typ
6
pF
COUT
Output Capacitance
VOUT = 0
8
pF
Note : Sampled only, not 100% tested, at TA = 25°C and a frequency of 20MHz.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
73
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
PACKAGE MECHANICAL
Figure 45. SOP 208mil 8L
SYMBOL
DIMENSION IN MM
NOR
1.975
0.15
1.825
5.275
7.90
5.275
1.27
0.425
0.65
MIN.
MAX
A
1.75
2.20
A1
0.05
0.25
A2
1.70
1.95
D
5.15
5.40
E
7.70
8.10
E1
5.15
5.40
e
----b
0.35
0.50
L
0.5
0.80
θ
00
40
80
Note : 1. Coplanarity: 0.1 mm
2. Max. allowable mold flash is 0.15 mm
at the pkg ends, 0.25 mm between leads.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
74
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 46. WSON 5x6 8L
DIMENSION IN MM
MIN.
NOR
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.04
A2
--0.20
--D
5.90
6.00
6.10
E
4.90
5.00
5.10
D2
3.30
3.40
3.50
E2
3.90
4.00
4.10
e
--1.27
--b
0.35
0.40
0.45
L
0.55
0.60
0.65
Note: 1. Coplanarity: 0.1 mm
SYMBOL
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
75
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
Figure 47. 24-ball Thin Profile Fine-Pitch Ball Grid Array (6 x 8 mm) Package
DIMENSION IN MM
MIN.
NOR
A
----A1
0.27
--0.21 REF
A2
0.54 REF
A3
6 BSC
D
8 BSC
E
D1
--3.00
E1
--5.00
e
--1.00
b
--0.40
Note : 1. Coplanarity: 0.1 mm
SYMBOL
MAX
1.20
0.37
---------
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
76
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
preliminary
ORDERING INFORMATION
XM25QH128A
H I G
X - xx
[1]
SPECIAL OPTIONS
xx = for UID, start from 01 to distinguish different
UID request
[1]
SPECIAL OPTIONS
T=Tape and Reel(packing method)
R = Tray packing
PACKAGING CONTENT
G = RoHS, Halogen-Free and REACH compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
H = SOP 208mil 8L
W = WSON 5x6 8L
B = TFBGA 6x8 24ball
BASE PART NUMBER
XM = Wuhan Xinxin Semiconductor Manufacturing.
Corp.
25QH = 3V Serial Flash with 4KB Uniform-Sector
128 = 128 Megabit (16,384K x 8)
A = version identifier
Notes:
1、This option code is not included on the part marketing.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
77
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
XM25QH128A
Revisions List
preliminary
Revision No Description
Date
A
B
C
D
E
F
Initial Release
2016/06/27
Add WSON(6x8mm) Package
Change the max value of tSE (from 0.3s to 0.4s)
2017/01/03
Change Table 12-14(SFDP)
2017/09/28
Update ORDERING INFORMATION
2017/10/19
Update ORDERING INFORMATION;
1.Change the max value of tSE (from 0.4s to 0.7s) in Table 19. AC
Characteristics
2.Delete PDIP, SOP16, WSON(6x8mm) Package type
3.Update the package name of SOP, WSON, TFBGA packages
1.Change normal read 83MHz to 50MHz in Page1
2. Add Parameter FR for Serial Clock Frequency for: Quad I/O Fast Read (3.03.6V), Max value 104MHz in Page70
3. Add Parameter FR for Serial Clock Frequency for: Quad I/O Fast Read (2.73.0V), max value 80MHz in Page70
4. Update the max value of fR from 83MHz to 50MHz in Page70
5. Add note4 for Table 19. AC Characteristics
2018/02/28
G
H
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
78
2017/05/03
2018/07/13
2018/08/06
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. H, Issue Date: 2018/08/06
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