Application Note: AN_SYR827/SYR828
High Efficiency 5.5V, 6A, 2.4MHz
I C Programmable, Synchronous Step Down Regulator
2
Preliminary Specification
General Description
Features
SYR827/SYR828 is a high efficiency 2.4MHz synchronous
step down DC/DC regulator IC capable of delivering up to
6A output currents. It can operate over a wide input voltage
range from 2.6V to 5.5V and integrate main switch and
synchronous switch with very low RDS (ON) to minimize the
conduction loss. The output voltage can be programmed
from 0.7125V to 1.5V through I2C interface.
•
•
SYR827/SYR828 is in a space saving, low profile
CSP1.56*1.96-20 package.
Ordering Information
SYR827/8□(□□
□□)□
□□ □
Temperature Code
Packa ge Code
Optiona l Spec Code
Ordering Number
SYR827PKC
SYR828PKC
Package Type
CSP1.56*1.96-20
CSP1.56*1.96-20
•
•
•
Input voltage range: 2.6V to 5.5V
2.4 MHz switching frequency minimizes the external
components
Typical 65uA quiescent current
Low RDS(ON) for internal switches (PFET/NFET):
28mΩ/17mΩ
Programmable Output Voltage: 0.7125V to 1.5V in
12.5mV steps
•
6A continuous output current capability.
•
Capable for 0.25uH inductor and 22uF Ceramic
Capacitor.
•
•
•
Hic-cup mode protection for hard short condition
RoHS Compliant and Halogen Free
Compact package: CSP1.56*1.96-20
Applications
Note
0x40H
0x41H
•
Smart-phone
•
Web-tablets
Typical Applications
L1:0.25uH
VIN:2.6~5.5V
VIN
CIN
22uF/6.3V
K1
K2
VOUT
LX
VOUT
COUT
22uF/6.3V
VSEL
EN
SCL
SDA
R1
1MΩ
R2
1MΩ
GND AGND
Figure 1. Schematic Diagram
AN_SYR827/SYR828 Rev.0.1
Figure2. Efficiency
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AN_SYR827/SYR828
Pinout (top view)
Part Number
SYR827PKC
SYR828PKC
Package type
CSP1.56*1.96-20
CSP1.56*1.96-20
Top Mark①
Ab xyz
Bc xyz
①
Note① : x=year code, y=week code, z= lot number code.
Pin
Pin Name
Pin Description
D1,D2,E1,E2
VIN
D3,D4,E3,E4
B2,B3,C1,C2,C3,C4
A1
SW
GND
VSEL
A2
B1
B4
A3
A4
EN
SDA
AGND
SCL
VOUT
Power input pin. These pins must be decoupled to ground with at least
22uF ceramic capacitor. The input capacitor should be placed as close as
possible between VIN and GND pins.
Switching node pin. Connect these pins to the switching node of inductor.
Power ground pins.
Voltage select pin. When this pin is low, VOUT is set by the VSEL0 register.
When this pin is high, VOUT is set by the VSEL1 register.
Enable control pin. Active high. Do not leave it floating.
I2C interface Bi-directional Data line.
Analog ground pin.
I2C interface clock line.
Sense pin for output. Connect to the output capacitor side.
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AN_SYR827/SYR828
Absolute Maximum Ratings (Note 1)
VIN--------------------------------------------------------------------------------------------------------------------------- 6.0V
All Other Pins-------------------------------------------------------------------------------------------------------- VIN + 0.6V
Power Dissipation, PD @ TA = 25°C CSP1.56*1.96-20-------------------------------------------------------------- 2.6W
Package Thermal Resistance (Note 2)
θ JA ------------------------------------------------------------------------------------------------------------38°C/W
θ JC ------------------------------------------------------------------------------------------------------------- 8°C/W
Junction Temperature Range ------------------------------------------------------------------------------------------ 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
Storage Temperature Range --------------------------------------------------------------------------------- -65°C to 150°C
Recommended Operating Conditions (Note 3)
Supply Input Voltage -------------------------------------------------------------------------------------------- 2.6V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------- -40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------------- -40°C to 85°C
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AN_SYR827/SYR828
Electrical Characteristics
(VIN = 5V, VOUT = 1.0V, L = 0.25uH, COUT = 22uF, TA = 25°C, unless otherwise specified)
Parameter
Input Voltage Range
VIN UVLO
VIN UVLO Hysteresis
Quiescent Current
Shutdown Current
EN, VSEL, SDA, SCL
Rising threshold
Falling threshold
VOUT Accuracy
NFET RDS(ON)
PFET RDS(ON)
PMOS peak current limit
NMOS peak current limit
Internal soft-start time
Min on time
Oscillator Frequency
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
LX node discharge resistor
Input OVP shutdown
Over voltage protection
blanking time
Symbol
VIN
VUVLO
VUVHYST
IQ
ISHDN_H/W
ISHDN_S/W
Test Conditions
VIN Rising
Max
5.5
2.55
Unit
V
V
mV
µA
µA
1.1
Forced PWM, VOUT=VSEL0,
default value
RDS(ON)N
RDS(ON)P
ILIM_PEAK
-1.5
0.4
V
V
+1.5
%
17
28
300
40
2.4
150
15
150
6.15
5.85
mΩ
mΩ
A
A
us
ns
MHz
°C
°C
Ω
V
V
20
us
7.5
6
ILIM_VALLEY
tSS
FOSC
TSD
THYS
RDSH
VOVP
Typ
2.45
150
65
0.1
30
IOUT=0, EN=1, FB=105%*VREF
EN=0
EN=VIN, Buck_ENx=0
VIH
VIL
VREG
Min
2.6
Rising threshold
Falling threshold
TBlanking
5.5
Note 1: Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: θ JA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity
test board of JEDEC 51-3 thermal measurement standard.
Note 3: The device is not guaranteed to function outside its operating conditions.
AN_SYR827/SYR828Rev. 0.1
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AN_SYR827/SYR828
Enabling Function
The EN pin controls SYR827/SYR828 start up. EN pin low to high transition starts the power up sequence. If EN
pin is low, the DC/DC converter will be turned off.
SYR827/SYR828 allows software to enable of the regulator when EN is HIGH, via the BUCK_EN bits.
BUCK_EN0 and BUCK_EN1 are both initialized HIGH in the registers.
Hardware and Software Enable control table.
Pins
EN
VSEL
0
x
1
0
1
0
1
1
1
1
Bits
BUCK_EN0
x
0
1
x
x
BUCK_EN1
x
x
x
0
1
OUTPUT
OFF
OFF
ON
OFF
ON
Input Over Voltage Protection Function
When the VIN exceeds over voltage protection threshold, SYR827/SYR828 will stop switching to protect the
circuitry. An internal 20us blanking time helps to prevent the circuit from shutting down due to noise spikes.
I2C Interface
SYR827/SYR828 features an I2C interface that allow the HOST processor to control the output voltage achieve the
DVS function. The I2C interface supports clock speeds of up to 3.4MHz and uses standard I2C commands.
SYR827/SYR828 always operates as a slave device, and is addressed using a 7-bit slave address followed by an 8th
bit, which indicates whether the transaction is a read-operation or a write-operation. I2C address of the SYR827 is
set at the factory to 0x40h, the SYR828 is set to 0x41h..
START and STOP Conditions:
SYR827/SYR828 is controlled via an I2C compatible interface. The START condition is a HIGH to LOW transition
of the SDA line while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line while SCL
is HIGH. A STOP condition must be sent before each START condition. The I2C master always generates the
START and STOP conditions.
Data Validity:
The data on the SDA line must be stable during the HIGH period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
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AN_SYR827/SYR828
Acknowledge:
Each address and data transmission uses 9-clock pulses. The ninth pulse is the acknowledge bit (ACK). After the
——
START condition, the master sends 7-slave address bits and an R/ W bit during the next 8-clock pulses. During the
ninth clock pulse, the device that recognizes its own address holds the data line low to acknowledge. The
acknowledge bit is also used by both the master and the slave to acknowledge receipt of register addresses and data.
Data Transactions:
All transactions start with a control byte sent from the I2C master device. The control byte begins with a START
condition, followed by 7-bits of slave address (1000000x for the SYR827, 1000001x for the SYR828, this address
——
——
can be changed if necessary) followed by the 8th bit, R/ W bit. The R/ W bit is 0 for a write or 1 for a read. If any
slave devices on the I2C bus recognize their address, they will acknowledge by pulling the SDA line low for the last
clock cycle in the control byte. If no slaves exist at that address or are not ready to communicate, the data line will
be 1, indicating a Not Acknowledge condition. Once the control byte is sent, and SYR827/SYR828 acknowledges it,
the 2nd byte sent by the master must be a register address byte. The register address byte tells the SYR827/SYR828
which register the master will write or read. Once the SYR827/SYR828 receives a register address byte it responds
with an acknowledge.
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AN_SYR827/SYR828
Register Settings:
1. VSEL0 (0x00)
Register Name
VSEL0
Address
0x00
Field
Bit
R/W
Default
Description
Software buck enable. When EN pin is low, the
BUCK_EN0
7
R/W
1
regulator is off. When EN pin is high, BUCK_EN bit
takes precedent.
MODE0
6
R/W
0
0=Allow auto-PFM mode during light load.
1=Forced PWM mode
NSEL0
5:0
R/W
010111 (VOUT=1.0V)
000000 = 0.7125V
000001 = 0.7250V
000010 = 0.7375V
……
010111 = 1.0000V
……
111111 =1.5000V
2. VSEL1 (0x01)
Register Name
VSEL1
Address
0x01
Field
Bit
R/W
Default
Description
Software buck enable. When EN pin is low, the
BUCK_EN1
7
R/W
1
regulator is off. When EN pin is high, BUCK_EN bit
takes precedent.
MODE1
6
R/W
0
0=Allow auto-PFM mode during light load.
1=Forced PWM mode
NSEL1
5:0
R/W
010111 (VOUT=1.0V)
000000 = 0.7125V
000001 = 0.7250V
000010 = 0.7375V
……
010111 = 1.0000V
……
111111 =1.5000V
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AN_SYR827/SYR828
3. Control Register (0x02)
Register Name
Control Register
Address
0x02
Field
Output
Discharge
Slew Rate
Bit
R/W
Default
7
R/W
1
6:4
R/W
000=10mV/0.15us
Description
0 = discharge resistor is disabled.
1 = discharge resistor is enabled.
Set the slew rate for positive voltage transitions.
000 = 10mV/0.15us
001 = 10mV/0.3us
010 = 10mV/0.6us
011 = 10mV/1.2us
100 = 10mV/2.4us
101 = 10mV/4.8us
110 = 10mV/9.6us
111 = 10mV/19.2us
Reserved
3
R/W
0
Always reads back 0.
RESET
2
R/W
0
Setting to 1 resets all registers to default values.
Reserved
1:0
R/W
00
Always reads back 0.
4. ID1 Register (0x03)
Register Name
ID1 Register
Address
0x03
Field
Bit
R/W
Default
Description
VENDOR
7:5
R
100
IC vendor Silergy code.
Reserved
4
R
0
Always reads back 0.
DIE_ID
3:0
R
1000
IC option code
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AN_SYR827/SYR828
5. ID2 Register (0x04)
Register Name
ID2 Register
Address
0x04
Field
Bit
R/W
Default
Description
Reverved
7:4
R
0000
Always reads back 0.
DIE_REV
3:0
R
0001
IC mask revision code
6. PGOOD Register (0x05)
Register Name
PGOOD Register
Address
0x05
Field
Bit
R/W
Default
Description
PGOOD
7
R
0
1: Buck is enabled and soft-start is completed.
Reserved
6:0
R
000 0000
Always reads back 0.
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AN_SYR827/SYR828
Typical Performance Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
90
95
85
90
80
85
75
80
70
VIN=3.3V,VOUT=0.7125V
VIN=4.2V,VOUT=0.7125V
VIN=5.0V,VOUT=0.7125V
65
60
10
100
1000
VIN=3.3V,VOUT=1.0V
VIN=4.2V,VOUT=1.0V
VIN=5.0V,VOUT=1.0V
75
10000
70
10
100
Load Current (mA)
1000
10000
Load Current (mA)
Load Transient
Efficiency vs. Load Current
(VIN=5.0V, VOUT=1.0V, IO=0.6 ~ 6.0A)
100
∆VOUT
95
100mV/div
90
85
IL
80
5A/div
VIN=3.3V,VOUT=1.5V
VIN=4.2V,VOUT=1.5V
VIN=5.0V,VOUT=1.5V
75
70
10
100
1000
10000
Time (200µs/div)
Load Current (mA)
Startup from Enable
Shutdown from Enable
(VIN=5.0V, VOUT=1.0V, IO=6.0A)
(VIN=5.0V, VOUT=1.0V, IO=6.0A)
EN
5V/div
VOUT
1V/div
VLX
5V/div
EN
5V/div
VOUT
1V/div
VLX
5V/div
IL
IL
5A/div
5A/div
Time (400µs/div)
AN_SYR827/SYR828Rev. 0.1
Time (100µs/div)
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AN_SYR827/SYR828
Short Circuit Protection
Short Circuit Protection
(VIN=5.0V, VOUT=1.0V, IO=0A ~ short)
(VIN=5.0V, VOUT=1.0V, IO=6A ~ short)
VOUT
IL
1V/div
VOUT
5A/div
IL
Time (2ms/div)
Dynamic Voltage Switch
Dynamic Voltage Switch
0.5V/div
(VIN=5.0V,0A Load,VOUT=0.7125~1.5V,Slew Rate=10mV/19.2µs)
VOUT
IL
IL
5A/div
Time (2ms/div)
(VIN=5.0V,0A Load,VOUT=0.7125~1.5V,Slew Rate=10mV/0.15µs)
VOUT
1V/div
0.5V/div
1A/div
1A/div
Time (10µs/div)
Time (400µs/div)
Dynamic Voltage Switch
(VIN=5.0V,6A Load,VOUT=0.7125~1.5V,Slew Rate=10mV/0.15µs)
VOUT
0.5V/div
IL
5A/div
Time (10µs/div)
AN_SYR827/SYR828Rev. 0.1
Dynamic Voltage Switch
(VIN=5.0V,6A Load,VOUT=0.7125~1.5V,Slew Rate=10mV/19.2µs)
VOUT
0.5V/div
IL
5A/div
Time (800µs/div)
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AN_SYR827/SYR828
Output Ripple
(VIN=5.0V, VOUT=1.0V, IO=6.0A)
∆VOUT
50mV/div
VLX
2V/div
IL
5A/div
Time (400ns/div)
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AN_SYR827/SYR828
Operation
SYR827/SYR828 is a high efficiency 2.4MHz
synchronous step down DC/DC regulator IC capable
of delivering up to 6A output currents. It can operate
over a wide input voltage range from 2.6V to 5.5V
and integrate main switch and synchronous switch
with very low RDS (ON) to minimize the conduction
loss. The output voltage can be programmed from
0.7125V to 1.5V through I2C interface.
Applications Information
Because of the high integration in SYR827/SYR828,
the application circuit based on this regulator IC is
rather simple. Only input capacitor CIN, output
capacitor COUT, inductor L need to be selected for the
targeted applications.
Input capacitor CIN
This ripple current through input capacitor is
calculated as:
I C IN _R M S = I O U T ×
D (1-D ) (A)
This formula has a maximum at VIN=2×VOUT
condition, where ICIN_RMS=IOUT/2.
With the maximum load current at 6A, a typical X5R
or better grade ceramic capacitor with 6.3V rating
and greater than 22uF capacitance can handle this
ripple current well. To minimize the potential noise
problem, place this ceramic capacitor really close to
the VIN and GND pins. Care should be taken to
minimize the loop area formed by CIN, and VIN/GND
pins.
Output capacitor COUT
Both steady state ripple and transient requirements
must be taken into account when selecting this
capacitor. For the best performance, it is
recommended to use X5R or better grade ceramic
capacitor with 6.3V rating and more than one 22µF
capacitor.
Output inductor L:
There are several considerations in choosing this
inductor.
1) Choose the inductance to provide the desired
ripple current. It is suggested to choose the ripple
current to be about 40% of the maximum
AN_SYR827/SYR828Rev. 0.1
average input
calculated as:
L=
current.
The inductance is
VOUT (1 − VOUT /VIN_MAX )
FSW × IOUT_MAX × 40%
(H)
where FSW is the switching frequency and
is the maximum load current.
IOUT_MAX
SYR827/SYR828 is less sensitive to the ripple
current variations. Consequently, the final choice of
inductance can be slightly off the calculation value
without significantly impacting the performance.
2) The saturation current rating of an inductor must
be selected to guarantee an adequate margin to
the peak inductor current under full load
conditions.
VOUT(1-VOUT/VIN,MAX)
ISAT, MIN > IOUT, MAX +
2 ⋅ FSW ⋅ L
3) The DCR of the inductor and the core loss at the
switching frequency must be low enough to
achieve the desired efficiency requirement. It is
desirable to choose an inductor with
DCR