GD25Q256DYIGR

3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D DATASHEET 1 GD25Q256D 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Contents 1. FEATURES .................................................................................................................................................. 4 2. GENERAL DESCRIPTION .......................................................................................................................... 5 3. MEMORY ORGANIZATION ......................................................................................................................... 8 4. DEVICE OPERATION .................................................................................................................................. 9 5. DATA PROTECTION ................................................................................................................................. 11 6. STATUS AND EXTENDED ADDRESS REGISTERS ................................................................................ 12 7. 6.1. STATUS REGISTERS .............................................................................................................................. 12 6.2. EXTENDED ADDRESS REGISTER ............................................................................................................ 16 COMMANDS DESCRIPTION .................................................................................................................... 17 7.1. W RITE ENABLE (WREN) (06H) ............................................................................................................. 22 7.2. W RITE DISABLE (WRDI) (04H) .............................................................................................................. 22 7.3. W RITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ........................................................................ 23 7.4. READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) ...................................................................... 23 7.5. W RITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H) .................................................................... 24 7.6. READ EXTENDED REGISTER (C8H) ........................................................................................................ 25 7.7. W RITE EXTENDED REGISTER (C5H) ...................................................................................................... 25 7.8. READ DATA BYTES (READ 03H OR 4READ 13H) ................................................................................. 26 7.9. READ DATA BYTES AT HIGHER SPEED (FAST READ 0BH OR 4FAST READ 0CH) ...................................... 27 7.10. DUAL OUTPUT FAST READ (DOFR 3BH OR 4DOFR 3CH) ..................................................................... 28 7.11. QUAD OUTPUT FAST READ (QOFR 6BH OR 4QOFR 6CH) .................................................................... 30 7.12. DUAL I/O FAST READ (DIOFR BBH OR 4DIOFR BCH) .......................................................................... 32 7.13. QUAD I/O FAST READ (QIOFR EBH OR 4QIOFR ECH)......................................................................... 36 7.14. SET BURST WITH W RAP (77H) .............................................................................................................. 38 7.15. PAGE PROGRAM (PP 02H OR 4PP 12H) ............................................................................................... 39 7.16. QUAD PAGE PROGRAM (QPP 32H OR 4QPP 34H) ................................................................................ 41 7.17. SECTOR ERASE (SE 20H OR 4SE 21H)................................................................................................. 44 7.18. 32KB BLOCK ERASE (BE32 52H OR 4BE32 5CH) ................................................................................ 45 7.19. 64KB BLOCK ERASE (BE64 D8H OR 4BE64 DCH) ............................................................................... 46 7.20. CHIP ERASE (CE) (60/C7H) .................................................................................................................. 47 7.21. DEEP POWER-DOWN (DP) (B9H) .......................................................................................................... 47 7.22. READ UNIQUE ID (4BH) ........................................................................................................................ 48 7.23. ENTER 4-BYTE ADDRESS MODE (B7H) .................................................................................................. 49 7.24. EXIT 4-BYTE ADDRESS MODE (E9H) ..................................................................................................... 49 7.25. CLEAR SR FLAGS (30H) ....................................................................................................................... 50 7.26. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ............................................... 50 7.27. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) .............................................................................. 51 7.28. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ............................................................................. 52 7.29. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H)............................................................................. 53 7.30. READ IDENTIFICATION (RDID) (9FH) ..................................................................................................... 54 2 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.31. PROGRAM/ERASE SUSPEND (PES) (75H) .............................................................................................. 55 7.32. PROGRAM/ERASE RESUME (PER) (7AH)............................................................................................... 56 7.33. ERASE SECURITY REGISTERS (44H) ...................................................................................................... 57 7.34. PROGRAM SECURITY REGISTERS (42H) ................................................................................................. 58 7.35. READ SECURITY REGISTERS (48H)........................................................................................................ 59 7.36. ENABLE RESET (66H) AND RESET (99H) ............................................................................................... 60 7.37. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH) ........................................................................ 60 8. ELECTRICAL CHARACTERISTICS ......................................................................................................... 70 8.1. POWER-ON TIMING .......................................................................................................................... 70 8.2. INITIAL DELIVERY STATE................................................................................................................. 70 8.3. ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 70 8.4. CAPACITANCE MEASUREMENT CONDITIONS .............................................................................. 71 8.5. DC CHARACTERISTICS .................................................................................................................... 72 8.6. AC CHARACTERISTICS .................................................................................................................... 75 9. ORDERING INFORMATION ...................................................................................................................... 82 9.1. 10. VALID PART NUMBERS .......................................................................................................................... 83 PACKAGE INFORMATION .................................................................................................................... 84 10.1. PACKAGE SOP16 300MIL .................................................................................................................... 84 10.2. PACKAGE WSON8 (8*6MM) .................................................................................................................. 85 10.3. PACKAGE TFBGA-24BALL (5*5 BALL ARRAY) ....................................................................................... 86 11. REVISION HISTORY.............................................................................................................................. 87 3 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 1. FEATURES ◆ 256M-bit Serial Flash ◆ - 256 Bytes per programmable page Fast Program/Erase Speed -Page Program time: 0.4ms typical -Sector Erase time: 70ms typical ◆ Standard, Dual, Quad SPI -Block Erase time: 0.16/0.22s typical - Standard SPI: SCLK, CS#, SI, SO,WP#, HOLD#/RESET# -Chip Erase time: 70s typical - Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/RESET# - Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 ◆ - 3 or 4-Byte Addressing Mode Flexible Architecture -Uniform Sectors of 4K-Byte -Uniform Blocks of 32/64K-Byte ◆ High Speed Clock Frequency -Maximum 104MHz for fast read on 3.0 - 3.6V power supply ◆ Low Power Consumption ◆ Dual I/O Data transfer up to 208Mbits/s - 1uA typical deep power down current ◆ Quad I/O Data transfer up to 416Mbits/s - 12uA typical standby current -Maximum 80MHz for fast read on 2.7 - 3.6V power supply ◆ Dual I/O Data transfer up to 160Mbits/s ◆ Quad I/O Data transfer up to 320Mbits/s ◆ Advanced Security Features -3*2048-Byte Security Registers With OTP Locks ◆ Software Write Protection -128-bit Unique ID -Write protect all/portion of memory via software -Serial Flash Discoverable parameters (SFDP) register -Top/Bottom Block protection ◆ ◆ Allows XIP(execute in place) Operation Single Power Supply Voltage -Full voltage range:2.7 - 3.6V -Continuous Read With 8/16/32/64-Byte Wrap ◆ ◆ Package Information Cycling Endurance and Data Retention -SOP16 (300mil) -Minimum 100,000 Program/Erase Cycles -WSON8 (8*6mm) -20-year data retention typical -TFBGA-24 (5*5 ball array) 4 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 2. GENERAL DESCRIPTION The GD25Q256D (256M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#) . The Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of 416Mbits/s. CONNECTION DIAGRAM Figure 1 Connection Diagram HOLD#/ RESET# (IO3) 1 16 SCLK VCC 2 15 SI (IO0) (1) 3 NC 4 RESET# 14 NC 13 NC Top View A2 Top View B1 B2 B3 B4 B5 NC SCLK VSS VCC NC C1 C2 C3 C4 C5 NC CS# NC WP# (IO2) NC D2 D3 12 NC NC 6 11 NC CS# 7 10 VSS D1 9 WP# (IO2) NC 16-LEAD SOP A5 (1) NC 5 8 A4 NC NC SO (IO1) A3 RESET# D4 HOLD#/ SO(IO1) SI(IO0) RESET# (IO3) NC D5 NC E1 E2 E3 E4 E5 NC NC NC NC NC 24-BALL TFBGA (5x5 ball array) CS# 1 8 SO (IO1) 2 HOLD#/ 7 RESET# (IO3) WP# (IO2) 3 Top View VCC 6 SCLK VSS 4 5 SI (IO0) 8–LEAD WSON Note: 1. Only for specific order, Pin 3 of 16-LEAD SOP package or Pin A4 of 24-BALL TFBGA (5x5 ball array) package is RESET# pin. Please contact GigaDevice for detail. 2. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. 5 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D PIN DESCRIPTION Table 1. Pin Description for SOP16 package Pin No. Pin Name I/O Description 1 HOLD#/RESET# (IO3) I/O Hold or Reset Input (Data Input Output 3) 2 VCC 7 CS# I 8 SO (IO1) I/O Data Output (Data Input Output 1) 9 WP# (IO2) I/O Write Protect Input (Data Input Output 2) 10 VSS 15 SI (IO0) I/O 16 SCLK I Power Supply Chip Select Input Ground Data Input (Data Input Output 0) Serial Clock Input Table 2 Pin Description for TFBGA24 5*5 package Pin No. Pin Name I/O Description B2 SCLK I B3 VSS Ground B4 VCC Power Supply C2 CS# I C4 WP# (IO2) I/O Write Protect Input (Data Input Output 2) D2 SO (IO1) I/O Data Output (Data Input Output 1) D3 SI (IO0) I/O Data Input (Data Input Output 0) D4 HOLD#/RESET# (IO3) I/O Hold or Reset Input (Data Input Output 3) Serial Clock Input Chip Select Input Table 3. Pin Description for WSON8 package Pin No. Pin Name I/O Description 1 CS# I 2 SO (IO1) I/O Data Output (Data Input Output 1) 3 WP# (IO2) I/O Write Protect Input (Data Input Output 2) 4 VSS 5 SI (IO0) I/O 6 SCLK I 7 HOLD#/RESET# (IO3) I/O 8 VCC Chip Select Input Ground Data Input (Data Input Output 0) Serial Clock Input Hold or Reset Input (Data Input Output 3) Power Supply 6 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D BLOCK DIAGRAM Figure 2 Block Diagram Write Control Logic Status Register HOLD#/ RESET# (IO3) SCLK SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Protect Logic and Row Decode WP#(IO2) Flash Memory CS# Column Decode And 256-Byte Page Buffer SI(IO0) SO(IO1) Byte Address Latch/Counter 7 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 3. MEMORY ORGANIZATION GD25Q256D Table 4. GD25Q256D Memory Organization Each device has Each block has Each sector has Each page has 32M 64/32K 4K 256 Bytes 128K 256/128 16 - pages 8192 16/8 - - sectors 512/1024 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE GD25Q256D Table 5. GD25Q256D 64K Bytes Block Sector Architecture Block 511 510 509 …… …… 2 1 0 Sector Address Range 8191 01FF F000H 01FF FFFFH …… …… …… 8176 01FF 0000H 01FF 0FFFH 8175 01FE F000H 01FE FFFFH …… …… …… 8160 01FE 0000H 01FE 0FFFH 8159 01FD F000H 01FD FFFFH …… …… …… 8144 01FD 0000H 01FD 0FFFH …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 0002 F000H 0002 FFFFH …… …… …… 32 0002 0000H 0002 0FFFH 31 0001 F000H 0001 FFFFH …… …… …… 16 0001 0000H 0001 0FFFH 15 0000 F000H 0000 FFFFH …… …… …… 0 0000 0000H 0000 0FFFH 8 3.3V Uniform Sector Dual and Quad Serial Flash 4. GD25Q256D DEVICE OPERATION SPI Mode Standard SPI The GD25Q256D features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25Q256D supports Dual SPI operation when using the “Dual Output Fast Read”, “Dual Output Fast Read with 4-Byte address”, “Dual I/O Fast Read” and “Dual I/O Fast Read with 4-Byte address” commands (3BH 3CH BBH and BCH). These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25Q256D supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad Output Fast Read with 4-Byte address”, “Quad I/O Fast Read”, “Quad I/O Fast Read with 4-Byte address” (6BH, 6CH, EBH and ECH) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD#/RESET# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set. Hold The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated data I/O pin. The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Figure 3 Hold Condition CS# SCLK HOLD# HOLD HOLD 9 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D RESET The RESET# pin allows the device to be reset by the control. The HOLD#/RESET#(IO3) pin can be configured as a RESET# pin depending on the status register setting, which need QE=0 and HOLD/RST=1. For Special Order of the SOP16 and TFBGA packages, a dedicated RESET# pin is provided and it is independent of QE bit setting. The RESET# pin goes low for a period of tRLRH or longer will reset the flash. After reset cycle, the flash is at the following states: -Standby mode -All the volatile bits will return to the default status as power on. Figure 4 RESET Condition CS# RESET# RESET 10 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 5. DATA PROTECTION The GD25Q256D provides the following data protection methods: ◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: -Power-Up/Software reset (66H+99H) -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) -Quad Page Program (QPP) -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) ◆ Software Protection Mode: -The Block Protect (BP3, BP2, BP1, and BP0) bits and Top Bottom (TB) bit define the section of the memory array that can be read but cannot be changed. ◆ Hardware Protection Mode: WP# goes low to protect the BP0~BP3 bits, TB bit and SRP bit. ◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command and software reset (66H+99H). Table 6. GD25Q256D Protected area size Status Register Content Memory Content TB BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X 0 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 511 01FF0000h-01FFFFFFh 64KB Upper 1/512 0 0 0 1 0 510 to 511 01FE0000h-01FFFFFFh 128KB Upper 1/256 0 0 0 1 1 508 to 511 01FC0000h-01FFFFFFh 256KB Upper 1/128 0 0 1 0 0 504 to 511 01F80000h-01FFFFFFh 512KB Upper 1/64 0 0 1 0 1 496 to 511 01F00000h-01FFFFFFh 1MB Upper 1/32 0 0 1 1 0 480 to 511 01E00000h-01FFFFFFh 2MB Upper 1/16 0 0 1 1 1 448 to 511 01C00000h-01FFFFFFh 4MB Upper 1/8 0 1 0 0 0 384 to 511 01800000h-01FFFFFFh 8MB Upper 1/4 0 1 0 0 1 256 to 511 01000000h-01FFFFFFh 16MB Upper 1/2 1 0 0 0 1 0 00000000h-0000FFFFh 64KB Lower 1/512 1 0 0 1 0 0 to 1 00000000h-0001FFFFh 128KB Lower 1/256 1 0 0 1 1 0 to 3 00000000h-0003FFFFh 256KB Lower 1/128 1 0 1 0 0 0 to 7 00000000h-0007FFFFh 512KB Lower 1/64 1 0 1 0 1 0 to 15 00000000h-000FFFFFh 1MB Lower 1/32 1 0 1 1 0 0 to 31 00000000h-001FFFFFh 2MB Lower 1/16 1 0 1 1 1 0 to 63 00000000h-003FFFFFh 4MB Lower 1/8 1 1 0 0 0 0 to 127 00000000h-007FFFFFh 8MB Lower 1/4 1 1 0 0 1 0 to 255 00000000h-00FFFFFFh 16MB Lower 1/2 X 1 1 0 X ALL 00000000h-01FFFFFFh 32MB ALL X 1 X 1 X ALL 00000000h-01FFFFFFh 32MB ALL 11 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 6. STATUS 6.1. Status Registers Table 7. Status Register-1 No. Bit Name Description Note S0 WIP Erase/Write In Progress Volatile, read only S1 WEL Write Enable Latch Volatile, read only S2 BP0 Block Protect Bits Non-volatile writable S3 BP1 Block Protect Bits Non-volatile writable S4 BP2 Block Protect Bits Non-volatile writable S5 BP3 Block Protect Bits Non-volatile writable S6 TB Top/Bottom Protect Bit Non-volatile writable S7 SRP0 Status Register Protection Bit Non-volatile writable Table 8. Status Register-2 No. Bit Name Description Note S8 ADS Current Address Mode Volatile, read only S9 QE Quad Enable Non-volatile writable S10 SUS2 Program Suspend Volatile, read only S11 LB1 Security Register Lock Bit Non-volatile writable (OTP) S12 LB2 Security Register Lock Bit Non-volatile writable (OTP) S13 LB3 Security Register Lock Bit Non-volatile writable (OTP) S14 SRP1 Status Register Protection Bit Non-volatile writable S15 SUS1 Erase Suspend Volatile, read only Table 9. Status Register-3 No. Bit Name Description Note S16 Reserved Reserved Reserved S17 Reserved Reserved Reserved S18 PE Program Error bit Volatile, read only S19 EE Erase Error bit Volatile, read only S20 ADP Power Up Address Mode Non-volatile writable S21 DRV0 Output Driver Strength Non-volatile writable S22 DRV1 Output Driver Strength Non-volatile writable S23 HOLD/RST HOLD# or Reset# Function Non-volatile writable The status and control bits of the Status Register are as follows: WIP bit The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. 12 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. TB bit The Top Bottom (TB) bit is non-volatile (OTP). The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, and BP0), starting from Top or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set to “1”, the protect area will change to Bottom area of the memory device. This bit is written with the Write Status Register (WRSR) command. BP3, BP2, BP1, BP0 bits The Block Protect (BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP3, BP2, BP1, and BP0) bits are set to 1, the relevant memory area becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed only if none sector or block is protected. SRP1, SRP0 bits The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of the write protection: software protected, hardware protected, hardware unprotected, power supply lock-down or one time programmable. Table 10. Status Register Protect (SRP) bit SRP1 SRP0 #WP Status Register 0 0 X Software Protected 0 1 0 Hardware Protected 0 1 1 Hardware Unprotected 1 0 X 1 1 X Power Supply LockDown(1)(2) One Time Program(2) Description The Status Register can be written to after a Write Enable command, WEL=1.(Default) WP#=0, the Status Register locked and cannot be written to. WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1 Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. NOTE: 1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available on special order. Please contact GigaDevice for details. QE bit The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (It is best to set the QE bit to 0 to avoid short issue if the WP# or HOLD# pin is tied directly to the power supply or ground.) 13 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D LB3, LB2, LB1 bits. The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once they are set to 1, the Security Registers will become read-only permanently. SUS1, SUS2 bit The SUS1 and SUS2 bit are read only bit in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH) command, software reset (66H+99H) command as well as a power-down, power-up cycle. DRV1, DRV0 bits The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations. Table 11. Driver Strength for Read Operations DRV1,DRV0 Driver Strength 00 100% 01 75% (Default) 10 Reserved 11 Reserved HOLD/RST bit The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#. However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are disabled, the pin acts as dedicated data I/O pin. Reserved bit It is recommended to set the value of the reserved bit as “0”. PE bit The Program Error (PE) bit is a read only bit that indicates a program failure. It will also be set when the user attempts to program a protected array sector or access the locked OTP space. Error bits can be reset by CLEAR FLAG STATUS REGISTER command (30H). EE bit The Erase Error (EE) bit is a read only bit that indicates an erase failure. It will also be set when the user attempts to erase a protected array sector or access the locked OTP space. Error bits can be reset by CLEAR FLAG STATUS REGISTER command (30H). ADS bit The Address Status (ADS) bit is a read only bit that indicates the current address mode the device is operating in. The device is in 3-Byte address mode when ADS=0 (default), and in 4-Byte address mode when ADS=1. 14 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D ADP bit The Address Power-up (ADP) bit is a non-volatile writable bit that determines the initial address mode when the device is powered on or reset. This bit is only used during the power on or device reset initialization period. When ADP=0(factory default), the device will power up into 3-Byte address mode, the Extended Address Register must be used to access memory regions beyond 128Mb. When ADP=1, the device will power up into 4-Byte address mode directly. Power Up Device Initialization & Status Register Refresh (Non-Volatile Cells) 3-Byte Address Standard SPI Dual SPI Quad SPI ADP bit value Enable 4-Byte (B7H) Disable 4-Byte (E9H) 15 ADP = 1 4-Byte Address Standard SPI Dual SPI Quad SPI Software Reset (66H + 99H) Hardware Reset ADP = 0 3.3V Uniform Sector Dual and Quad Serial Flash 6.2. GD25Q256D Extended Address Register Table 12. Extended Address Register No. Name Description Note EA0 A24 Address bit Volatile writable EA1 Reserved Reserved Reserved EA2 Reserved Reserved Reserved EA3 Reserved Reserved Reserved EA4 Reserved Reserved Reserved EA5 Reserved Reserved Reserved EA6 Reserved Reserved Reserved EA7 Reserved Reserved Reserved The extended address register is only used when the address mode is 3-Byte mode, as to set the higher address. A24=1 indicates the upper 128Mb memory address, A24=0 indicates the lower 128Mb. EA1~EA7 are reserved. A24 bit The Extended Address Bit A24 is used only when the device is operating in the 3-Byte Address Mode (ADS=0), which is volatile writable by C5H command. The lower 128Mb memory array (00000000h – 00FFFFFFh) is selected when A24=0, and all instructions with 3-Byte addresses will be executed within that region. When A24=1, the upper 128Mb memory array (01000000h – 01FFFFFFh) will be selected. If the device powers up with ADP bit set to 1, or an “Enter 4-Byte Address Mode (B7H)” instruction is issued, the device will require 4-Byte address input for all address related instructions, and the Extended Address Bit A24 setting will be ignored. However, any instruction with 4-Byte address input will replace the Extended Address Bit A24 with new settings. Reserved bit It is recommended to set the value of the reserved bit as “0”. 16 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-Byte command code must be shifted in to the device, with most significant bit first on SI, and each bit being latched on the rising edges of SCLK. Every command sequence starts with a one-Byte command code. Depending on the command, this might be followed by address Bytes, or by data Bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to deselected status. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a Byte boundary, otherwise the command is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input Byte is not a full Byte, nothing will happen and WEL will not be reset. When the device is in 3-Byte address mode (ADS=0), please refer to command set in table13 & table14. When the device is in 4-Byte address mode (ADS=1), please refer to command set in table13 & table15. Extended Address Register setting is effective to achieve A31-A24, accompanying A23-A0 within the instruction, when commands listed in table14 are executed. Extended Address Register setting is ignored when A31-A24 are given in the instruction listed in table 15 and some specific instruction from table13 (13H, 0CH, 3CH, 6CH, BCH, ECH). Table 13. Commands (Standard/Dual/Quad SPI, 3-Byte & 4-Byte address mode) Command Name Add Byte 1 Mode Write Enable Write Disable Volatile SR Write Enable Read Status Register-1 Read Status Register-2 Read Status Register-3 Write Status Register-1 Write Status Register-1&2 Write Status Register-2 Write Status Register-3 Read Extended Addr. Register Write Extended Addr. Register 3&4 3&4 3&4 3&4 3&4 3&4 3&4 3&4 3&4 3&4 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes 06H 04H 50H 05H (S7-S0) (cont.) 35H (S15-S8) (cont.) 15H (S23-S16) 01H S7-S0 01H S7-S0 31H S15-S8 11H S23-S16 C8H (EA7-EA0) C5H EA7-EA0 S15-S8 3&4 3&4 17 3.3V Uniform Sector Dual and Quad Serial Flash Chip Erase Enable Reset Reset Program/Erase Suspend Program/Erase Resume Set Burst with Wrap (5) Release From Deep Power-Down Read Device ID Deep PowerDown Manufacturer/ Device ID Manufacturer/ Device ID by Dual I/O Manufacturer/ Device ID by Quad I/O Read Identification Enter 4-Byte Address Mode Exit 4-Byte Address Mode Read Data with 4-Byte Address Fast Read with 4-Byte Address Fast Read Dual Output with 4-Byte Address (1) Fast Read Quad Output with 4-Byte Address (3) Fast Read Dual I/O with 4-Byte Address (2) Fast Read Quad I/O with 4-Byte Address (4) Page Program with 4-Byte Address Quad Page 3&4 3&4 3&4 3&4 C7/60H 66H 99H 75H 3&4 7AH 3&4 77H 3&4 ABH 3&4 ABH 3&4 B9H 3&4 3&4 3&4 3&4 3&4 3&4 GD25Q256D dummy W7-W0 dummy dummy dummy (DID7DID0) (cont.) 90H 00H 00H 00H (MID7MID0) (DID7-DID0) (cont.) 92H A23-A8 A7-A0, M7-M0 (MID7-MID0) (DID7-DID0) 94H A23-A0, M7-M0 9FH (MID7MID0) (5) dummy (MID7-MID0) (DID7-DID0) (JDID15(JDID7JDID8) JDID0) (cont.) B7H E9H 3&4 13H A31-A24 A23-A16 A15-A8 A7-A0 (D7-D0) 3&4 0CH A31-A24 A23-A16 A15-A8 A7-A0 dummy (D7-D0) 3&4 3CH A31-A24 A23-A16 A15-A8 A7-A0 dummy (D7-D0) 3&4 6CH A31-A24 A23-A16 A15-A8 A7-A0 dummy (D7-D0) 3&4 BCH A31-A24 A23-A16 A15-A8 A7-A0 M7-M0 (D7-D0) 3&4 ECH A31-A24 A23-A16 A15-A8 A7-A0 M7-M0 dummy dummy D7-D0 3&4 12H A31-A24 A23-A16 A15-A8 A7-A0 D7-D0 Next Byte 3&4 34H A31-A24 A23-A16 A15-A8 A7-A0 D7-D0 18 3.3V Uniform Sector Dual and Quad Serial Flash Program with 4-Byte Address Sector Erase with 4-Byte Address Block Erase(32K) with 4-Byte Address Block Erase(64K) with 4-Byte Address Clear SR Flags Read Serial Flash Discoverable Parameter GD25Q256D 3&4 21H A31-A24 A23-A16 A15-A8 A7-A0 3&4 5CH A31-A24 A23-A16 A15-A8 A7-A0 3&4 DCH A31-A24 A23-A16 A15-A8 A7-A0 3&4 30H 3&4 5AH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (cont.) Table 14. Commands (Standard/Dual/Quad SPI, 3-Byte address) Command Name Add Mode Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes Read Data Fast Read Dual Output Fast Read (1) Dual I/O Fast Read (2) Quad Output Fast Read (3) Quad I/O Fast Read (4) Page Program Quad Page Program Sector Erase Block Erase(32K) Block Erase(64K) Read Unique ID Erase Security Registers (6) Program Security Registers (6) Read Security Registers (6) 3 3 03H 0BH A23-A16 A23-A16 A15-A8 A15-A8 A7-A0 A7-A0 (D7-D0) dummy (Next Byte) (D7-D0) (cont.) (cont.) 3 3BH A23-A16 A15-A8 A7-A0 dummy (D7-D0)(1) (cont.) 3 BBH A23-A8(2) A7-A0 M7-M0(2) (D7-D0)(1) 3 6BH A23-A16 A15-A8 A7-A0 3 EBH dummy (D7-D0)(3) 3 02H A23-A0 M7-M0(4) A23-A16 A15-A8 A7-A0 D7-D0 3 32H A23-A16 A15-A8 A7-A0 D7-D0 3 20H A23-A16 A15-A8 A7-A0 3 52H A23-A16 A15-A8 A7-A0 3 D8H A23-A16 A15-A8 A7-A0 3 4BH dummy dummy dummy 3 44H A23-A16 A15-A8 A7-A0 3 42H A23-A16 A15-A8 3 48H A23-A16 A15-A8 19 (cont.) dummy (D7-D0)(3) (cont.) (cont.) Next Byte dummy (UID7-UID0) A7-A0 D7-D0 D7-D0 A7-A0 dummy (D7-D0) 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Table 15. Commands (Standard/Dual/Quad SPI, 4-Byte address) Command Name Add Mode Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Bytes-7 n-Bytes Read Data Fast Read Dual Output Fast Read (1) Dual I/O Fast Read (2) Quad Output Fast Read (3) 4 4 03H 0BH A31-A24 A31-A24 A23-A16 A23-A16 A15-A8 A15-A8 A7-A0 A7-A0 (D7-D0) dummy (D7-D0) (cont.) (cont.) 4 3BH A31-A24 A23-A16 A15-A8 A7-A0 dummy (D7-D0)(1) (cont.) 4 BBH A31-A24 A23-A16 A15-A8 A7-A0 M7-M0(2) dummy (D7-D0)(1) 4 6BH A31-A24 A23-A16 A15-A8 A7-A0 dummy (D7-D0)(1) (cont.) M7-M0(4) dummy dummy (D7-D0)(3) A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 Quad I/O Fast Read (4) Page Program Quad Page Program Sector Erase Block Erase(32K) Block Erase(64K) Read Unique ID Erase Security Registers (6) Program Security Registers (6) Read Security Registers (6) 4 EBH 4 02H A31-A24 A23-A16 A15-A8 A7-A0 A31-A24 4 32H A31-A24 A23-A16 A15-A8 A7-A0 4 20H A31-A24 A23-A16 A15-A8 A7-A0 4 52H A31-A24 A23-A16 A15-A8 A7-A0 4 D8H A31-A24 A23-A16 A15-A8 A7-A0 4 4BH dummy dummy dummy dummy 4 44H A31-A24 A23-A16 A15-A8 A7-A0 4 42H A31-A24 A23-A16 A15-A8 4 48H A31-A24 A23-A16 A15-A8 (cont.) A7-A0 D7-D0 D7-D0 (cont.) A7-A0 dummy (D7-D0) (cont.) IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3,…..) 4. Quad Input Address IO1 = A21, A17, A13, A9, A5, A1, M5, M1 (cont.) (UID7-UID0) 1. Dual Output data A4, A0, M4, M0 (cont.) dummy NOTE: IO0 = A20, A16, A12, A8, D7-D0 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID 20 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3, …) 6. Security Registers Address Security Register1: A23-A16=00H, A15-A12=1H, A11=0b, A10-A0= Byte Address; Security Register2: A23-A16=00H, A15-A12=2H, A11=0b, A10-A0= Byte Address; Security Register3: A23-A16=00H, A15-A12=3H, A11=0b, A10-A0= Byte Address. Table of ID Definitions: GD25Q256D Operation Code MID7-MID0 ID15-ID8 ID7-ID0 9FH C8 40 19 90H C8 18 ABH 18 21 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Quad Page Program (QPP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR). The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes high. Figure 5. Write Enable Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command SI 06H High-Z SO 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit may be set to a 0 by issuing the Write Disable (WRDI) command to disable Page Program (PP), Quad Page Program (QPP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), that require WEL be set to 1 for execution. The WRDI command can be used by the user to protect memory areas against inadvertent writes that can possibly corrupt the contents of the memory. The WRDI command is ignored during an embedded operation while WIP bit =1. The WEL bit is reset by following condition: Write Disable command (WRDI), Power-up, and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high. Figure 6. Write Disable Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 Command 04H High-Z 22 6 7 3.3V Uniform Sector Dual and Quad Serial Flash 7.3. GD25Q256D Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command and any other commands can’t be inserted between them. Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. Figure 7. Write Enable for Volatile Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 Command(50H) SI SO High-Z 7.4. Read Status Register (RDSR) (05H or 35H or 15H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H” / “35H” / “15H”, the SO will output Status Register bits S7~S0 / S15-S8 / S23-S16. Figure 8. Read Status Register Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 Command 05H or 35H or 15H High-Z Register0/1/2 5 4 3 2 1 MSB Register0/1/2 0 7 MSB 23 6 5 4 3 2 1 0 7 3.3V Uniform Sector Dual and Quad Serial Flash 7.5. GD25Q256D Write Status Register (WRSR) (01H or 31H or 11H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S19, S18, S15, S10, S8, S1 and S0 of the Status Register. CS# must be driven high after the eighth of the data Byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (TB, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. The Write Status Register-1 (01h) command can also write the Status Register-1&2. To complete the Write Status Register-1&2 command, the CS# pin must be driven high after the sixteenth bit of data is clocked in. If CS# is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, and the Status Register-2 will not be affected. Figure 9. Write Status Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI SO 01H/31H/11H 9 10 11 12 13 14 15 Status Register in 7 MSB 6 5 4 3 High-Z 24 2 1 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.6. GD25Q256D Read Extended Register (C8H) Extended Register contains Address Bit A24. The Read Extended Register instruction is entered by driving CS# low and shifting the instruction code “C8H” into the SI pin on the rising edge of SCLK. The Extended Register bits are then shifted out on the SO pin at the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 10. When the device is in the 4-Byte Address Mode, the value of A24 Bit is ignored. Figure 10 Read Extended Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 Extended Addr. Register Out 6 5 4 3 2 1 Command SI C8H SO High-Z 0 MSB 7.7. 7 Extended Addr. Register Out 6 5 4 3 2 1 0 7 MSB Write Extended Register (C5H) The Write Extended Register command could be executed no matter the Write Enable Latch (WEL) bit is 0 or 1.The Write Extended Register instruction is entered by driving CS# low, sending the instruction code “C5H”, and then writing the Extended Register data Byte as illustrated in Figure 11. Upon power up or the execution of a Software/Hardware Reset, the Extended Register bit values will be cleared to 0. Figure 11 Write Extended Register Sequence Diagram CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 Extended Addr. Register In 6 5 4 3 2 1 MSB High-Z Command SI SO C5H 25 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.8. GD25Q256D Read Data Bytes (READ 03H or 4READ 13H) The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0), and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read Data Bytes Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command SI 24-bit address 03H 23 22 21 2 1 0 MSB High-Z SO 3 MSB 7 6 Data Out1 5 4 3 2 1 Data Out2 0 Figure 13. Read Data Bytes Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command SI 32-bit address 03H 31 30 29 2 1 0 MSB High-Z SO 3 MSB 7 6 5 Data Out1 4 3 2 1 Data Out2 0 Figure 14. Read Data with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command SI SO 13H High-Z 32-bit address 31 30 29 3 2 1 0 MSB MSB 26 7 6 5 Data Out1 4 3 2 1 Data Out2 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.9. Read Data Bytes at Higher Speed (Fast Read 0BH or 4Fast Read 0CH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-Byte address (A23-A0) and a dummy Byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fC, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Figure 15. Read Data Bytes at Higher Speed Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 0BH 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 SO 7 6 MSB Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Figure 16. Read Data Bytes at Higher Speed Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI 32-bit address 0BH 31 30 29 3 2 1 0 High-Z SO CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 7 MSB 27 Data Out1 6 5 4 3 2 1 Data Out2 0 7 6 5 MSB 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 17. Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI 32-bit address 0CH 31 30 29 3 2 1 0 High-Z SO CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 SO 7.10. Data Out1 5 4 3 2 7 6 MSB 1 0 Data Out2 7 6 5 MSB Dual Output Fast Read (DOFR 3BH or 4DOFR 3CH) The Dual Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure 18. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Figure 18. Dual Output Fast Read Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24-bit address 3BH 23 22 21 3 2 1 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks SI SO 6 4 2 0 6 4 2 0 6 Data Out1 Data Out2 7 5 3 1 7 5 3 1 MSB MSB 7 28 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 19. Dual Output Fast Read Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI 32-bit address 3BH 31 30 29 3 2 1 0 High-Z SO CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 Data Out1 Data Out2 7 5 3 1 7 5 3 1 7 MSB MSB SO Figure 20. Dual Output Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI 32-bit address 3CH 31 30 29 3 2 1 High-Z SO CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 Data Out1 Data Out2 7 5 3 1 7 5 3 1 7 MSB MSB 29 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.11. GD25Q256D Quad Output Fast Read (QOFR 6BH or 4QOFR 6CH) The Quad Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure21. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Figure 21. Quad Output Fast Read Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI(IO0) 24-bit address 6BH 23 22 21 SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z 3 2 1 CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Clocks SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 30 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 22. Quad Output Fast Read Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI(IO0) 32-bit address 6BH 31 30 29 SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z 3 2 1 CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Clocks SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 31 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 23.Fast Read Quad Output with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI(IO0) 32-bit address 6CH 31 30 29 SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) High-Z 3 2 1 0 CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Clocks 7.12. SI(IO0) 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 Dual I/O Fast Read (DIOFR BBH or 4DIOFR BCH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-Byte address (A23-0) and a “Continuous Read Mode” Byte 2-bit per clock by SI and SO, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure24. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-4) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in followed Figure25. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the command code, thus returning to normal operation. A Reset command can be used to reset (M5-4) before issuing normal command. 32 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure24. Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=0) CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 6 4 2 0 6 4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 Command SI(IO0) BBH SO(IO1) A23-16 A15-8 A7-0 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 Byte4 Figure 25. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=0) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 A23-16 A15-8 A7-0 M7-4 M3-0 CS# SCLK 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 33 Byte4 0 3 1 M7-4 M3-0 CS# SCLK 2 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 26.Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=1) CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 5 3 1 7 Command SI(IO0) BBH SO(IO1) 7 A31-24 4 2 0 6 5 3 1 7 A23-16 4 2 0 6 5 3 1 7 A15-8 4 2 0 5 3 1 A7-0 CS# SCLK 24 25 26 27 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 M7-4 M3-0 Byte1 Byte2 Byte3 Byte4 Figure 27. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0) ADS=1) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 6 4 2 0 6 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 5 3 1 7 7 A23-16 A31-24 A15-8 4 2 0 6 4 2 0 5 3 1 7 5 3 1 M7-4 M3-0 A7-0 CS# SCLK 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 34 Byte4 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 28. Dual I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4≠ (1, 0), ADS=0 or ADS=1) CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Command SI(IO0) BCH SO(IO1) 7 A31-24 A23-16 A15-8 A7-0 CS# SCLK 24 25 26 27 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 M7-4 M3-0 Byte1 Byte2 Byte3 Byte4 Figure 29. Dual I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4= (1, 0) ADS=0 or ADS=1) CS# SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 6 4 2 0 6 4 2 0 6 4 2 0 6 7 5 3 1 7 5 3 1 7 5 3 1 7 A23-16 A31-24 A15-8 4 2 0 6 4 2 0 5 3 1 7 5 3 1 M7-4 M3-0 A7-0 CS# SCLK 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte2 Byte3 35 Byte4 3.3V Uniform Sector Dual and Quad Serial Flash 7.13. GD25Q256D Quad I/O Fast Read (QIOFR EBH or 4QIOFR ECH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-Byte address (A23-0) and a “Continuous Read Mode” Byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the command code, thus returning to normal operation. A Reset command can be used to reset (M5-4) before issuing normal command. Figure 30. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK Command SI(IO0) EBH A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Figure 31. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=0) CS# 0 1 2 3 4 5 6 7 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A23-16 A15-8 A7-0 M7-0 36 8 9 10 11 12 13 14 15 Dummy Byte1 Byte2 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 32. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCLK Command 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 EBH SI(IO0) Dummy A31-24A23-16A15-8 A7-0 M7-0 Byte1 Byte2 Figure 33.Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A31-24 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Figure 34. Quad I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4≠ (1, 0), ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCLK Command 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SI(IO0) ECH A31-24A23-16A15-8 A7-0 M7-0 37 Dummy Byte1 Byte2 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 35.Quad I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4= (1, 0), ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 SCLK A31-24 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to EBH or ECH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following EBH or ECH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-Byte section of a 256-Byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-Byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-Byte) of data without issuing multiple read commands. The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section within a page. 7.14. Set Burst with Wrap (77H) The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” command to access a fixed length of 8/16/32/64-Byte section within a 256-Byte page, in standard SPI mode. The Set Burst with Wrap command sequence: CS# goes low  Send Set Burst with Wrap command  Send 24 dummy bits  Send 8 bits “Wrap bits”  CS# goes high. Table 16 Set Burst with Wrap configuration W6,W5 W4=0 W4=1 (default) Wrap Around Wrap Length Wrap Around Wrap Length 0, 0 Yes 8-Byte No N/A 0, 1 Yes 16-Byte No N/A 1, 0 Yes 32-Byte No N/A 1, 1 Yes 64-Byte No N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-Byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. 38 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 36. Set Burst with Wrap Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x x x x x x 4 x SO(IO1) x x x x x x 5 x WP#(IO2) x x x x x x 6 x HOLD#(IO3) x x x x x x x x SCLK Command SI(IO0) 77H W6-W4 7.15. Page Program (PP 02H or 4PP 12H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address Bytes and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low  sending Page Program command  3 or 4-Byte address on SI  at least 1 Byte data on SI  CS# goes high. If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) is not executed. 39 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 37. Page Program Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 24-bit address 23 22 21 3 2 Data Byte 1 1 0 7 MSB 6 5 4 3 2 1 0 2078 2079 6 2077 7 2076 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 MSB CS# 2075 02H 2074 SI 1 0 SCLK Data Byte 2 SI 7 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 2 Data Byte 256 1 0 MSB MSB 5 4 3 2 MSB Figure 38. Page Program Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command 32-bit address 31 30 29 3 2 Data Byte 1 1 0 7 5 4 3 2 1 0 2086 2087 6 2084 7 2085 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2081 MSB CS# 2080 MSB 6 2083 02H 2082 SI 1 0 SCLK Data Byte 2 SI 7 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 2 Data Byte 256 1 0 MSB MSB 5 4 3 2 MSB Figure 39. Page Program with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command 32-bit address 31 30 29 3 2 1 0 7 5 4 3 2 1 2086 2087 2084 2085 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2083 MSB CS# 2080 MSB 6 2082 12H Data Byte 1 2081 SI 1 0 SCLK Data Byte 2 SI 7 MSB 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 MSB 2 Data Byte 256 1 0 7 MSB 40 6 5 4 3 2 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.16. GD25Q256D Quad Page Program (QPP 32H or 4QPP 34H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address Bytes and at least one data Byte on IO pins. The command sequence is shown below. If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Quad Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Page Program command applied to a page which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) is not executed. Figure 40. Quad Page Program Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 24-bit address 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 538 539 540 541 542 543 32H 23 22 21 3 2 Byte1 Byte2 537 SI(IO0) 1 MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 536 CS# SCLK Byte11Byte12 Byte253 Byte256 SI(IO0) 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 0 4 0 4 0 4 0 4 0 4 0 41 4 0 4 0 4 0 4 0 4 0 4 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 41. Quad Page Program Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command SI(IO0) 32-bit address 32H 31 30 29 3 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 545 547 548 549 550 551 1 546 2 Byte1 Byte2 MSB 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 544 CS# SCLK Byte11 Byte12 Byte253 Byte256 SI(IO0) 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 0 4 0 4 0 4 0 4 0 4 0 42 4 0 4 0 4 0 4 0 4 0 4 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 42. Quad Page Program with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command SI(IO0) 32-bit address 34H 31 30 29 3 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 545 547 548 549 550 551 1 546 2 Byte1 Byte2 MSB 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 544 CS# SCLK Byte11Byte12 Byte253 Byte256 SI(IO0) 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 0 4 0 4 0 4 0 4 0 4 0 4 43 0 4 0 4 0 4 0 4 0 4 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.17. GD25Q256D Sector Erase (SE 20H or 4SE 21H) The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address Byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-Byte address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bit is not executed. Figure 43. Sector Erase Sequence Diagram (ADS=0) CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 29 30 31 24 Bits Address 20H 23 22 MSB 2 1 0 Figure 44. Sector Erase Sequence Diagram (ADS=1) CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 37 38 39 32 Bits Address 20H 31 30 MSB 2 1 0 Figure 45. Sector Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# SCLK SI 0 1 2 3 4 5 6 7 Command 21H 8 9 37 38 39 32 Bits Address 31 30 MSB 44 2 1 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.18. 32KB Block Erase (BE32 52H or 4BE32 5CH) The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-Byte address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bits is not executed. Figure 46. 32KB Block Erase Sequence Diagram (ADS=0) CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 29 30 31 24 Bits Address 52H 23 22 MSB 2 1 0 Figure 47.32KB Block Erase Sequence Diagram (ADS=1) CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 37 38 39 32 Bits Address 52H 31 30 MSB 2 1 0 Figure 48. 32KB Block Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# SCLK SI 0 1 2 3 4 5 6 7 Command 5CH 8 9 37 38 39 32 Bits Address 31 30 MSB 45 2 1 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.19. 64KB Block Erase (BE64 D8H or 4BE64 DCH) The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-Byte address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bits is not executed. Figure 49. 64KB Block Erase Sequence Diagram (ADS=0) CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 29 30 31 24 Bits Address D8H 23 22 MSB 2 1 0 Figure 50.64KB Block Erase Sequence Diagram (ADS=1) CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 37 38 39 32 Bits Address D8H 31 30 MSB 2 1 0 Figure 51. 64KB Block Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) CS# SCLK SI 0 1 2 3 4 5 6 7 Command DCH 8 9 37 38 39 32 Bits Address 31 30 MSB 46 2 1 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.20. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is ignored if one or more sectors/blocks are protected. Figure 52. Chip Erase Sequence Diagram CS# 0 SCLK 1 3 4 5 6 7 Command SI 7.21. 2 60H or C7H Deep Power-Down (DP) (B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command or software reset command. The Release from Deep Power-Down and Read Device ID (RDI) command releases the device from Deep Power-Down mode , also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device always in the Standby Mode after Power-Up. The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep PowerDown (DP) command is not executed. As soon as CS# is driven high, it requires a delay of t DP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 53. Deep Power-Down Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command tDP Stand-by mode Deep Power-down mode B9H 47 3.3V Uniform Sector Dual and Quad Serial Flash 7.22. GD25Q256D Read Unique ID (4BH) The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID command sequence in 3 Byte mode (ADS=0): CS# goes low  sending Read Unique ID command Dummy Byte1 Dummy Byte2 Dummy Byte3 Dummy Byte4128bit Unique ID Out CS# goes high. The Read Unique ID command sequence in 4 Byte mode (ADS=0): CS# goes low  sending Read Unique ID command Dummy Byte1 Dummy Byte2 Dummy Byte3 Dummy Byte4 Dummy Byte5128bit Unique ID Out CS# goes high. Figure 54. Read Unique ID Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI 4-Byte Dummy 4BH 7 6 5 3 2 1 0 High-Z SO CS# 40 41 42 43 44 45 46 47 SCLK SI SO 7 6 MSB Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB Figure 55. Read Unique ID Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 7 6 44 45 46 47 SCLK Command SI 5-Byte Dummy 4BH High-Z SO CS# 48 49 50 51 52 53 54 55 SCLK SI SO 7 6 MSB Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 48 5 3 2 1 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.23. GD25Q256D Enter 4-Byte Address Mode (B7H) The Enter 4-Byte Address Mode command enables accessing the address length of 32-bit for the memory area of higher density (larger than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit8 (ADS bit) of status register will be automatically set to “1” to indicate the 4-Byte address mode has been enabled. Once the 4-Byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit. The sequence of issuing EN4B instruction is: CS# goes low  sending Enter 4-Byte mode command CS# goes high. Figure 56. Enter 4-Byte Address Mode Sequence Diagram CS# SCLK 0 1 2 4 5 6 7 Command SI B7H High-Z SO 7.24. 3 Exit 4-Byte Address Mode (E9H) The Exit 4-Byte Address Mode command is executed to exit the 4-Byte address mode and return to the default 3-Byte address mode. After sending out the EX4B instruction, the bit8 (ADS bit) of status register will be cleared to “0” to indicate the exit of the 4-Byte address mode. Once exiting the 4-Byte address mode, the address length will return to 24-bit. The sequence of issuing EN4B instruction is: CS# goes low  sending Exit 4-Byte Address Mode command CS# goes high. Figure 57.Exit 4-Byte Address Mode Sequence Diagram CS# SCLK SI SO 0 1 2 3 4 5 Command E9H High-Z 49 6 7 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.25. Clear SR Flags (30H) The Clear Status Register Flags command resets bit S18 (Program Error bit) and S19 (Erase Error bit) from status register. It is not necessary to set the WEL bit before the Clear Status Register command is executed. The Clear SR command will be not accepted even when the device remains busy with WIP set to 1, as the device does remain busy when either error bit is set. The WEL bit will be unchanged after this command is executed. Figure 58.Clear Status Register Flags Sequence Diagram CS# 0 SCLK 1 2 3 5 6 7 Command SI 30H High-Z SO 7.26. 4 Release from Deep Power-Down and Read Device ID (RDI) (ABH) The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown below. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy Byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown below. The Device ID value is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 59. Release Power-Down Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 t RES1 Command ABH Deep Power-down mode 50 Stand-by mode 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 60. Release Power-Down/Read Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 SCLK Command SI SO t RES2 3 Dummy Bytes 23 22 ABH 2 1 0 MSB High-Z 7 6 Device ID 5 4 3 2 MSB 7.27. 1 0 Deep Power-down Mode Stand-by Mode Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown below. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 61. Read Manufacture ID/ Device ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 90H 23 22 21 3 2 High-Z SO CS# 24-bit address 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI SO 7 MSB 6 Manufacturer ID 5 4 3 2 1 Device ID 0 7 MSB 51 6 5 4 3 2 1 0 1 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.28. Read Manufacture ID/ Device ID Dual I/O (92H) The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O. The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 62. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 62. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 Command SI(IO0) 92H SO(IO1) A23-16 A15-8 A7-0 M7-0 CS# SCLK 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SI(IO0) 6 SO(IO1) 7 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID Device ID 4 2 0 6 4 2 0 6 5 3 1 7 5 3 1 7 MFR ID (Repeat) 52 Device ID (Repeat) 4 2 0 6 4 2 0 5 3 1 7 5 3 1 MFR ID (Repeat) Device ID (Repeat) 3.3V Uniform Sector Dual and Quad Serial Flash 7.29. GD25Q256D Read Manufacture ID/ Device ID Quad I/O (94H) The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 63. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 63. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 SCLK Command SI(IO0) 94H A23-16 A15-8 A7-0 M7-0 CS# 24 25 26 27 28 29 30 31 SCLK SI(IO0) 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 MFR ID DID MFR ID DID (Repeat)(Repeat)(Repeat)(Repeat) 53 Dummy MFR ID DID 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.30. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two Bytes of device identification. The device identification indicates the memory type in the first Byte, and the memory capacity of the device in the second Byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The Read Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure 64. Read Identification ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 SCLK SI 9FH Command SO Manufacturer ID 5 4 3 2 1 MSB CS# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI SO 7 MSB 6 5 4 3 2 1 Memory Type JDID15-JDID8 0 7 MSB 54 6 5 4 3 2 Capacity JDID7-JDID0 1 0 0 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.31. Program/Erase Suspend (PES) (75H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and Erase/Program Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command (02H/32H) are not allowed during Program suspend. The Write Status Register command (01H/31H/11H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation. Table 17. Commands Allowed During Program or Erase Suspend Allowed Allowed Command Name Code During During (Hex) Erase Program Comment Suspend Suspend Write Enable 06 Yes Read Status Register-1 05 Yes Yes Read Status Register-2 35 Yes Yes Read Status Register-3 15 Yes Yes C8 Yes Yes C5 Yes Yes Read 03 Yes Yes All array reads allowed in suspend. 4Read 13 Yes Yes All array reads allowed in suspend. Fast Read 0B Yes Yes All array reads allowed in suspend. 4Fast Read 0C Yes Yes All array reads allowed in suspend. Dual I/O Fast Read BB Yes Yes All array reads allowed in suspend. 4Dual I/O Fast Read BC Yes Yes All array reads allowed in suspend. Dual Output Fast Read 3B Yes Yes All array reads allowed in suspend. 4Dual Output Fast Read 3C Yes Yes All array reads allowed in suspend. Quad I/O Fast Read EB Yes Yes All array reads allowed in suspend. 4Quad I/O Fast Read EC Yes Yes All array reads allowed in suspend. Quad Output Fast Read 6B Yes Yes All array reads allowed in suspend. 6C Yes Yes All array reads allowed in suspend. Page Program 02 Yes Required for array program during erase suspend. 4Page Program 12 Yes Required for array program during erase suspend. Quad Page Program 32 Yes Required for array program during erase suspend. 4Quad Page Program 34 Yes Required for array program during erase suspend. Program/Erase Resume 7A Yes Required to resume from erase/program suspend. Read Extended Addr. Register Write Extended Addr. Register 4Quad Output Fast Read Required for program command within erase suspend. Needed to read WIP to determine end of suspend process. Needed to read suspend status to determine whether the operation is suspended or complete. Needed to read suspend status to determine whether the operation is suspended or complete. Extended Addr. Register may need to be changed during a suspend to reach a sector needed for read or program. Extended Addr. Register may need to be changed during a suspend to reach a sector needed for read or program. 55 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Enable Reset 66 Yes Yes Reset allowed anytime. Reset 99 Yes Yes Reset allowed anytime. The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. Figure 65. Program/Erase Suspend Sequence Diagram CS# 0 SCLK 1 2 3 4 5 6 7 tSUS Command SI 75H High-Z SO Accept read command 7.32. Program/Erase Resume (PER) (7AH) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. Figure 66. Program/Erase Resume Sequence Diagram CS# SCLK SI 0 1 2 3 4 5 6 7 Command 7AH SO Resume Erase/Program 56 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.33. Erase Security Registers (44H) The GD25Q256D provides three 2048-Byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command 3 or 4Byte address on SI  CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is t SE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored. Table 18. Security Registers Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11 0 0 0 Figure 67. Erase Security Registers command Sequence Diagram (ADS=0) CS# SCLK 0 1 2 3 4 5 6 7 8 Command SI 9 29 30 31 24 Bits Address 23 22 MSB 44H 2 1 0 Figure68.Erase Security Registers command Sequence Diagram (ADS=1) CS# SCLK 0 1 2 3 4 5 6 7 Command SI 44H 8 9 37 38 39 32 Bits Address 31 30 MSB 57 2 1 0 A10-0 Do not care Do not care Do not care 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 7.34. Program Security Registers (42H) The Program Security Registers command is similar to the Page Program command. Each security register contains four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Table 19. Security Registers Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11 0 0 0 A10-0 Byte Address Byte Address Byte Address Figure 69. Program Security Registers command Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 23 22 21 3 2 Data Byte 1 1 0 7 MSB 5 4 3 2 1 0 2078 2079 6 2076 7 2077 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2073 MSB 2072 CS# 6 2075 42H 2074 SI 24-bit address 1 0 SCLK Data Byte 2 SI 7 6 5 4 3 2 Data Byte 3 1 0 7 MSB 6 5 4 3 2 Data Byte 256 1 0 MSB 5 4 3 2 MSB Figure 70.Program Security Registers command Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Command 32 31 30 3 2 1 0 7 5 4 3 2 1 2086 2087 2084 2085 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2083 CS# 6 MSB 2080 MSB 2082 42H Data Byte 1 2081 SI 32-bit address 1 0 SCLK Data Byte 2 SI 7 6 MSB 5 4 3 2 Data Byte 3 1 0 7 6 5 4 MSB 3 2 Data Byte 256 1 0 7 MSB 58 6 5 4 3 2 0 3.3V Uniform Sector Dual and Quad Serial Flash 7.35. GD25Q256D Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command i is followed by a 3-Byte address (A23-A0) or 4-Byte address (A31-A0) and a dummy Byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency f C, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Once the A10-A0 address reaches the last Byte of the register (Byte 7FFH), it will reset to 000H, the command is completed by driving CS# high. Table 20. Security Registers Address Security Register #1 Security Register #2 Security Register #3 A23-16 00H 00H 00H A15-12 0001 0010 0011 A11 0 0 0 A10-0 Byte Address Byte Address Byte Address Figure 71. Read Security Registers command Sequence Diagram (ADS=0) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 48H 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 SO Data Out1 5 4 3 2 7 6 MSB 1 0 Data Out2 7 6 5 MSB Figure 72. Read Security Registers command Sequence Diagram (ADS=1) CS# 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 SCLK Command SI 32-bit address 48H 31 30 29 3 2 1 0 High-Z SO CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 7 6 MSB 59 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 3.3V Uniform Sector Dual and Quad Serial Flash 7.36. GD25Q256D Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure 73. Enable Reset and Reset command Sequence Diagram CS# 0 SCLK 1 SI 2 3 4 5 6 7 0 1 2 3 4 5 Command Command 66H 99H 6 7 High-Z SO 7.37. Read Serial Flash Discoverable Parameter (5AH) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216B. Figure 74. Read Serial Flash Discoverable Parameter command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24-bit address 5AH 23 22 21 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI SO 7 6 5 4 3 2 1 0 7 6 MSB 60 Data Out1 5 4 3 2 1 0 Data Out2 7 6 5 MSB 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Table 21. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed:50444653H Add(H) DW Add Data Data (Byte) (Bit) 00H 07:00 53H 53H 01H 15:08 46H 46H 02H 23:16 44H 44H 03H 31:24 50H 50H SFDP Minor Revision Number Start from 00H 04H 07:00 06H 06H SFDP Major Revision Number Start from 01H 05H 15:08 01H 01H Number of Parameters Headers Start from 00H 06H 23:16 02H 02H Unused Contains 0xFFH and can never be 07H 31:24 FFH FFH 08H 07:00 00H 00H Start from 0x00H 09H 15:08 06H 06H Start from 0x01H 0AH 23:16 01H 01H Parameter Table Length How many DWORDs in the 0BH 31:24 10H 10H (in double word) Parameter table Parameter Table Pointer (PTP) First address of JEDEC Flash 0CH 07:00 30H 30H Parameter table 0DH 15:08 00H 00H 0EH 23:16 00H 00H 0FH 31:24 FFH FFH 10H 07:00 C8H C8H changed ID number (JEDEC) 00H: It indicates a JEDEC specified header Parameter Table Minor Revision Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed ID Number It is indicates GigaDevice (GigaDevice Manufacturer ID) manufacturer ID Parameter Table Minor Revision Start from 0x00H 11H 15:08 00H 00H Start from 0x01H 12H 23:16 01H 01H Parameter Table Length How many DWORDs in the 13H 31:24 03H 03H (in double word) Parameter table Parameter Table Pointer (PTP) First address of GigaDevice Flash 14H 07:00 90H 90H Parameter table 15H 15:08 00H 00H 16H 23:16 00H 00H 17H 31:24 FFH FFH 18H 07:00 84H 84H 19H 15:08 00H 00H Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed ID Number 4-Byte address instruction (4-Byte Address Instruction) parameter ID Parameter Table Minor Revision Start from 0x00H Number 61 3.3V Uniform Sector Dual and Quad Serial Flash Parameter Table Major Revision GD25Q256D Start from 0x01H 1AH 23:16 01H 01H Parameter Table Length How many DWORDs in the 1BH 31:24 02H 02H (in double word) Parameter table Parameter Table Pointer (PTP) First address of GigaDevice Flash 1CH 07:00 C0H C0H Parameter table 1DH 15:08 00H 00H 1EH 23:16 00H 00H 1FH 31:24 FFH FFH Number Unused Contains 0xFFH and can never be changed 62 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Table 22. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) Data Data 00: Reserved; 01: 4KB erase; Block/Sector Erase Size 10: Reserved; 01:00 01b 02 1b 03 0b 11: not support 4KB erase Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction 0: Nonvolatile status bit Requested for Writing to Volatile 1: Volatile status bit Status Registers (BP status register bit) 30H E5H 0: Use 50H Opcode, Write Enable Opcode Select for 1: Use 06H Opcode, Writing to Volatile Status Note: If target flash status register is Registers Nonvolatile, then bits 3 and 4 must 04 0b 07:05 111b 15:08 20H 16 1b 18:17 01b 19 0b be set to 00b. Unused Contains 111b and can never be changed 4KB Erase Opcode 31H (1-1-2) Fast Read 0=Not support, 1=Support Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte, addressing flash array 10: 4Byte only, 11: Reserved Double Transfer Rate (DTR) clocking 0=Not support, 1=Support 32H F3H (1-2-2) Fast Read 0=Not support, 1=Support 20 1b (1-4-4) Fast Read 0=Not support, 1=Support 21 1b (1-1-4) Fast Read 0=Not support, 1=Support 22 1b 23 1b 33H 31:24 FFH 37H:34H 31:00 Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-4-4) Fast Read Number of Mode Bits 39H (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support Mode Bits 00100b 44H 07:05 010b 15:08 EBH 20:16 01000b 3AH 000b:Mode Bits not support (1-1-4) Fast Read Opcode 3BH 63 FFH 0FFFFFFFH 38H (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of 04:00 000b:Mode Bits not support 20H EBH 08H 23:21 000b 31:24 6BH 6BH 3.3V Uniform Sector Dual and Quad Serial Flash Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of Mode Bits (Byte) (Bit) 04:00 3DH 0 0000b: Wait states (Dummy of Wait states Clocks) not support 000b: Mode Bits not support 3FH 0=not support Data 1=support Unused 08H 07:05 000b 15:08 3BH 20:16 00010b 0=not support 1=support Unused 3BH 42H 23:21 010b 31:24 BBH 00 0b 03:01 111b 04 0b 07:05 111b 40H (4-4-4) Fast Read Data 01000b 3EH (1-2-2) Fast Read Opcode (2-2-2) Fast Read DW Add 000b: Mode Bits not support (1-2-2) Fast Read Number of Mode Bits Add(H) 3CH (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number GD25Q256D BBH EEH Unused 43H:41H 31:08 0xFFH 0xFFH Unused 45H:44H 15:00 0xFFH 0xFFH 20:16 00000b (2-2-2) Fast Read Number 0 0000b: Wait states (Dummy of Wait states Clocks) not support (2-2-2) Fast Read Number of Mode Bits 46H 000b: Mode Bits not support (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of Mode Bits Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector Type 3 erase Opcode Sector Type 4 Size 000b 47H 31:24 FFH FFH 49H:48H 15:00 0xFFH 0xFFH 20:16 00000b 000b: Mode Bits not support Sector Type 1 erase Opcode Sector Type 2 Size 23:21 4AH (4-4-4) Fast Read Opcode Sector Type 1 Size 00H Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector Type 4 erase Opcode 64 00H 23:21 000b 4BH 31:24 FFH FFH 4CH 07:00 0CH 0CH 4DH 15:08 20H 20H 4EH 23:16 0FH 0FH 4FH 31:24 52H 52H 50H 07:00 10H 10H 51H 15:08 D8H D8H 52H 23:16 00H 00H 53H 31:24 FFH FFH 3.3V Uniform Sector Dual and Quad Serial Flash Description Comment GD25Q256D Add(H) DW Add (Byte) (Bit) Multiplier from typical erase time 3:0 to maximum erase time Erase Type 1 Erase, Typical time 42H 7:4 0100b 10:8 010b 15:11 01100b 17:16 01b 23:18 110010b 24 0b 31:25 1111111b 3:0 0010b Erase time=70ms/80ms C9H Erase time=300ms/304ms 57H Erase Type 4 Erase, Typical time Not exist Multiplier from typical time to max time for Page or Byte program FEH 58H Page Size Page size=256Byte Page Program Typical time Page program=600us/640us 82H 7:4 1000b 13:8 101001b 15:14 11b 18:16 100b 23:19 00010b 30:24 1011000b 31 0b 3:0 1100b 59H Byte Program Typical time, first Byte Byte Program Typical time, additional Byte Chip Erase, Typical time E9H First Byte program=30us/32us 5AH Additional Byte program=2.5us/3us Chip erase typical time=100s/100s 14H 5BH Reserved Prohibited Operations During Program Suspend Erase Suspend Reserved Interval Suspend in-progress program max latency Erase Resume to Suspend Interval Suspend in-progress erase max latency 58H 5CH Prohibited Operations During Program Resume to Suspend 62H Erase time=200ms/256ms 56H Erase Type 3 Erase, Typical time Data 0010b 54H 55H Erase Type 2 Erase, Typical time Data Interval=64us 5DH ECH 7:4 1110b 8 0b 12:9 0000b 15:13 011b 19:16 0110b 23:20 0000b 30:24 0110011b 60H max latency=20us/20us 5EH Interval=64us max latency=20us/20us 06H 5FH Suspend / Resume supported 33H 31 0b Program Resume Instruction 60H 7:0 7AH 7AH Program Suspend Instruction 61H 15:0 75H 75H Resume Instruction 62H 23:16 7AH 7AH Suspend Instruction 63H 31:24 75H 75H 65 3.3V Uniform Sector Dual and Quad Serial Flash Description Comment GD25Q256D Add(H) DW Add (Byte) (Bit) Reserved Data 1:0 00b 7:2 000001b 14:8 0111101b Data Use of legacy polling is supported Status Register Polling Device by reading the Status Register with Busy 05h instruction and checking WIP 64H 04H bit[0] (0=ready; 1=busy). Exit Deep Power down to next operation delay Delay=30us/30us 65H BDH 15 1b 22:16 1010101b 23 1b 30:24 1011100b 31 0b 3:0 0000b 7:4 000b 8 0b 9 1b Exit Deep Power down Instruction 66H Enter Deep Power down Instruction D5H 67H Deep Power down Supported 4-4-4 mode disable sequences Not support 4-4-4 mode 5CH 68H 4-4-4 mode enable sequences 00H Not support 4-4-4 mode 0-4-4 mode supported Supported 0-4-4 Mode Exit Method M=00H 15:10 000001b 0-4-4 Mode Entry Method M=AXH 19:16 0100b 22:20 100b 23 0b 31:24 00000000b 6:0 0001000b Quad Enable Requirements (QER) 69H QE is in status register 2, bit 1 6AH RESET Disable Reserved 6BH 06H 44H 00H Volatile or Non-Volatile Register and Write Enable Instruction for 6CH Status Register 1 Reserved Soft Reset and Rescue Sequence Support 66H-99H 08H 7 0b 13:8 010000b 6DH 50H 15:14 01b 6EH 23:16 00000000b 00H 6FH 31:24 00000001b 01H Exit 4-Byte Addressing Enter 4-Bye Addressing 66 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Table 23. Parameter Table (1): GigaDevice Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) 91H:90H 93H:92H Data Data 15:00 3600H 3600H 31:16 2700H 2700H 2000H=2.000V Vcc Supply Maximum Voltage 2700H=2.700V 3600H=3.600V 1650H=1.650V Vcc Supply Minimum Voltage 2250H=2.250V 2350H=2.350V 2700H=2.700V HW Reset# pin 0=not support 1=support 00 1b HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 1b SW Reset Opcode Should be issue Reset Enable(66H) before Reset cmd. 95H:94H 11:04 1001 1001b (99H) F99FH Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b 14 1b 15 1b 96H 23:16 77H 77H 97H 31:24 64H 64H 00 0b 01 0b 09:02 FFH 10 0b Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 08H:support 8B wrap-around read Wrap-Around Read data length 16H:8B&16B 32H:8B&16B&32B 64H:8B&16B&32B&64B Individual block lock Individual block lock bit (Volatile/Nonvolatile) 0=not support 0=Volatile 1=support 1=Nonvolatile Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect EBFCH 9BH:98H Secured OTP 0=not support 1=support 11 1b Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0/1b(2) Unused 15:14 11b Unused 31:16 FFFFH NOTE: 1. GD25Q256DxxSx support Permanent Lock. Please contact GigaDevice for details. 67 CBFC/ FFFFH 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Table 24. Parameter Table (2): 4-Byte Instruction Tables Description Comment Support for (1-1-1) READ command. 0 = NOT supported Instruction = 13H 1 = supported Support for (1-1-1) FAST READ 0 = NOT supported command. Instruction = 0CH 1 = supported Support for (1-1-2) FAST READ 0 = NOT supported command. Instruction = 3CH 1 = supported Support for (1-2-2) FAST READ 0 = NOT supported command. Instruction = BCH 1 = supported Support for (1-1-4) FAST READ 0 = NOT supported command. Instruction = 6CH 1 = supported Support for (1-4-4) FAST READ 0 = NOT supported command. Instruction = ECH 1 = supported Support for (1-1-1) Page Program 0 = NOT supported command. Instruction = 12H 1 = supported Support for (1-1-4) Page Program 0 = NOT supported command. Instruction = 34H 1 = supported Support for (1-4-4) Page Program 0 = NOT supported command. Instruction = 3EH 1 = supported Support for Erase Command – Type 1 size. Instruction lookup in next the dword Support for Erase Command – Type 2 size. Instruction lookup in next the dword Support for Erase Command – Type 3 size. Instruction lookup in next the dword Support for Erase Command – Type 4 size. Instruction lookup in next the dword Add(H) DW Add (Byte) (Bit) 1 = supported 0 = NOT supported 1 = supported 0 = NOT supported C1H 0 = NOT supported 1 = supported Support for (1-1-1) DTR READ 0 = NOT supported command. Instruction = 0EH 1 = supported Support for (1-2-2) DTR READ 0 = NOT supported command. Instruction = BEH 1 = supported Support for (1-4-4) DTR READ 0 = NOT supported command. Instruction = EEH 1 = supported 68 00 1b 01 1b 02 1b 03 1b C0H 0 = NOT supported 1 = supported Data Data FFH 04 1b 05 1b 06 1b 07 1b 08 0b 09 1b 10 1b 11 1b 12 0b 13 0b 14 0b 15 0b 0EH 3.3V Uniform Sector Dual and Quad Serial Flash Description Support for volatile individual sector lock Read command. Instruction = E0H Support for volatile individual sector lock Write command. Instruction = E1H Support for non-volatile individual sector lock Read command. Instruction = E2H Support for non-volatile individual sector lock Write command. Instruction = E3H Comment GD25Q256D Add(H) DW Add (Byte) (Bit) 0 = NOT supported 1 = supported 0 = NOT supported 1 = supported 0 = NOT supported Data 16 0b 17 0b C2H 1 = supported 0 = NOT supported 1 = supported Data F0H 18 0b 19 0b 23:20 1111b Reserved Reserved Reserved Reserved C3H 31:24 FFH FFH Instruction for Erase Type 1 FFH = NOT supported C4H 07:00 21H 21H Instruction for Erase Type 2 FFH = NOT supported C5H 15:08 5CH 5CH Instruction for Erase Type 3 FFH = NOT supported C6H 23:16 DCH DCH Instruction for Erase Type 4 FFH = NOT supported C7H 31:24 FFH FFH 69 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Figure 75.Power-on Timing Vcc(max) Chip Selection is not allowed Vcc(min) tVSL Device is fully accessible VWI Time Table 25. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min tVSL VCC (min) To CS# Low 2.5 VWI Write Inhibit Voltage 1.5 Max Unit ms 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each Byte contains FFH). The Status Register bits are set to 0, except DRV0 bit (S21) is set to 1. 8.3. ABSOLUTE MAXIMUM RATINGS Table 26. Absolute Maximum Ratings Parameter Value Unit -40 to 85 Ambient Operating Temperature -40 to 105 ℃ -40 to 125 ℃ Storage Temperature -65 to 150 Applied Input/Output Voltage -0.6 to VCC+0.4 V -2.0 to VCC+2.0 V -0.6 to 4.2 V Transient Input/Output Voltage (note: overshoot) VCC 70 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D Figure 76. Input Test Waveform and Measurement Level Maximum Negative Overshoot Waveform 20ns Maximum Positive Overshoot Waveform 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns 8.4. CAPACITANCE MEASUREMENT CONDITIONS Table 27. Capacitance Measurement Conditions Symbol Parameter Min Typ. Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 Input Rise And Fall time pF 5 ns Input Pulse Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Figure77. Input/Output Timing Reference Level Input timing reference level 0.8VCC 0.7VCC 0.1VCC 0.2VCC Output timing reference level AC Measurement Level Note: Input pulse rise and fall time are