SY8502FCC

Application Note: SY8502 High Efficiency, 1.2A Continuous, 1.8A Peak, 85V Input Synchronous Step Down Regulator General Description Features SY8502 develops high efficiency synchronous stepdown DC-DC converter capable of delivering 1.2A continuous, 1.8A peak current. The SY8502 operates over a wide input voltage range from 7V to 85V and integrate main switch and synchronous switch with very low RDS(ON) to minimize the conduction loss. • low RDS(ON) for internal switches (top/bottom): 500mΩ/240mΩ • 7-85V input voltage range • 1.2A continuous, 1.8A peak output current capability • Adjustable switching frequency • Instant PWM architecture to achieve fast transient responses. • Programmable Switching Frequency Range 200~500 kHz. • 2ms internal softstart limits the inrush current • Precious +/-2% 1.2V reference • RoHS Compliant and Halogen Free • Compact SO8E package The device adopts the instant PWM architecture to achieve fast transient responses for high step down applications. Ordering Information SY8502 □(□□)□ Tempera ture Code Packa ge Code Optiona l Spec Code Ordering Number SY8502FCC Package type SO8E Note -- Applications • Non-Isolated Telecommunication Buck Regulator • Secondary High Voltage Post Regulator • Automotive Systems Typical Applications Efficiency vs. Load Current 100 90 80 70 60 VIN=7V, VOUT=5V 50 VIN=24V, VOUT=5V VIN=48V, VOUT=5V 40 VIN=85V, VOUT=5V 30 0 0.5 1 1.5 Load Current (A) Figure 1. Schematic Diagram AN_SY8502 Rev. 0.9 Figure 2. Efficiency Silergy Corp. Confidential- Prepared for Customer Use Only 1 AN_SY8502 Pinout (top view) NC 1 IN 2 EN 3 RON 4 GND Exposed Pad 8 LX 7 BS 6 VCC 5 FB (SO8E) Top Mark: BDXxyz for SY8502FCC (Device code: BDX, x=year code, y=week code, z= lot number code) Pin Name NC IN EN Pin Number 1 2 3 RON 4 Pin Description Not connected. Input pin. Decouple this pin to GND with a low ESR ceramic cap. Enable control. The device has an accurate 1.2V rising threshold. This pin can also be used to program the Vin turn on voltage with resistor divider. Connect a resistor from this pin to IN to set the top switch ON time. The switching frequency can be calculated using following equation: Fs (kHz ) = FB 5 VCC BS 6 7 LX GND 8 Exposed Pad AN_SY8502 Rev. 0.9 11× VO (V ) + 500 Ron ( M Ω) Output Feedback Pin. Connect this pin to the center point of the output resistor divider (as shown in Figure 1) to program the output voltage: Vout=1.2*(1+R1/R2) Supply input of internal LDO. Boot-Strap Pin. Supply high side gate driver. Decouple this pin to LX pin with 0.1uF ceramic cap. Inductor pin. Connect this pin to the switching node of inductor Ground pin. Silergy Corp. Confidential- Prepared for Customer Use Only 2 AN_SY8502 Block Diagram Absolute Maximum Ratings (Note 1) Supply Input Voltage -------------------------------------------------------------------------------------------------------- 90V EN, LX----------------------------------------------------------------------------------------------------------------- VIN + 0.3V BS -------------------------------------------------------------------------------------------------------------------------- LX + 6V FB, RON Voltage -------------------------------------------------------------------------------------------------------------- 6V VCC ----------------------------------------------------------------------------------------------------------------------------- 30V Power Dissipation, PD @ TA = 25°C SO8E ----------------------------------------------------------------------------- 3.3W Package Thermal Resistance (Note 2) θ JA --------------------------------------------------------------------------------------------------------------- 30°C/W θ JC --------------------------------------------------------------------------------------------------------------- 10°C/W Junction Temperature Range ---------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------------- 260°C Storage Temperature Range ------------------------------------------------------------------------------------ -65°C to 150°C Recommended Operating Conditions (Note 3) Supply Input Voltage ------------------------------------------------------------------------------------------------- 7V to 85V Junction Temperature Range ------------------------------------------------------------------------------------ -40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------- -40°C to 85°C AN_SY8502 Rev. 0.9 Silergy Corp. Confidential- Prepared for Customer Use Only 3 AN_SY8502 Electrical Characteristics (VIN=48V, VOUT=5V, L=33uH, COUT=10uF, TA=25°C, IOUT=1.2A unless otherwise specified) Parameter Symbol Test Conditions Min Typ Quiescent Current IQ IOUT=0, VFB=VREF*105% Shutdown Current ISHDN EN=0 8 Feedback Reference VREF 1.176 1.2 Voltage FB Input Current IFB VFB=3.3V -50 Top FET RON RDS(ON)1 500 Bottom FET RON RDS(ON)2 240 Top FET peak Current ILIM,Top 3.2 Limit Bottom FET Valley ILIM,Bottom 1.6 Current Limit EN Rising Threshold VENH 1.2 EN Falling Threshold VENL 0.8 Input UVLO Rising VUVLO 5.8 6.3 Threshold Input UVLO Hysteresis VHYS 0.25 Switching Frequency FOSC VIN=48V, RON=1.6MΩ 340 Min ON Time 80 Min OFF Time 200 Thermal Shutdown TSD 150 Temperature Thermal Shutdown THYS 15 Hysteresis Max 400 11 1.224 Unit µA µA V 50 nA mΩ mΩ A A 6.8 V V V V kHz ns ns °C °C Note 1: Stresses beyond the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: θ JA is measured in the natural convection at TA = 25°C on a low effective 4-layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Paddle of SO8E packages is the case position for θ JC measurement. Note 3: The device is not guaranteed to function outside its operating conditions. AN_SY8502 Rev. 0.9 Silergy Corp. Confidential- Prepared for Customer Use Only 4 Typical Performance Characteristics Efficiency vs. Load Current Efficiency vs. Load Current 100 100 90 90 80 80 70 70 60 VIN=7V, VOUT=5V 50 VIN=18V, VOUT=12V 60 VIN=24V, VOUT=12V VIN=24V, VOUT=5V VIN=48V, VOUT=12V VIN=48V, VOUT=5V 40 50 VIN=85V, VOUT=12V VIN=85V, VOUT=5V 40 30 0 0.5 1 1.5 0 0.5 Load Current (A) Load Regulation 1.5 Load Regulation 12.232 5.036 VIN=7V, VOUT=5V VIN=24V, VOUT=5V VIN=48V, VOUT=5V VIN=85V, VOUT=5V 5.034 12.230 12.228 Output Voltage (V) 5.032 5.030 5.028 5.026 5.024 5.022 VIN=85V, VOUT=12V 12.226 12.224 VIN=48V, VOUT=12V 12.222 12.220 12.218 12.216 VIN=18V, VOUT=12V VIN=24V, VOUT=12V 12.214 5.020 12.212 0 0.5 1 1.5 0 0.5 Load Current (A) 1 1.5 Load Current (A) Line Regulation Line Regulation 12.240 5.036 IOUT=0A, VOUT=12V 5.034 IOUT=0.12A, VOUT=12V 12.235 Output Voltage (V) 1 Load Current (A) IOUT=1.20A, VOUT=12V 5.032 12.230 5.030 5.028 12.225 5.026 IOUT=0A, VOUT=5V IOUT=0.12A, VOUT=5V IOUT=1.20A, VOUT=5V 5.024 5.022 12.220 12.215 0 20 40 60 Input Voltage (V) 80 100 0 20 40 60 Input Voltage (V) 80 100 AN_SY8502 Output Ripple Output Ripple (VIN=24V, VOUT=5V, IO=1.2A) (VIN=48V, VOUT=5V, IO=1.2A) ∆VOUT 20mV/div ∆VOUT 20mV/div VLX 20V/div VLX 50V/div IL 1A/div Time (4µs/div) IL 1A/div Time (4µs/div) Output Ripple Output Ripple (VIN=24V, VOUT=12V, IO=1.2A) (VIN=48V, VOUT=12V, IO=1.2A) ∆VOUT 20mV/div VLX 20V/div IL 1A/div Time (2µs/div) AN_SY8502 Rev. 0.9 ∆VOUT 50mV/div VLX 50V/div IL 1A/div Time (2µs/div) Silergy Corp. Confidential- Prepared for Customer Use Only 6 AN_SY8502 Startup from VIN (VIN=24V, VOUT=5V, IO=1.2A) VIN VOUT 20V/div 5V/div VLX 20V/div IL 1A/div Time (4ms/div) Startup from VIN (VIN=48V, VOUT=5V, IO=1.2A) VIN VOUT 50V/div 5V/div VLX 50V/div IL 1A/div Time (4ms/div) AN_SY8502 Rev. 0.9 Silergy Corp. Confidential- Prepared for Customer Use Only 7 AN_SY8502 Startup from VIN (VIN=24V, VOUT=12V, IO=1.2A) VIN 20V/div VOUT 10V/div VLX 20V/div IL 1A/div Time (4ms/div) Startup from VIN (VIN=48V, VOUT=12V, IO=1.2A) VIN 50V/div VOUT 10V/div VLX 50V/div IL 1A/div Time (4ms/div) Startup from Enable (VIN=24V, VOUT=5V, IO=1.2A) VEN 5V/div VOUT 5V/div VLX 20V/div IL 1A/div Time (2ms/div) AN_SY8502 Rev. 0.9 Silergy Corp. Confidential- Prepared for Customer Use Only 8 AN_SY8502 Startup from Enable (VIN=48V, VOUT=5V, IO=1.2A) VEN 5V/div VOUT 5V/div VLX 20V/div IL 1A/div Time (2ms/div) Startup from Enable (VIN=24V, VOUT=12V, IO=1.2A) VEN 5V/div VOUT 10V/div VLX 20V/div IL 1A/div Time (2ms/div) Startup from Enable (VIN=24V, VOUT=12V, IO=1.2A) VEN 5V/div VOUT 10V/div VLX 20V/div IL 1A/div Time (2ms/div) AN_SY8502 Rev. 0.9 Silergy Corp. Confidential- Prepared for Customer Use Only 9 AN_SY8502 Startup from Enable (VIN=48V, VOUT=12V, IO=1.2A) VEN 5V/div VOUT 10V/div VLX 50V/div IL 1A/div Time (2ms/div) Short Circuit Protection Short Circuit Protection (VIN=48V, VOUT=5V, IO=0A~ Short) (VIN=48V, VOUT=5V, IO=1.2A~ Short) VOUT 5V/div VLX 50V/div IL VOUT 5V/div VLX 50V/div IL 1A/div 1A/div Time (800µs/div) Time (800µs/div) Short Circuit Protection Short Circuit Protection (VIN=48V, VOUT=12V, IO=0A~ Short) (VIN=48V, VOUT=12V, IO=1.2A~ Short) VOUT 10V/div VOUT 10V/div VLX 50V/div VLX 50V/div IL 1A/div IL 1A/div Time (2ms/div) AN_SY8502 Rev. 0.9 Time (2ms/div) Silergy Corp. Confidential- Prepared for Customer Use Only 10 AN_SY8502 Operation Description The SY8502 operates over a wide input voltage range from 7V to 85V and integrates main switch and synchronous switch with very low RDS(ON) to minimize the conduction loss. This regulator adopts the instant PWM architecture with an internal ripple control scheme using an on-time inversely proportional to VIN to achieve fast transient responses for high voltage step down applications. This architecture requires no loop compensation. In addition, it operates at pseudo-constant frequency under continuous conduction mode to minimize the size of inductor and capacitor. Applications Information Because of the high integration in the SY8502 IC, the application circuit based on this regulator IC is rather simple. Only on-timer resistor RON, feedback resistors (R1 and R2), input capacitor CIN, output capacitor COUT and output inductor L need to be selected for the targeted applications specifications. 1) Choose the inductance to provide the desired ripple current. It is suggested to choose the ripple current to be about 40% of the maximum output current. The inductance is calculated as: L2 = The SY8502 regulator IC is quite tolerant of different ripple current amplitude. Consequently, the final choice of inductance can be slightly off the calculation value without significantly impacting the performance. 2) The saturation current rating of the inductor must be selected greater than the peak inductor current under full load conditions. I SAT _ MIN > I OUT _ MAX + Choose R1and R2 to program the proper output voltage. To minimize the power consumption under light loads, it is desirable to choose large resistance values for both R1 and R2. Input Capacitor CIN:  Vout ICIN _ RMS = IOUT _ MAX × D (1 − D) The capacitance of input capacitor is calculated as: R1 I ×V × (VIN − VOUT ) C IN = OUT OUT ∆VIN × FS ×η × VIN 2 R2 ∆VIN is desired input voltage ripple GND Output Inductor L: There are several considerations in choosing this inductor. AN_SY8502 Rev. 0.9 FS × L2 × 2 The ripple current through input capacitor is calculated as： VFB is typical 1.2V. FB VOUT × (1 − VOUT / VIN _ MAX ) 3) The DCR of the inductor and the core loss at the switching frequency must be low enough to achieve the desired efficiency requirement. It is desirable to choose an inductor with smaller DCR to achieve a good overall efficiency. Output Voltage Program. Vout FS × I OUT _ MAX × 40% Where Fs is the switching frequency and IOUT_MAX is the maximum load current. This regulator is well suited for 48 Volt telecom and the new 42V automotive power bus ranges. R1 = (1 + ) × VFB R2 VOUT × (1 − VOUT / VIN _ MAX ) To minimize the potential noise problem, place a typical X5R or better grade ceramic capacitor really close to the IN and GND pins. Care should be taken to minimize the loop area formed by CIN, and IN/GND pins. In this case, a 1uF low ESR ceramic capacitor is recommended. Silergy Corp. Confidential- Prepared for Customer Use Only 11 AN_SY8502 Output Capacitor COUT: Soft Start The output capacitor is selected to handle the output ripple noise requirements. Both steady state ripple and transient requirements must be taken into consideration when selecting this capacitor. It is recommended to use X5R or better grade ceramic capacitor greater than 10uF capacitance. The SY8502 has a built-in soft-start to control the rise rate of the output voltage and limit the input current surge during IC start-up. The typical soft-start time is 2ms. Enable Operation The on-time for the SY8502 is determined by the RON resistor, and is inversely proportional to the input voltage, resulting in a nearly constant frequency as VIN is varied over its range. Pulling the EN pin low will shut down the device. During shut mode, the SY8502 shutdown current drops to lower than 10uA. Driving the EN pin high will turn on the IC again. Input UVLO can be programmed by EN rising threshold. Minimum VUVLO value need larger than 6.5V Frequency vs. Ron Resistor: R VUVLO (V ) = (1 + 4 ) × Vth R5 On Time Fs (kHz ) = 11× VO (V ) + 500 Ron ( M Ω) Vth is EN rising threshold voltage, typical is 1.2V Notice: Final switch frequency is not only effected by component tolerant but also minimum off and on time limit. Internal LDO Regulator The SY8502 consists of two internal LDOs for 4V_VDD from IN pin and VCC pin. Upon power up, the LDO regulator from IN sources current into the capacitor on internal 4V_VDD. When the voltage on the 4V_VDD reaches the under-voltage lockout threshold voltage, the buck switch is enabled. After soft start done and VCC pin voltage is larger than 4.2V, the VCC side LDO is enabled and IN side LDO is disabled. A 0.1uF ceramic capacitor is recommended for CVCC at most applications. Load Transient Considerations: The SY8502 regulator IC adopts the instant PWM architecture to achieve good stability and fast transient responses. Adding a Cff ceramic cap in parallel with R1 is recommended. In applications，the input pin (IN) can be connected directly to the line voltages up to 85 Volts, where power dissipation in the VCC regulator is a concern, an auxiliary voltage can be connected to the VCC pin via a diode. Setting the auxiliary voltage to 4.5 -28V will shut off the internal regulator from IN, reducing internal power dissipation. External Boot-strap Cap This capacitor provides the gate driver voltage for internal high side MOSEFET. A 100nF low ESR ceramic capacitor connected between BS pin and LX pin is recommended. Over Current Protection SY8502 provides cycle-by-cycle over current limiting on both high side MOSFET and low-side MOSFET. Under over current condition, if the output AN_SY8502 Rev. 0.9 Silergy Corp. Confidential- Prepared for Customer Use Only 12 AN_SY8502 voltage drops below 33% of set-point, the device will fold back valley current limit to 0.5x typical value. pin. 4) The PCB copper area associated with LX pin must be minimized to avoid the potential noise problem. 1) It is desirable to maximize the PCB copper area connecting to GND pin to achieve the best thermal and noise performance. If the board space allowed, a ground plane is highly desirable. 2) CIN must be close to Pin IN and GND. The loop area formed by CIN and GND must be minimized. CBS 6) If the system chip interfacing with the EN pin has a high impedance state at shutdown mode and the IN pin is connected directly to a power source such as a Li-Ion battery, it is desirable to add a pull down 1Mohm resistor between the EN and GND pins to prevent the noise from falsely turning on the regulator at shutdown mode. CVCC CIN 3) CVCC should be placed close to VCC pin and GND 5) The feedback components RUP and RDOWN, and the trace connecting to the FB pin must NOT be adjacent to the LX net on the PCB layout to avoid the noise problem. AN_SY8502 Rev. 0.9 COUT The layout design of SY8502 is very important for proper operation. Following are the tips for good PCB layout. D1 Layout Design: Silergy Corp. Confidential- Prepared for Customer Use Only 13 AN_SY8502 SO8E Package Outline & PCB layout Recommended PCB Layout (Reference Only) Side view Notes: Top view Front view All dimension in millimeter and exclude mold flash & metal burr. AN_SY8502 Rev. 0.9 Silergy Corp. Confidential- Prepared for Customer Use Only 14 AN_SY8502 Taping & Reel Specification 1. Taping orientation SO8E 3.9/4.1 11.7/12.3 1.45/1.55 Feeding direction 2. Carrier Tape & Reel specification for packages Package type SO8E Tape width (mm) Pocket pitch(mm) Reel size (Inch) Trailer length(mm) Leader length (mm) Qty per reel 12 8 13" 400 400 2500 3. Others: NA AN_SY8502 Rev. 0.0A Silergy Corp. Confidential- Prepared for Customer Use Only 15