CD74HCT243E

[ /Title (CD74 HCT24 2, CD74 HC243 , CD74 HCT24 3) /Subject (High Speed CMOS Logic Quad- Data sheet acquired from Harris Semiconductor SCHS168D November 1997 - Revised October 2003 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs Features Description • Typical Propagation Delay (A to B, B to A) of 7ns at VCC = 5V, CL = 15pF, TA = 25oC The ’HC243 and ’HCT243 silicon-gate CMOS three-state bidirectional noninverting buffers are intended for two-way asynchronous communication between data buses. They have high-drive-current outputs that enable high-speed operation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits and have speeds comparable to low-power Schottky TTL circuits. They can drive 15 LSTTL loads. • Three-State Outputs • Buffered Inputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC The states of the output-enable (OEB, OEA) inputs determine both the direction of flow (A to B, B to A), and the three-state mode. • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs Ordering Information • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V PART NUMBER • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD54HC243, CD54HCT243 (CERDIP) CD74HC243, CD74HCT243 (PDIP, SOIC) TOP VIEW OEB 1 14 VCC NC 2 13 OEA A0 3 12 NC A1 4 11 B0 A2 5 10 B1 A3 6 9 B2 GND 7 8 B3 TEMP. RANGE (oC) CD54HC243F3A -55 to 125 14 Ld CERDIP CD54HCT243F3A -55 to 125 14 Ld CERDIP CD74HC243E -55 to 125 14 Ld PDIP CD74HC243M -55 to 125 14 Ld SOIC CD74HC243MT -55 to 125 14 Ld SOIC CD74HC243M96 -55 to 125 14 Ld SOIC CD74HCT243E -55 to 125 14 Ld PDIP CD74HCT243M -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE 1 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Functional Diagram ‘HC243, ‘HCT243 A0 A1 3 11 4 10 5 9 B1 A2 B2 6 8 A3 OEB OEA B0 B3 1 DIRECTION SELECT LOGIC 13 TRUTH TABLE HC, HCT243 SERIES CONTROL INPUTS DATA PORT STATUS OEB OEA An Bn H H O I L H Z Z H L Z Z L L I O H= High Voltage Level L= Low Voltage Level I= Input O= Output (Same Level as Input) Z= High Impedance To prevent excess currents in the High Z modes all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. 2 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V -6 4.5 3.98 - - 3.84 - 3.7 - V -7.8 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V 7.8 6 - - 0.26 - 0.33 - 0.4 V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VIH or VIL - - 3 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) II VCC or GND - Quiescent Device Current ICC VCC or GND Three-State Leakage Current IOZ High Level Input Voltage 25oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.1 - ±1 - ±1 µA 0 6 - - 8 - 80 - 160 µA VIL or VIH - 6 - - ±0.5 - ±0.5 - ±10 µA VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -6 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 6 4.5 - - 0.26 - 0.33 - 0.4 V PARAMETER Input Leakage Current IO (mA) VCC (V) -40oC TO 85oC HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC to GND - 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Three-State Leakage Current IOZ VIL or VIH - 5.5 - - ±0.5 - ±5.0 - ±10 µA Input Leakage Current Quiescent Device Current NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS An, Bn 1.1 OEA, OEB 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Switching Specifications PARAMETER HC TYPES Propagation Delay Data to Outputs Output High-Z, to High Level to Low Level Output High Level, Output Low Level to High-Z Output Transition Times Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF tPZL, tPZH tPHZ, tPLZ tTLH, tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 90 115 135 ns 4.5 - 18 23 27 ns CL = 15pF 5 7 - - - ns CL = 50pF 6 - 15 20 23 ns CL = 50pF 2 - 150 190 225 ns CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns CL = 50pF 6 - 26 33 38 ns CL = 50pF 2 - 150 190 225 ns CL = 50pF 4.5 - 30 38 45 ns CL = 15pF 5 12 - - - ns CL = 50pF 6 - 26 33 38 ns 2 - 60 75 90 ns 4.5 - 12 15 18 ns CL = 50pF 6 - 10 13 15 ns Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 80 - - - pF 4.5 - 22 28 33 ns CL = 15pF 5 9 - - - ns CL = 50pF 4.5 - 34 43 51 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 12 15 18 ns HCT TYPES Propagation Delay Data to Outputs tPLH, tPHL Output High-Z to High Level to Low Level tPZH, tPZL Output High Level, Output Low Level to High-Z tPHZ, tPLZ Output Transition Times tTLH, tTHL CL = 50pF Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 3, 4) CPD - 5 91 - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per channel. 4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5 CD54HC243, CD74HC243, CD54HCT243, CD74HCT243 Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL 6ns 10% 2.7 1.3 OUTPUT LOW TO OFF 90% OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 3V tPZL tPLZ 50% OUTPUTS ENABLED 6ns GND 10% tPHZ tf OUTPUT DISABLE tPZL tPLZ OUTPUT HIGH TO OFF 6ns tr VCC 90% tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT LOW TO OFF 1.3V 10% INVERTING OUTPUT FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 50% tTLH 90% tPLH tPHL GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL OUTPUT DISABLE tf = 6ns tr = 6ns VCC 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 8409001CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8409001CA CD54HC243F3A CD54HC243F ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC243F CD54HC243F3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8409001CA CD54HC243F3A CD74HC243E ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E CD74HC243EE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -55 to 125 CD74HC243E CD74HC243M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M CD74HC243M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M CD74HC243MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 HC243M CD74HCT243E ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -55 to 125 CD74HCT243E CD74HCT243EE4 ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -55 to 125 CD74HCT243E CD74HCT243M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 HCT243M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of