BQ2018TS-E1TR

bq2018 Power Minder™ IC Features General Description ➤ Multifunction charge/discharge counter The bq2018 is a low-cost charge/discharge counter peripheral packaged in an 8-pin TSSOP or SOIC. It works with an intelligent host controller, providing state-of-charge information for rechargeable batteries. ➤ Resolves signals less than 12.5µV ➤ Internal offset calibration improves accuracy ➤ 1024 bits of NVRAM configured as 128 x 8 ➤ Internal temperature sensor for self-discharge estimation ➤ Single-wire serial interface ➤ Dual operating modes: - Operating: VSR2 (Max. = +200mV) 12.5µVh increments 16-bit SCR Self-discharge count register 1 count/hour @ 25°C 16-bit DTC Discharge time counter 1 count/0.8789s default 1 count/225s if STD is set 16-bit CTC Charge time counter 1 count/0.8789s default 1 count/225s if STC is set 16-bit MODE/ WOE MODE/ Wake output enable — 8-bit 4 bq2018 7f 7f Discharge count high byte 7e Discharge count low byte 7d Charge count high byte 7c Charge count low byte 7b Self-discharge high byte 7a Self-discharge low byte 73 72 79 Discharge time high byte 78 Discharge time low byte User RAM 77 Charge time high byte 76 Charge time low byte 75 Mode/wake output enable 74 Temperature/clear 73 Offset register 00 FG201801.eps Figure 3. Address Map useful in determining an estimation of the battery selfdischarge based on capacity and storage temperature conditions. During charge, the CCR and the Charge Time Counter (CTC) are active. If VSR1 is greater than VSR2, indicating a charge, the CCR counts at a rate equivalent to 12.5µV every hour, and the CTC counts at a rate of 1 count/0.8789 seconds. For example, a +100mV signal produces 8000 CCR counts and 4096 CTC counts each hour. The amount of charge added to the battery can easily be calculated. The bq2018 may be programmed to measure the voltage offset between SR1 and SR2 during pack assembly or at any time by invoking the Calibration mode. The Offset Register (OFR) is used to store the bq2018 offset. The 8bit 2’s complement value stored in the OFR is scaled to the same units as the DCR and CCR, representing the amount of positive or negative offset in the bq2018. The maximum offset for the bq2018 is specified as ± 500µV. Care should be taken to ensure proper PCB layout. Using OFR, the system host can cancel most of the effects of bq2018 offset for greater resolution and accuracy. The DTC and the CTC are 16-bit registers, and roll over beyond ffffh. If a rollover occurs, the corresponding bit in the MODE/WOE register is set, and the counter will subsequently increment at 1/256 of the normal rate (16 counts/hr.). Whenever the signal between SR1 and SR2 is above the Wakeup Output Enable (WOE) threshold and the HDQ pin is high, the bq2018 is in its full operating state. In this state, the DCR, CCR, DTC, CTC, and SCR are fully operational, and the WAKE output is low. During this mode, the internal RAM registers of the bq2018 may be accessed over the HDQ pin, as described in the section “Communicating With the 2018.” Figure 3 shows the bq2018 register address map. The bq2018 uses the upper 13 locations. The remaining memory can store user-specific information such as chemistry, serial number, and manufacturing date. WAKE Output This output is used to inform the system that the voltage difference between SR1 and SR2 is above or below the Wake Output Enable (WOE) threshold programmed in the MODE/WOE register. When the voltage difference between SR1 and SR2 is below VWOE, the WAKE output goes into High Z and remains in this state until the discharge or charge current increases above the specified value. The MODE/WOE resets to 0eh after a power-on reset. VWOE is set by dividing 3.84mV by a value between 1 and 7 (1–7h) according to Table 3. If the signal between SR1 and SR2 is below the WOE threshold (refer to the WAKE section for details) and HDQ remains low for greater than 10 seconds, the bq2018 enters a sleep mode where all register counting is suspended. The bq2018 remains in this mode until HDQ returns high. For self-discharge calculation, the self-discharge count register (SCR) counts at a rate equivalent to 1 count every hour at a nominal 25°C and doubles approximately every 10°C up to 60°C. The SCR count rate is halved every 10 °C below 25°C down to 0°C. The value in SCR is 5 bq2018 Table 3. WOE Thresholds Table 4. Temperature Steps WOE3–1 (hex) VWOE (mV) 0h n/a 1h 3.840 2h 1.920 10–20° 2h × 1/2 3h 1.280 20–30° 3h 1 count/hr. 4h 0.960 30–40° 4h ×2 5h 0.768 40–50° 5h ×4 6h 0.640 50–60° 6h ×8 7h* 0.549 >60° 7h × 16 Temp Value (hex) SDR Count Rate VWOE, then the calibration cycle is reset. The bq2018 then postpones the calibration cycle until the conditions are met. The calibration bit does not reset to zero until a valid calibration cycle is completed. The requirement for HDQ to remain low for the calibration cycle can be disabled by setting the OVRDQ bit to 1. In this case, calibration continues as long as |VSR| < VWOE. The OVRDQ bit is reset to zero at the end of a valid calibration cycle. Communication with the bq2018 always occurs with the least-significant bit being transmitted first. Figure 4 shows an example of a communication sequence to read the bq2018 OFR register. Communicating with the bq2018 bq2018 Registers The bq2018 includes a simple single-pin (referenced to VSS) serial data interface. A host processor uses the interface to access various bq2018 registers. Battery activity may be easily monitored by adding a single contact to the battery pack. Note: The HDQ pin requires an external pull-up or pull-down resistor. The bq2018 command and status registers are listed in Table 5 and described below. Command (CMDR) The write-only command register is accessed when the bq2018 has received eight contiguous valid command bits. The command register contains two fields: The interface uses a command-based protocol, where the host processor sends a command byte to the bq2018. The command directs the bq2018 either to store the next eight bits of data received to a register specified by the command byte or to output the eight bits of data from a register specified by the command byte. n W/R n Command address The W/R bit of the command register is used to select whether the received command is for a read or a write function. The W/R values are The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 5K bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2018 may be sampled using the pulse-width capture timers available on some microcontrollers. A UART may also be used to communicate through the HDQ pin. CMDR Bits 7 6 5 4 3 2 1 0 W/R - - - - - - - Where W/R is If a communication time-out occurs, e.g., the host waits longer than tCYCB for the bq2018 to respond or if this is the first access command, then a BREAK should be sent by the host. The host may then resend the command. The bq2018 detects a BREAK when the HDQ pin is driven to a logic-low state for a time, tB or greater. The HDQ pin then returns to its normal ready-high logic state for a time, tBR. The bq2018 is then ready to receive a command from the host processor. 0 The bq2018 outputs the requested register contents specified by the address portion of the CMDR 1 The following eight bits should be written to the register specified by the address portion of the CMDR The lower seven-bit field of CMDR contains the address portion of the register to be accessed. The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2018 taking the HDQ pin to a logic-low state for a period, tSTRH,B. The next section is the actual data transmission, where the data should be valid by a period, tDSU,B, after the negative edge used to start communication. The data should be held for a period, tDV/tDH, to allow the host or bq2018 to sample the data bit. CMDR Bits 7 - 6 5 AD6 AD5 4 3 2 1 0 AD4 AD3 AD2 AD1 AD0 Discharge Count Registers (DCRH/DCRL) The DCRH high-byte register (address = 7fh) and the DCRL low-byte register (address = 7eh) contain the count 8 bq2018 DTCH and DTCL increment at a rate of 16 counts per hour. Note: If a second rollover occurs, STC is cleared. Access to the bq2018 should be timed to clear CTCH/CTCL more often than every 170 days. The TMP/CLR register is used to force the reset of both the CTCH and CTCL to zero. of the discharge, and are incremented whenever VSR1 < VSR2. These registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. The TMP/CLR register is used to force the reset of both the DCRH and DCRL to zero. Charge Count Registers (CCRH/CCRL) Mode/Wake-up Enable Register The CCRH high-byte register (address = 7dh) and the CCRL low-byte register (address = 7ch) contain the count of the charge, and are incremented whenever VSR1 > VSR2. These registers continue to count beyond ffffh, so proper register maintenance should be done by the host system. The TMP/CLR register is used to force the reset of both the CCRH and CCRL to zero. The Mode/WOE register (address = 75h) contains the calibration, wakeup enable information, and the STC and STD bits as described below. The Override DQ(OVRDQ) bit (bit 7) is used to override the requirement for HDQ to be low prior to initiating VOS calibration. This bit is normally set to zero. If OVRDQ is written to one, the bq2018 begins offset calibration when |VSR|