NJ88C25/KA/MP

THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS NJ88C25 NJ88C25 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DS3280-1.3 NJ88C25 FREQUENCY SYNTHESISER (MICROPROCESSOR SERIAL INTERFACE) The NJ88C25 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable ‘M’ counter, 7-bit programmable ‘A’ counter, latched and buffered Band 0 and Band 1 outputs and the necessary control and latch circuitry for accepting and latching the input data. Data is presented serially under external control from a suitable microprocessor. Although 30 bits of data are initially required to program all counters, subsequent updating can be abbreviated to 19 bits, when only the ‘A’, ‘M’ and ‘B’ counters require changing. The NJ88C25 is intended to be used in conjunction with a twomodulus prescaler such as the SP8710 series to produce a universal binary coded synthesiser. PDA 1 18 CH PDB 2 17 RB FV 3 16 MC LD 4 15 CAP FIN 5 NJ88C25 14 VSS 6 13 CLOCK VDD 7 12 DATA BAND 0 8 11 BAND 1 OSC IN 9 10 OSC OUT DG18, DP18, MP18 FEATURES ■ Low Power Consumption Fig.1 Pin connections - top view ■ High Performance Sample and Hold Phase Detector ■ Serial Input with Fast Update Feature ORDERING INFORMATION NJ88C25 KA DG Ceramic DIL Package NJ88C25 KA DP Plastic DIL Package NJ88C25 KA MP Miniature Plastic DIL Package ABSOLUTE MAXIMUM RATINGS Supply voltage, VDD2VSS: 20·5V to 7V Input voltage Open drain output, pins 3 and 4: 7V All other pins: VSS20·3V to VDD10·3V Storage temperature: 265°C to 1150°C (DG package) 255°C to 1125°C (DP and MP packages) RB 17 OSC IN OSC OUT 9 ENABLE REFERENCE COUNTER (11BITS) fr 42 10 CAP CH 15 18 SAMPLE/HOLD PHASE DETECTOR 1 FREQUENCY/ PHASE DETECTOR 2 PDA LATCH 6 LATCH 7 LATCH 8 12 DATA 14 ENABLE CLOCK 13 ‘B’ REGISTER LATCH 6 BAND 0 BAND 1 FIN fV ‘R’ REGISTER ‘M’ REGISTER ‘A’ REGISTER LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 11 3 ‘M’ COUNTER (10 BITS) ‘A’ COUNTER (7 BITS) VSS LOCK DETECT (LD) VSS 8 FV VSS 5 CONTROL LOGIC VDD 4 PDB 7 6 Fig.2 Block diagram 16 MODULUS CONTROL OUTPUT (MC) NJ88C25 ELECTRICAL CHARACTERISTICS AT VDD = 5V Test conditions unless otherwise stated: VDD–VSS=2·7V to 5·5V. Temperature range = –30°C to +70°C DC Characteristics Value Characteristic Units Supply current OUTPUTS Modulus Control (MC), BAND 1 and BAND 2 High level Low level Lock Detect (LD) and FV Low level Open drain pull-up voltage PDB High level Low level 3-state leakage current Typ. Conditions Max. 5·5 0·7 3·7 mA mA mA fosc, fFIN = 20MHz fosc, fFIN = 1MHz fosc, fFIN = 10MHz 0·4 V V ISOURCE = 1mA ISINK = 1mA 0·4 7·0 V V ISINK = 4mA 0·4 ±0·1 V V µA ISOURCE = 4mA ISINK = 4mA VDD20·4 4·6    Min. 0 to 5V square wave AC Characteristics Value Characteristic Units 200 20 30 0·5 0·5 0·2 0·2 0·2 0·2 0·2 3 Conditions Max. 50 tCH 2 500 5 1 1 5 mV RMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, ns See note 2 µs µs µs µs µs µs µs V V ns kΩ nF nF kΩ    FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to modulus control MC Programming Inputs Clock high time, tCH Clock low time, tCL Enable set-up time, tES (see note 5) Enable hold time, tEH Data set-up time, tDS Data hold time, tDH Clock rise and fall times Positive threshold Negative threshold Phase Detector Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Programming capacitor, CAP Output resistance, PDA Typ.          Min. All timing periods are referenced to the negative transition of the clock waveform. See note 5 TTL compatible, see note 1 See note 3 NOTES 1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs. 4. The inputs to the device should be at logic ‘0’ when power is applied if latch-up conditions are to be avoided. This includes the OSC IN and FIN inputs. 5. Clock to enable set-up time (tES) is variable, dependent on fOSC. It needs to be specified in terms of fOSC, clock high time (tCH) and clock low time (tCL) and must meet the following conditions: 431/fOSCA. Where every possible channel is required, the minimum total division ratio N should be: N>P 22P. 17 RB An external sample and hold phase comparator gain programming resistor should be connected between this pin and VSS. 18 CH An external hold capacitor should be connected between this pin and VSS. Two latch outputs, providing an output of the data from the ‘B’ register. 3 NJ88C25 8 2·0 VDD = 5V FIN = LOW FREQUENCY 0V TO 5V SQUARE WAVE 7 1·5 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VDD = 5V OSC IN, FIN = 0V TO 5V SQUARE WAVE OSC IN 1·0 FIN 6 5 10MHz 4 3 1MHz 2 0·5 TOTAL SUPPLY CURRENT IS THE SUM OF THAT DUE TO FIN AND OSC IN 1 2 3 4 5 6 7 INPUT FREQUENCY (MHz) 8 1 9 0·2 10 Fig. 3 Typical supply current v. input frequency 0·4 0·6 0·8 1·0 1·2 INPUT LEVEL (V RMS) 1·4 1·6 Fig. 4 Typical supply current v. input level, OSC IN PROGRAMMING Reference Divider Chain The comparison frequency depends upon the crystal oscillator frequency and the division ratio of th ‘R’ counter, which can be programmed in the range 3 to 2047, and a fixed divide by two stage. fosc R= 23fcomp where fosc = oscillator frequency, fcomp = comparison frequency, R = ‘R’ counter ratio For example, where the crystal frequency = 10MHz and a channel spacing comparison frequency of 12·5kHz is required, R= 107 = 400 2312·53103 Thus, the ‘R’ register would be programmed to 400 expressed in binary. The total division ratio would then be 23400 = 800 since the total division ratio of the ‘R’ counter plus the 42 stage is from 6 to 4094 in steps of 2. VCO Divider Chain The synthesised frequency of the voltage controlled oscillator (VCO) will depend on the division ratios of the ‘M’ and ‘A’ counters, the ratio of the external two-modulus prescaler (P/P11)and the comparison frequency . For example, if the desired VCO frequency = 275MHz, the comparison frequency is 12·5kHz and a two-modulus prescaler of 464/65 is being used, then 6 N = 275310 3 = 223103 12·5310 Now, N = MP1A, which can be rearranged as N/P = M1A/P. In our example we have P = 64, therefore A 223103 = M1 64 64 such that M = 343 and A /64 = 0·75. Now, M is programmed to the integer part = 343 and A is programmed to the fractional part364 i.e., A = 0·75364 = 48. NB The minimum ratio N that can be used is P 22P (=4032 in our example) for all contiguous channels to be available. To check: N = 343364148 = 22000, which is the required division ratio and is greater than 4032 ( = P 22P ). tCL tCH CLOCK ENABLE The division ratio N = MP1A, where M is the ratio of the ‘M’ counter in the range 8 to 1023 and A is the ratio of the ‘A’ counter in the range 0 to 127. Note that M>A and N = fVCO fcomp tEH tES tEH tDS tDH DATA Fig. 5 Timing diagram showing timing periods required for correct operation 4 tES NJ88C25 1 2 3 4 5 (17)28 (18)29 (19)30 CLOCK ENABLE DATA A6 A5 A4 A3 A2 (M2)R2 (B1)R1 (B0)R0 Fig.6 Timing diagram showing programming details PHASE COMPARATORS Noise output from a synthesiser loop is related to loop gain: KPD KVCO N where KPD is the phase detector constant (volts/rad), KVCO is the VCO constant (rad/sec/volt) and N is the overall loop division ratio. When N is large and the loop gain is low, noise may be reduced by employing a phase comparator with a high gain. The sample and hold phase comparator in the NJ88C25 has a high gain and uses a double sampling technique to reduce spurious outputs to a low level. A standard digital phase/frequency detector driving a threestate output,PDB, provides a ‘coarse’ error signal to enable fast switching between channels. The PDB output is active until the phase error is within the sample and hold phase detector window, when PDB becomes high impedance. Phase-lock is indicated at this point by a low level on LD. The sample and hold phase detector provides a ‘fine’ error signal to give further phase adjustment and to hold the loop in lock. An internally generated ramp, controlled by the digital output from both the reference and main divider chains, is sampled at the reference frequency to give the ‘fine’ error signal, PDA. When in phase lock, this output would be typically at (VDD2VSS)/2 and any offset from this would be proportional to phase error. The relationship between this offset and the phase error is the phase comparator gain, KPDA, which is programmable with an external resistor, RB, and a capacitor, CAP. An internal 50pF capacitor is used in the sample and hold comparator. 5 NJ88C25 HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 CUSTOMER SERVICE CENTRES • FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F Fax : (1) 64 46 06 07 • GERMANY Munich Tel: (089) 3609 06-0 Tx: 523980 Fax : (089) 3609 06-55 • ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 • JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228 • NORTH AMERICA Integrated Circuits and Microwave Products Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. 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