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S-5715ENSL1-M3T1U

S-5715ENSL1-M3T1U

  • 厂商:

    ABLIC(艾普凌科)

  • 封装:

    TO236-3

  • 描述:

    MAGNETIC SWITCH UNIPOLAR SOT23-3

  • 数据手册
  • 价格&库存
S-5715ENSL1-M3T1U 数据手册
S-5715 Series www.ablic.com www.ablicinc.com HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 © ABLIC Inc., 2011-2012 The S-5715 Series, developed by CMOS technology, is a high-accuracy Hall IC that operates with high-speed / middlespeed detection and low current consumption. The output voltage changes when the S-5715 Series detects the intensity level of flux density. Using the S-5715 Series with a magnet makes it possible to detect the open / close and rotation state in various devices. High-density mounting is possible by using the small SOT-23-3 or the super-small SNT-4A packages. Due to its high-accuracy magnetic characteristics, the S-5715 Series can make operation’s dispersion in the system combined with magnet smaller. Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is indispensable.  Features  Pole detection*1:  Detection logic for magnetism*1:  Output form*1:  Magnetic sensitivity: *1  Operating cycle (current consumption) :  Power supply voltage range:  Operation temperature range:  Lead-free (Sn 100%), halogen-free*2 Detection of both poles, S pole or N pole Active "L", active "H" Nch open-drain output, CMOS output BOP = 3.0 mT typ. Product with both poles detection tCYCLE = 0.10 ms (1400 A) typ. tCYCLE = 0.90 ms (155 A) typ. tCYCLE = 5.70 ms (26 A) typ. Product with S pole or N pole detection tCYCLE = 0.05 ms (1400 A) typ. tCYCLE = 1.25 ms (60 A) typ. tCYCLE = 6.05 ms (13 A) typ. VDD = 2.7 V to 5.5 V Ta = 40C to 85C *1. The option can be selected. *2. Refer to " Product Name Structure" for details.  Applications  Plaything, portable game  Home appliance  Housing equipment  Industrial equipment  Packages  SOT-23-3  SNT-4A 1 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Block Diagrams 1. Nch open-drain output product VDD OUT Sleep / Awake logic *1 *1 Chopping stabilized amplifier VSS *1. Parasitic diode Figure 1 2. CMOS output product VDD Sleep / Awake logic *1 *1 OUT Chopping stabilized amplifier VSS *1. Parasitic diode Figure 2 2 *1 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Product Name Structure 1. Product name S-5715 x x x x 1 - xxxx U Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and packing specifications*1 M3T1: SOT-23-3, Tape I4T1: SNT-4A, Tape Magnetic sensitivity 1: BOP = 3.0 mT typ. Detection logic for magnetism L: Active "L" H: Active "H" Pole detection D: Detection of both poles S: Detection of S pole N: Detection of N pole Output form N: Nch open-drain output C: CMOS output Operating cycle C: tCYCLE = 5.70 ms typ. (product with both poles detection) tCYCLE = 6.05 ms typ. (product with S pole or N pole detection) D: tCYCLE = 0.90 ms typ. (product with both poles detection) tCYCLE = 1.25 ms typ. (product with S pole or N pole detection) E: tCYCLE = 0.10 ms typ. (product with both poles detection) tCYCLE = 0.05 ms typ. (product with S pole or N pole detection) *1. Refer to the tape drawing. 2. Packages Table 1 Package Name SOT-23-3 SNT-4A Dimension MP003-C-P-SD PF004-A-P-SD Package Drawing Codes Tape MP003-C-C-SD PF004-A-C-SD Reel MP003-Z-R-SD PF004-A-R-SD Land  PF004-A-L-SD 3 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series 3. Product name list 3. 1 SOT-23-3 3. 1. 1 Nch open-drain output product Table 2 Operating Cycle Output Form Pole Detection (tCYCLE) Nch open-drain output S-5715CNDL1-M3T1U 5.70 ms Both poles Nch open-drain output S-5715CNSL1-M3T1U 6.05 ms S pole Nch open-drain output S-5715DNDL1-M3T1U 0.90 ms Both poles Nch open-drain output S-5715DNSL1-M3T1U 1.25 ms S pole Nch open-drain output S-5715ENDL1-M3T1U 0.10 ms Both poles Nch open-drain output S-5715ENSL1-M3T1U 0.05 ms S pole Nch open-drain output S-5715ENSH1-M3T1U 0.05 ms S pole Remark Please contact our sales office for products other than the above. Product Name 3. 1. 2 Detection Logic Magnetic for Magnetism Sensitivity (BOP) Active "L" Active "L" Active "L" Active "L" Active "L" Active "L" Active "H" 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. CMOS output product Table 3 Operating Cycle Output Form Pole Detection (tCYCLE) S-5715CCDL1-M3T1U 5.70 ms CMOS output Both poles S-5715CCSL1-M3T1U 6.05 ms CMOS output S pole S-5715DCDL1-M3T1U 0.90 ms CMOS output Both poles S-5715DCSL1-M3T1U 1.25 ms CMOS output S pole S-5715ECDL1-M3T1U 0.10 ms CMOS output Both poles S-5715ECSL1-M3T1U 0.05 ms CMOS output S pole Remark Please contact our sales office for products other than the above. Product Name 3. 2 Detection Logic Magnetic for Magnetism Sensitivity (BOP) Active "L" Active "L" Active "L" Active "L" Active "L" Active "L" 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. SNT-4A 3. 2. 1 Nch open-drain output product Table 4 Operating Cycle Output Form Pole Detection (tCYCLE) Nch open-drain output S-5715CNDL1-I4T1U 5.70 ms Both poles Nch open-drain output S-5715CNSL1-I4T1U 6.05 ms S pole Nch open-drain output S-5715CNNL1-I4T1U 6.05 ms N pole Nch open-drain output S-5715DNDL1-I4T1U 0.90 ms Both poles Nch open-drain output S-5715DNSL1-I4T1U 1.25 ms S pole Nch open-drain output S-5715ENDL1-I4T1U 0.10 ms Both poles Remark Please contact our sales office for products other than the above. Product Name 3. 2. 2 Detection Logic for Magnetism Active "L" Active "L" Active "L" Active "L" Active "L" Active "L" Magnetic Sensitivity (BOP) 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. CMOS output product Table 5 Operating Cycle Output Form Pole Detection (tCYCLE) S-5715CCDL1-I4T1U 5.70 ms CMOS output Both poles S-5715CCSL1-I4T1U 6.05 ms CMOS output S pole S-5715CCNL1-I4T1U 6.05 ms CMOS output N pole S-5715DCDL1-I4T1U 0.90 ms CMOS output Both poles S-5715DCSL1-I4T1U 1.25 ms CMOS output S pole S-5715ECDL1-I4T1U 0.10 ms CMOS output Both poles Remark Please contact our sales office for products other than the above. Product Name 4 Detection Logic for Magnetism Active "L" Active "L" Active "L" Active "L" Active "L" Active "L" Magnetic Sensitivity (BOP) 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. 3.0 mT typ. HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Pin Configurations 1. SOT-23-3 Table 6 Top view 1 2 Pin No. Symbol Description 1 VSS GND pin 2 VDD Power supply pin 3 OUT Output pin 3 Figure 3 2. SNT-4A Table 7 Top view 1 2 4 3 Figure 4 Pin No. Symbol Description 1 VDD Power supply pin 2 VSS GND pin 3 *1 NC No connection 4 OUT Output pin *1. The NC pin is electrically open. The NC pin can be connected to the VDD pin or the VSS pin. 5 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Absolute Maximum Ratings Table 8 Item Symbol Power supply voltage Output current Output voltage (Ta = 25C unless otherwise specified) Absolute Maximum Rating Unit Nch open-drain output product VDD VSS  0.3 to VSS  7.0 V IOUT 2.0 mA VSS  0.3 to VSS  7.0 V VSS  0.3 to VDD  0.3 430*1 300*1 V mW mW VOUT CMOS output product Power dissipation SOT-23-3 SNT-4A PD Operation ambient temperature Topr 40 to 85 C Storage temperature Tstg 40 to 125 C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm  76.2 mm  t1.6 mm (2) Name: JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation (PD) [mW] 600 SNT-4A 200 0 Figure 5 6 SOT-23-3 400 0 150 100 50 Ambient Temperature (Ta) [C] Power Dissipation of Package (When Mounted on Board) HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Electrical Characteristics 1. Product with both poles detection 1. 1 S-5715CxDxx Table 9 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT  Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7  5.0 26.0 5.5 40.0 V A  1   0.4 V 2   0.4 V 2 VDD  0.4   V 3   1 A 4 Leakage current ILEAK Awake mode time tAW   0.10  ms  Sleep mode time tSL   5.60  ms  Operating cycle tCYCLE  5.70 12.00 ms  1. 2 tAW  tSL S-5715DxDxx Table 10 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT  Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7  5.0 155.0 5.5 230.0 V A  1   0.4 V 2   0.4 V 2 VDD  0.4   V 3   1 A 4 Leakage current ILEAK Awake mode time tAW   0.10  ms  Sleep mode time tSL   0.80  ms  Operating cycle tCYCLE  0.90 2.00 ms  tAW  tSL 7 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series 1. 3 S-5715ExDxx Table 11 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT  Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7  5.0 5.5 1400.0 2000.0 V A  1   0.4 V 2   0.4 V 2 VDD  0.4   V 3   1 A 4 Leakage current ILEAK Awake mode time tAW   0.10  ms  Sleep mode time tSL   0.00  ms  Operating cycle tCYCLE  0.10 0.20 ms  8 tAW  tSL HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series 2. Product with S pole or N pole detection 2. 1 S-5715CxSxx, S-5715CxNxx Table 12 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT  Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7  5.0 13.0 5.5 20.0 V A  1   0.4 V 2   0.4 V 2 VDD  0.4   V 3   1 A 4 Leakage current ILEAK Awake mode time tAW   0.05  ms  Sleep mode time tSL   6.00  ms  Operating cycle tCYCLE  6.05 12.00 ms  2. 2 tAW  tSL S-5715DxSxx, S-5715DxNxx Table 13 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT  Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7  5.0 60.0 5.5 90.0 V A  1   0.4 V 2   0.4 V 2 VDD  0.4   V 3   1 A 4 Leakage current ILEAK Awake mode time tAW   0.05  ms  Sleep mode time tSL   1.20  ms  Operating cycle tCYCLE  1.25 2.50 ms  tAW  tSL 9 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series 2. 3 S-5715ExSxx, S-5715ExNxx Table 14 Item Power supply voltage Current consumption Output voltage (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Test Condition Min. Typ. Max. Unit Circuit Symbol VDD IDD VOUT  Average value Nch open-drain output product Output transistor Nch, IOUT = 2 mA Output transistor Nch, IOUT = 2 mA CMOS output product Output transistor Pch, IOUT = 2 mA Nch open-drain output product Output transistor Nch, VOUT = 5.5 V 2.7  5.0 5.5 1400.0 2000.0 V A  1   0.4 V 2   0.4 V 2 VDD  0.4   V 3   1 A 4 Leakage current ILEAK Awake mode time tAW   0.05  ms  Sleep mode time tSL   0.00  ms  Operating cycle tCYCLE  0.05 0.10 ms  10 tAW  tSL HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Magnetic Characteristics 1. Product with both poles detection Table 15 Item Operation point *1 Release point*2 Hysteresis width*3 2. S pole N pole S pole N pole S pole N pole Symbol BOPS BOPN BRPS BRPN BHYSS BHYSN (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Condition Min. Typ. Max. Unit Test Circuit  1.4 3.0 4.0 mT 5  4.0 3.0 1.4 mT 5  1.1 2.2 3.7 mT 5  3.7 2.2 1.1 mT 5 BHYSS = BOPS  BRPS  0.8  mT 5 BHYSN = BOPN  BRPN  0.8  mT 5 Product with S pole detection Table 16 (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Operation point*1 S pole *2 Release point S pole Hysteresis width*3 S pole 3. Symbol BOPS BRPS BHYSS Condition Min. Typ. Max. Unit Test Circuit   1.4 1.1  3.0 2.2 0.8 4.0 3.7  mT mT mT 5 5 5 BHYSS = BOPS  BRPS Product with N pole detection Table 17 Item Operation point*1 N pole *2 Release point N pole Hysteresis width*3 N pole Symbol BOPN BRPN BHYSN (Ta = 25C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Condition Min. Typ. Max. Unit Test Circuit  4.0 3.0 1.4 mT 5  3.7 2.2 1.1 mT 5 BHYSN = BOPN  BRPN  0.8  mT 5 *1. BOPN, BOPS: Operation points BOPN and BOPS are the values of magnetic flux density when the output voltage (VOUT) is inverted after the magnetic flux density applied to the S-5715 Series by the magnet (N pole or S pole) is increased (the magnet is moved closer). Even when the magnetic flux density exceeds BOPN or BOPS, VOUT retains the status. *2. BRPN, BRPS: Release points BRPN and BRPS are the values of magnetic flux density when the output voltage (VOUT) is inverted after the magnetic flux density applied to the S-5715 Series by the magnet (N pole or S pole) is decreased (the magnet is moved further away). Even when the magnetic flux density falls below BRPN or BRPS, VOUT retains the status. *3. BHYSN, BHYSS: Hysteresis widths BHYSN and BHYSS are the difference between BOPN and BRPN, and BOPS and BRPS, respectively. Remark The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss. 11 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Test Circuits A R*1 100 k VDD S-5715 Series OUT VSS *1. Resistor (R) is unnecessary for the CMOS output product. Figure 6 Test Circuit 1 VDD S-5715 Series OUT VSS Figure 7 A V Test Circuit 2 VDD S-5715 Series OUT VSS Figure 8 12 A V Test Circuit 3 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series VDD S-5715 Series OUT A VSS V Figure 9 Test Circuit 4 R*1 100 k VDD S-5715 Series OUT VSS *1. V Resistor (R) is unnecessary for the CMOS output product. Figure 10 Test Circuit 5 13 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Standard Circuit *1 VDD CIN 0.1 F R 100 k S-5715 Series OUT VSS *1. Resistor (R) is unnecessary for the CMOS output product. Figure 11 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 14 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Operation 1. Direction of applied magnetic flux The S-5715 Series detects the flux density which is vertical to the marking surface. In product with both poles detection, the output voltage (VOUT) is inverted when the S pole or N pole is moved closer to the marking surface. In product with S pole detection, the output voltage (VOUT) is inverted when the S pole is moved closer to the marking surface. In product with N pole detection, the output voltage (VOUT) is inverted when the N pole is moved closer to the marking surface. Figure 12 and Figure 13 show the direction in which magnetic flux is being applied. 1. 1 SOT-23-3 1. 2 N S SNT-4A N S Marking surface Marking surface Figure 12 2. Figure 13 Position of Hall sensor Figure 14 and Figure 15 show the position of Hall sensor. The center of this Hall sensor is located in the area indicated by a circle, which is in the center of a package as described below. The following also shows the distance (typ. value) between the marking surface and the chip surface of a package. 2. 1 SOT-23-3 Top view 2. 2 1 The center of Hall sensor; in this  0.3 mm 4 2 3 The center of Hall sensor; in this  0.3 mm 1 2 SNT-4A Top view 3 0.16 mm (typ.) 0.7 mm (typ.) Figure 14 Figure 15 15 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series 3. Basic operation The S-5715 Series changes the output voltage level (VOUT) according to the level of the magnetic flux density (N pole or S pole) applied by a magnet. The following explains the operation when the magnetism detection logic is active "L". 3. 1 Product with both poles detection When the magnetic flux density vertical to the marking surface exceeds BOPN or BOPS after the S pole or N pole of a magnet is moved closer to the marking surface of the S-5715 Series, VOUT changes from "H" to "L". When the S pole or N pole of a magnet is moved further away from the marking surface of the S-5715 Series and the magnetic flux density is lower than BRPN or BRPS, VOUT changes from "L" to "H". Figure 16 shows the relationship between the magnetic flux density and VOUT. VOUT BHYSN BHYSS H L N pole BOPN 0 BRPN BRPS BOPS S pole Flux density (B) Figure 16 3. 2 Product with S pole detection When the magnetic flux density vertical to the marking surface exceeds BOPS after the S pole of a magnet is moved closer to the marking surface of the S-5715 Series, VOUT changes from "H" to "L". When the S pole of a magnet is moved further away from the marking surface of the S-5715 Series and the magnetic flux density is lower than BRPS, VOUT changes from "L" to "H". Figure 17 shows the relationship between the magnetic flux density and VOUT. VOUT BHYSS H L N pole 0 BRPS Flux density (B) Figure 17 16 BOPS S pole HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series 3. 3 Product with N pole detection When the magnetic flux density vertical to the marking surface exceeds BOPN after the N pole of a magnet is moved closer to the marking surface of the S-5715 Series, VOUT changes from "H" to "L". When the N pole of a magnet is moved further away from the marking surface of the S-5715 Series and the magnetic flux density is lower than BRPN, VOUT changes from "L" to "H". Figure 18 shows the relationship between the magnetic flux density and VOUT. VOUT BHYSN H L N pole BOPN BRPN 0 S pole Flux density (B) Figure 18 17 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Precautions  If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feedthrough current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.  Note that the IC may malfunction if the power supply voltage rapidly changes.  Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.  Large stress on this IC may affect on the magnetic characteristics. Avoid large stress which is caused by bend and distortion during mounting the IC on a board or handle after mounting.  ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 18 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series  Marking Specifications 1. SOT-23-3 Top view (1) to (3): (4): 1 Product code (Refer to Product name vs. Product code.) Lot number (1) (2) (3) (4) 2 3 Product name vs. Product code 1. 1 Nch open-drain output product Product Code Product Name (1) (2) (3) X 2 C S-5715CNDL1-M3T1U X 2 L S-5715CNSL1-M3T1U X 2 B S-5715DNDL1-M3T1U X 2 O S-5715DNSL1-M3T1U X 2 R S-5715ENDL1-M3T1U X 2 A S-5715ENSL1-M3T1U X 2 U S-5715ENSH1-M3T1U 1. 2 CMOS output product Product Name S-5715CCDL1-M3T1U S-5715CCSL1-M3T1U S-5715DCDL1-M3T1U S-5715DCSL1-M3T1U S-5715ECDL1-M3T1U S-5715ECSL1-M3T1U Product Code (1) (2) (3) X 2 M X 2 N X 2 P X 2 Q X 2 S X 2 T 19 HIGH-SPEED / MIDDLE-SPEED LOW CURRENT CONSUMPTION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC Rev.2.3_02 S-5715 Series 2. SNT-4A Top view 1 (1) to (3): 4 (1) (2) (3) 2 3 Product name vs. Product code 2. 1 Nch open-drain output product Product Code Product Name (1) (2) (3) X 2 C S-5715CNDL1-I4T1U X 2 L S-5715CNSL1-I4T1U X 2 V S-5715CNNL1-I4T1U X 2 B S-5715DNDL1-I4T1U X 2 O S-5715DNSL1-I4T1U X 2 R S-5715ENDL1-I4T1U 2. 2 CMOS output product Product Name S-5715CCDL1-I4T1U S-5715CCSL1-I4T1U S-5715CCNL1-I4T1U S-5715DCDL1-I4T1U S-5715DCSL1-I4T1U S-5715ECDL1-I4T1U 20 Product Code (1) (2) (3) X 2 M X 2 N X 2 W X 2 P X 2 Q X 2 S Product code (Refer to Product name vs. Product code.) 2.9±0.2 1 2 3 +0.1 0.16 -0.06 0.95±0.1 1.9±0.2 0.4±0.1 No. MP003-C-P-SD-1.1 TITLE SOT233-C-PKG Dimensions No. MP003-C-P-SD-1.1 ANGLE UNIT mm ABLIC Inc. +0.1 ø1.5 -0 4.0±0.1 2.0±0.1 +0.25 ø1.0 -0 0.23±0.1 4.0±0.1 1.4±0.2 3.2±0.2 1 2 3 Feed direction No. MP003-C-C-SD-2.0 TITLE SOT233-C-Carrier Tape No. MP003-C-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.2±0.5 Enlarged drawing in the central part ø13±0.2 No. MP003-Z-R-SD-1.0 SOT233-C-Reel TITLE MP003-Z-R-SD-1.0 No. QTY. ANGLE UNIT mm ABLIC Inc. 3,000 1.2±0.04 3 4 +0.05 0.08 -0.02 2 1 0.65 0.48±0.02 0.2±0.05 No. PF004-A-P-SD-6.0 TITLE SNT-4A-A-PKG Dimensions No. PF004-A-P-SD-6.0 ANGLE UNIT mm ABLIC Inc. +0.1 ø1.5 -0 4.0±0.1 2.0±0.05 0.25±0.05 +0.1 1.45±0.1 2 1 3 4 ø0.5 -0 4.0±0.1 0.65±0.05 Feed direction No. PF004-A-C-SD-2.0 TITLE SNT-4A-A-Carrier Tape No. PF004-A-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.0±0.3 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PF004-A-R-SD-1.0 TITLE SNT-4A-A-Reel No. PF004-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 5,000 0.52 1.16 2 0.52 0.35 1. 2. 0.3 1 (0.25 mm min. / 0.30 mm typ.) (1.10 mm ~ 1.20 mm) 0.03 mm 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.10 mm ~ 1.20 mm) TITLE SNT-4A-A -Land Recommendation PF004-A-L-SD-4.1 No. No. PF004-A-L-SD-4.1 ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com
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