S-5717 Series
www.ablic.com
www.ablicinc.com
LOW VOLTAGE OPERATION
BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
© ABLIC Inc., 2013
The S-5717 Series, developed by CMOS technology, is a high-accuracy Hall IC that operates at a low voltage and low
current consumption.
The output voltage changes when the S-5717 Series detects the intensity level of flux density. Using the S-5717 Series with
a magnet makes it possible to detect the open / close in various devices.
High-density mounting is possible by using the super-small SNT-4A package.
Due to its low voltage operation and low current consumption, the S-5717 Series is suitable for battery-operated portable
devices. Also, due to its high-accuracy magnetic characteristics, the S-5717 Series can make operation's dispersion in the
system combined with magnet smaller.
Caution
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or automobile
equipment including car audio, keyless entry and engine control unit, contact to ABLIC Inc. is
indispensable.
Features
Pole detection*1:
Detection logic for magnetism*1:
Output form*1:
Magnetic sensitivity:
*1
Operating cycle (current consumption) :
Power supply voltage range:
Operation temperature range:
Lead-free (Sn 100%), halogen-free
Detection of both poles, S pole or N pole
Active "L", active "H"
Nch open-drain output, CMOS output
BOP = 3.3 mT typ.
Product with both poles detection
tCYCLE = 50.50 ms (IDD = 2.0 A) typ.
Product with S pole or N pole detection
tCYCLE = 50.85 ms (IDD = 1.4 A) typ.
VDD = 1.6 V to 3.6 V
Ta = 40C to 85C
*1. The option can be selected.
Applications
Mobile phone, smart phone
Notebook PC, tablet PC
Digital video camera
Plaything, portable game
Home appliance
Package
SNT-4A
1
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Block Diagrams
1.
Nch open-drain output product
VDD
OUT
Sleep / Awake logic
*1
*1
Chopping
stabilized amplifier
VSS
*1. Parasitic diode
Figure 1
2.
CMOS output product
VDD
Sleep / Awake logic
*1
*1
OUT
Chopping
stabilized amplifier
VSS
*1. Parasitic diode
Figure 2
2
*1
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Product Name Structure
1.
Product name
S-5717
A x
x
x
x
-
I4T1
U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and packing specifications*1
I4T1:
SNT-4A, Tape
Magnetic sensitivity
8: BOP = 3.3 mT typ.
Detection logic for magnetism
L: Active "L"
H: Active "H"
Pole detection
D: Detection of both poles
S: Detection of S pole
N: Detection of N pole
Output form
N: Nch open-drain output
C: CMOS output
Operating cycle
A: tCYCLE = 50.50 ms typ.
(Product with both poles detection)
tCYCLE = 50.85 ms typ.
(Product with S pole or N pole detection)
*1. Refer to the tape drawing.
2.
Package
Table 1
Package Name
SNT-4A
3.
Dimension
PF004-A-P-SD
Package Drawing Codes
Tape
PF004-A-C-SD
Reel
PF004-A-R-SD
Land
PF004-A-L-SD
Product name list
3. 1
SNT-4A
3. 1. 1
Nch open-drain output product
Table 2
Product Name
S-5717ANDL8-I4T1U
Operating Cycle
(tCYCLE)
50.50 ms typ.
Output Form
Nch open-drain output
Pole Detection
Detection Logic Magnetic Sensitivity
for Magnetism
(BOP)
Both poles
Active "L"
3.3 mT typ.
Remark Please contact our sales office for products other than the above.
3. 1. 2
CMOS output product
Table 3
Product Name
S-5717ACDL8-I4T1U
Operating Cycle
(tCYCLE)
50.50 ms typ.
Output Form
CMOS output
Pole Detection
Detection Logic Magnetic Sensitivity
for Magnetism
(BOP)
Both poles
Active "L"
3.3 mT typ.
Remark Please contact our sales office for products other than the above.
3
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Pin Configuration
1.
SNT-4A
Table 4
Top view
1
2
Pin No.
4
3
Symbol
1
Figure 3
Pin Description
OUT
Output pin
2
VSS
GND pin
3
NC*1
No connection
4
VDD
Power supply pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
Absolute Maximum Ratings
Table 5
Item
Symbol
(Ta = 25C unless otherwise specified)
Absolute Maximum Rating
Unit
Power supply voltage
VDD
VSS 0.3 to VSS 7.0
V
Output current
IOUT
1.0
mA
Output voltage
Nch open-drain output product
CMOS output product
Power dissipation
VOUT
VSS 0.3 to VSS 7.0
V
VSS 0.3 to VDD 0.3
V
300*1
mW
PD
Operation ambient temperature
Topr
40 to 85
C
Storage temperature
Tstg
40 to 125
C
*1.
When mounted on board
[Mounted board]
(1) Board size:
114.3 mm 76.2 mmt1.6 mm
(2) Name:
JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Power Dissipation (PD) [mW]
600
400
200
0
Figure 4
4
0
150
100
50
Ambient Temperature (Ta) [C]
Power Dissipation of Package (When Mounted on Board)
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Electrical Characteristics
1.
Product with both poles detection
1. 1
S-5717AxDxx
Table 6
(Ta = 25C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Output voltage
Symbol
VDD
IDD
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
2.
Condition
Min.
Typ.
Max.
Unit
Test
Circuit
1.60
1.85
2.0
3.60
3.5
V
A
1
0.2
V
2
0.2
V
2
VDD
0.2
V
3
1
A
4
0.10
50.40
50.50
100.00
ms
ms
ms
Average value
Nch open-drain
output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = 0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
tAW tSL
Product with S pole or N pole detection
2. 1
S-5717AxSxx, S-5717AxNxx
Table 7
Item
Power supply voltage
Current consumption
Output voltage
(Ta = 25C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Test
Condition
Min.
Typ.
Max.
Unit
Circuit
Symbol
VDD
IDD
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Average value
Nch open-drain
output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = 0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
tAW tSL
1.60
1.85
1.4
3.60
3.0
V
A
1
0.2
V
2
0.2
V
2
VDD
0.2
V
3
1
A
4
0.05
50.80
50.85
100.00
ms
ms
ms
5
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Magnetic Characteristics
1.
Product with both poles detection
1. 1
Product with BOP = 3.3 mT typ.
Table 8
(Ta = 25C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
Release point*2
Hysteresis width*3
2.
S pole
N pole
S pole
N pole
S pole
N pole
Symbol
BOPS
BOPN
BRPS
BRPN
BHYSS
BHYSN
Condition
BHYSS = BOPS BRPS
BHYSN = BOPN BRPN
Min.
2.3
4.7
1.2
3.4
Typ.
3.3
3.3
2.4
2.4
0.9
0.9
Max.
4.7
2.3
3.4
1.2
Unit
mT
mT
mT
mT
mT
mT
Test Circuit
5
5
5
5
5
5
Product with S pole detection
2. 1
Product with BOP = 3.3 mT typ.
Table 9
(Ta = 25C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
S pole
Release point*2
S pole
Hysteresis width*3
S pole
3.
Symbol
BOPS
BRPS
BHYSS
Condition
BHYSS = BOPS BRPS
Min.
2.3
1.2
Typ.
3.3
2.4
0.9
Max.
4.7
3.4
Unit
mT
mT
mT
Test Circuit
5
5
5
Product with N pole detection
3. 1
Product with BOP = 3.3 mT typ.
Table 10
(Ta = 25C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
N pole
*2
Release point
N pole
Hysteresis width*3
N pole
Symbol
BOPN
BRPN
BHYSN
Condition
Min.
Typ.
Max.
Unit
Test Circuit
4.7
3.4
3.3
2.4
0.9
2.3
1.2
mT
mT
mT
5
5
5
BHYSN = BOPN BRPN
*1. BOPN, BOPS: Operation points
BOPN and BOPS are the values of magnetic flux density when the output voltage (VOUT) is inverted after the magnetic flux
density applied to the S-5717 Series by the magnet (N pole or S pole) is increased (the magnet is moved closer).
Even when the magnetic flux density exceeds BOPN or BOPS, VOUT retains the status.
*2. BRPN, BRPS: Release points
BRPN and BRPS are the values of magnetic flux density when the output voltage (VOUT) is inverted after the magnetic flux
density applied to the S-5717 Series by the magnet (N pole or S pole) is decreased (the magnet is moved further away).
Even when the magnetic flux density falls below BRPN or BRPS, VOUT retains the status.
*3. BHYSN, BHYSS: Hysteresis widths
BHYSN and BHYSS are the difference between BOPN and BRPN, and BOPS and BRPS, respectively.
Remark
6
The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss.
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Test Circuits
A
*1
R
100 k
VDD
S-5717
Series OUT
VSS
*1.
Resistor (R) is unnecessary for the CMOS output product.
Figure 5
Test Circuit 1
VDD
S-5717
Series OUT
VSS
Figure 6
A
V
Test Circuit 2
VDD
S-5717
Series OUT
VSS
Figure 7
A
V
Test Circuit 3
7
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
VDD
S-5717
Series OUT
A
VSS
V
Figure 8
Test Circuit 4
R*1
100 k
VDD
S-5717
Series OUT
VSS
*1.
Resistor (R) is unnecessary for the CMOS output product.
Figure 9
8
V
Test Circuit 5
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Standard Circuit
*1
VDD
CIN
0.1 F
R
100 k
S-5717
Series OUT
VSS
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 10
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
9
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Operation
1.
Direction of applied magnetic flux
The S-5717 Series detects the flux density which is vertical to the marking surface.
In the product with both poles detection, the output voltage (VOUT) is inverted when the S pole or N pole is moved closer
to the marking surface.
In the product with S pole detection, VOUT is inverted when the S pole is moved closer to the marking surface.
In the product with N pole detection, VOUT is inverted when the N pole is moved closer to the marking surface.
Figure 11 shows the direction in which magnetic flux is being applied.
N
S
Marking surface
Figure 11
2.
Position of Hall sensor
Figure 12 shows the position of Hall sensor.
The center of this Hall sensor is located in the area indicated by a circle, which is in the center of a package as
described below.
The following also shows the distance (typ. value) between the marking surface and the chip surface of a package.
Top view
1
The center of Hall sensor;
in this 0.3 mm
4
2
3
0.16 mm (typ.)
Figure 12
10
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
3.
Basic operation
The S-5717 Series changes the output voltage level (VOUT) according to the level of the magnetic flux density (N pole
or S pole) applied by a magnet.
The following explains the operation when the magnetism detection logic is active "L".
3. 1
Product with both poles detection
When the magnetic flux density vertical to the marking surface exceeds the operation point (BOPN or BOPS) after
the S pole or N pole of a magnet is moved closer to the marking surface of the S-5717 Series, VOUT changes from
"H" to "L". When the S pole or N pole of a magnet is moved further away from the marking surface of the S-5717
Series and the magnetic flux density is lower than the release point (BRPN or BRPS), VOUT changes from "L" to "H".
Figure 13 shows the relationship between the magnetic density and VOUT.
VOUT
BHYSN
BHYSS
H
L
N pole
BOPN
BRPN
0
BRPS
BOPS
S pole
Magnetic flux density (B)
Figure 13
3. 2
Product with S pole detection
When the magnetic flux density vertical to the marking surface exceeds BOPS after the S pole of a magnet is
moved closer to the marking surface of the S-5717 Series, VOUT changes from "H" to "L". When the S pole of a
magnet is moved further away from the marking surface of the S-5717 Series and the magnetic flux density is
lower than BRPS, VOUT changes from "L" to "H".
Figure 14 shows the relationship between the magnetic density and VOUT.
VOUT
BHYSS
H
L
N pole
0
BRPS
BOPS
S pole
Magnetic flux density (B)
Figure 14
11
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
3. 3
Product with N pole detection
When the magnetic flux density vertical to the marking surface exceeds BOPN after the N pole of a magnet is
moved closer to the marking surface of the S-5717 Series, VOUT changes from "H" to "L". When the N pole of a
magnet is moved further away from the marking surface of the S-5717 Series and the magnetic flux density is
lower than BRPN, VOUT changes from "L" to "H".
Figure 15 shows the relationship between the magnetic density and VOUT.
VOUT
BHYSN
H
L
N pole
BOPN
BRPN
0
S pole
Magnetic flux density (B)
Figure 15
12
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Precautions
If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feedthrough current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.
Note that the IC may malfunction if the power supply voltage rapidly changes.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
Large stress on this IC may affect on the magnetic characteristics. Avoid large stress which is caused by bend and
distortion during mounting the IC on a board or handle after mounting.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
13
LOW VOLTAGE OPERATION BOTH POLES / UNIPOLAR DETECTION TYPE HALL IC
Rev.1.0_02
S-5717 Series
Marking Specification
1.
SNT-4A
Top view
1
(1) to (3):
4
(1) (2) (3)
2
3
Product name vs. Product code
1. 1
Nch open-drain output product
Product Name
S-5717ANDL8-I4T1U
1. 2
CMOS output product
Product Name
S-5717ACDL8-I4T1U
14
Product Code
(1)
(2)
(3)
4
S
A
Product Code
(1)
(2)
(3)
4
S
B
Product code (Refer to Product name vs. Product code.)
1.2±0.04
3
4
+0.05
0.08 -0.02
2
1
0.65
0.48±0.02
0.2±0.05
No. PF004-A-P-SD-6.0
TITLE
SNT-4A-A-PKG Dimensions
No.
PF004-A-P-SD-6.0
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
4.0±0.1
2.0±0.05
0.25±0.05
+0.1
1.45±0.1
2
1
3
4
ø0.5 -0
4.0±0.1
0.65±0.05
Feed direction
No. PF004-A-C-SD-2.0
TITLE
SNT-4A-A-Carrier Tape
No.
PF004-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PF004-A-R-SD-1.0
TITLE
SNT-4A-A-Reel
No.
PF004-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
1.16
2
0.52
0.35
1.
2.
0.3
1
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
0.03 mm
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
TITLE
SNT-4A-A
-Land Recommendation
PF004-A-L-SD-4.1
No.
No. PF004-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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