S-5724 Series
www.ablic.com
LOW VOLTAGE OPERATION
HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
© ABLIC Inc., 2012-2021
The S-5724 Series, developed by CMOS technology, is a high-accuracy hall effect latch IC that operates at a low voltage
with a high-sensitivity, a high-speed detection and low current consumption.
The output voltage changes when the S-5724 Series detects the intensity level of magnetic flux density and a polarity
change. Using the S-5724 Series with a magnet makes it possible to detect the rotation status in various devices.
High-density mounting is possible by using the small SOT-23-3 or the super-small SNT-4A packages.
Due to its high-accuracy magnetic characteristics, the S-5724 Series can make operation's dispersion in the system
combined with magnet smaller.
Caution
This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, it is imperative to
contact our sales representatives.
Features
• Pole detection:
• Output logic*1:
• Output form*1:
• Magnetic sensitivity:
• Operating cycle (current consumption)*1:
• Power supply voltage range:
• Operation temperature range:
• Built-in power-down circuit:
• Lead-free (Sn 100%), halogen-free
Bipolar latch
VOUT = "L" at S pole detection
VOUT = "H" at S pole detection
Nch open-drain output, CMOS output
BOP = 3.0 mT typ.
tCYCLE = 50 μs (IDD = 640.0 μA) typ.
tCYCLE = 1.25 ms (IDD = 26.0 μA) typ.
tCYCLE = 6.05 ms (IDD = 6.0 μA) typ.
VDD = 1.6 V to 3.5 V
Ta = −40°C to +85°C
Extends battery life (only SNT-4A)
*1. The option can be selected.
Applications
• Digital still camera
• Plaything, portable game
• Home appliance
Packages
• SOT-23-3
• SNT-4A
1
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
Block Diagrams
1. Nch open-drain output product
1. 1 Product without power-down function
VDD
OUT
Sleep / Awake logic
*1
*1
Chopping
stabilized amplifier
VSS
*1. Parasitic diode
Figure 1
1. 2 Product with power-down function (SNT-4A)
VDD
*1
Power-down circuit
Sleep / Awake logic
OUT
CE
*1
*1
*1
Chopping
stabilized amplifier
VSS
*1. Parasitic diode
Figure 2
2
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
2. CMOS output product
2. 1 Product without power-down function
VDD
Sleep / Awake logic
*1
*1
OUT
Chopping
stabilized amplifier
*1
VSS
*1. Parasitic diode
Figure 3
2. 2 Product with power-down function (SNT-4A)
VDD
*1
Power-down circuit
Sleep / Awake logic
*1
CE
OUT
*1
*1
*1
Chopping
stabilized amplifier
VSS
*1. Parasitic diode
Figure 4
3
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
Product Name Structure
1. Product name
S-5724 x x
B x 1 -
xxxx U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and packing specifications*1
M3T1: SOT-23-3, Tape
I4T1:
SNT-4A, Tape
Magnetic sensitivity
1: BOP = 3.0 mT typ.
Output logic
L: VOUT = "L" at S pole detection
H: VOUT = "H" at S pole detection
Pole detection
B: Bipolar latch
Output form
N: Nch open-drain output
C: CMOS output
Operating cycle
C: tCYCLE = 6.05 ms typ.
D: tCYCLE = 1.25 ms typ.
E: tCYCLE = 50 μs typ.
H: tCYCLE = 6.05 ms typ.
I:
tCYCLE = 1.25 ms typ.
J: tCYCLE = 50 μs typ.
(Without power-down function)
(Without power-down function)
(Without power-down function)
(With power-down function, SNT-4A)
(With power-down function, SNT-4A)
(With power-down function, SNT-4A)
*1. Refer to the tape drawing.
2. Packages
Table 1 Package Drawing Codes
Package Name
SOT-23-3
SNT-4A
4
Dimension
Tape
Reel
MP003-C-P-SD
PF004-A-P-SD
MP003-C-C-SD
PF004-A-C-SD
MP003-Z-R-SD
PF004-A-R-SD
Land
−
PF004-A-L-SD
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
3. Product name list
3. 1 SOT-23-3
3. 1. 1 Nch open-drain output product
Table 2
Product Name
Operating Cycle Power-down
(tCYCLE)
Function
S-5724CNBL1-M3T1U
6.05 ms typ.
Unavailable
S-5724DNBL1-M3T1U
1.25 ms typ.
Unavailable
S-5724ENBL1-M3T1U
50 μs typ.
Unavailable
Output Form
Pole
Detection
Nch open-drain
Bipolar latch
output
Nch open-drain
Bipolar latch
output
Nch open-drain
Bipolar latch
output
Output logic
Magnetic
Sensitivity
(BOP)
VOUT = "L" at S pole
3.0 mT typ.
detection
VOUT = "L" at S pole
3.0 mT typ.
detection
VOUT = "L" at S pole
3.0 mT typ.
detection
Remark Please contact our sales representatives for products other than the above.
3. 1. 2 CMOS output product
Table 3
Product Name
Operating Cycle Power-down
(tCYCLE)
Function
Output Form
Pole
Detection
S-5724CCBL1-M3T1U
6.05 ms typ.
Unavailable
CMOS output
Bipolar latch
S-5724DCBL1-M3T1U
1.25 ms typ.
Unavailable
CMOS output
Bipolar latch
S-5724ECBL1-M3T1U
50 μs typ.
Unavailable
CMOS output
Bipolar latch
Output logic
Magnetic
Sensitivity
(BOP)
VOUT = "L" at S pole
3.0 mT typ.
detection
VOUT = "L" at S pole
3.0 mT typ.
detection
VOUT = "L" at S pole
3.0 mT typ.
detection
Remark Please contact our sales representatives for products other than the above.
3. 2 SNT-4A
3. 2. 1 Nch open-drain output product
Table 4
Product Name
S-5724INBL1-I4T1U
Operating Cycle Power-down
(tCYCLE)
Function
1.25 ms typ.
Available
Output Form
Pole
Detection
Nch open-drain
Bipolar latch
output
Output logic
Magnetic
Sensitivity
(BOP)
VOUT = "L" at S pole
3.0 mT typ.
detection
Remark Please contact our sales representatives for products other than the above.
3. 2. 2 CMOS output product
Table 5
Product Name
Operating Cycle Power-down
Function
(tCYCLE)
Output Form
Pole
Detection
S-5724HCBL1-I4T1U
6.05 ms typ.
Available
CMOS output
Bipolar latch
S-5724HCBH1-I4T1U
6.05 ms typ.
Available
CMOS output
Bipolar latch
S-5724ICBL1-I4T1U
1.25 ms typ.
Available
CMOS output
Bipolar latch
S-5724ICBH1-I4T1U
1.25 ms typ.
Available
CMOS output
Bipolar latch
S-5724JCBL1-I4T1U
50 μs typ.
Available
CMOS output
Bipolar latch
S-5724JCBH1-I4T1U
50 μs typ.
Available
CMOS output
Bipolar latch
Output logic
VOUT = "L" at S pole
detection
VOUT = "H" at S pole
detection
VOUT = "L" at S pole
detection
VOUT = "H" at S pole
detection
VOUT = "L" at S pole
detection
VOUT = "H" at S pole
detection
Magnetic
Sensitivity
(BOP)
3.0 mT typ.
3.0 mT typ.
3.0 mT typ.
3.0 mT typ.
3.0 mT typ.
3.0 mT typ.
Remark Please contact our sales representatives for products other than the above.
5
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
Pin Configurations
1. SOT-23-3
Top view
1
2
Table 6
Pin No.
3
Symbol
Description
1
VSS
GND pin
2
VDD
Power supply pin
3
OUT
Output pin
Figure 5
2. SNT-4A
Table 7
Top view
1
2
4
3
Figure 6
6
Pin No.
Symbol
Description
1
VDD
Power supply pin
2
VSS
3
CE
4
OUT
GND pin
Enabling pin
"H": Enables operation
"L": Power-down
Output pin
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
Absolute Maximum Ratings
Table 8
Item
Symbol
(Ta = +25°C unless otherwise specified)
Absolute Maximum Rating
Unit
VDD
VSS − 0.3 to VSS + 7.0
Input voltage
VCE
VSS − 0.3 to VDD + 0.3
V
Output current
IOUT
±1.0
mA
VSS − 0.3 to VSS + 7.0
V
VSS − 0.3 to VDD + 0.3
430*1
300*1
V
mW
mW
Power supply voltage
Output voltage
Nch open-drain output product
VOUT
V
CMOS output product
SOT-23-3
Power
dissipation
SNT-4A
Operation ambient temperature
Topr
−40 to +85
°C
Storage temperature
Tstg
−40 to +125
°C
When mounted on board
[Mounted board]
(1) Board size:
114.3 mm × 76.2 mm × t1.6 mm
(2) Name:
JEDEC STANDARD51-7
Caution
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
600
Power Dissipation (PD) [mW]
*1.
PD
SNT-4A
200
0
Figure 7
SOT-23-3
400
0
150
100
50
Ambient Temperature (Ta) [°C]
Power Dissipation of Package (When Mounted on Board)
7
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
Electrical Characteristics
1. Product without power-down function
1. 1 S-5724CxBxx
Table 9
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Output voltage
Symbol
VDD
IDD
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
6.0
3.50
11.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.05
6.00
6.05
−
−
12.00
ms
ms
ms
−
−
−
Average value
Nch open-drain output
product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
1. 2 S-5724DxBxx
Table 10
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Output voltage
Symbol
VDD
IDD
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
8
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
26.0
3.50
45.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.05
1.20
1.25
−
−
2.50
ms
ms
ms
−
−
−
Average value
Nch open-drain output
product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
1. 3 S-5724ExBxx
Table 11
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Output voltage
Symbol
VDD
IDD
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Condition
Min.
Typ.
−
1.60
−
1.85
3.50
640.0 1000.0
Average value
Nch open-drain output
product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
Max.
V
μA
Test
Circuit
−
1
Unit
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
50
0
50
−
−
100
μs
μs
μs
−
−
−
9
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
2. Product with power-down function (SNT-4A)
2. 1 S-5724HxBxx
Table 12
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Current consumption during
power-down
Output voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
6.0
3.50
11.0
V
μA
Test
Circuit
−
1
VDD
IDD
Average value
IDD2
VCE = VSS
−
−
1
μA
6
Nch open-drain
outputproduct
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.05
6.00
6.05
ms
ms
ms
−
−
−
−
−
−
−
12.00
VDD ×
0.3
V
−
VOUT
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Enabling pin input voltage "L"
VCEL
−
Enabling pin input voltage "H"
VCEH
−
Enabling pin input current "L"
Enabling pin input current "H"
Power-down transition time
Enable transition time
Output logic update time after
inputting "H" to enabling pin
ICEL
ICEH
tOFF
tON
10
tOE
VDD = 1.85 V, VCE = 0 V
VDD = 1.85 V, VCE = 1.85 V
−
−
−
VDD ×
0.7
−1
−1
−
−
−
−
V
−
−
−
−
−
1
1
100
100
μA
μA
μs
μs
7
8
−
−
−
−
200
μs
−
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
2. 2 S-5724IxBxx
Table 13
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Current consumption during
power-down
Output voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
26.0
3.50
45.0
V
μA
Test
Circuit
−
1
VDD
IDD
Average value
IDD2
VCE = VSS
−
−
1
μA
6
Nch open-drain
outputproduct
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.05
1.20
1.25
ms
ms
ms
−
−
−
−
−
−
−
2.50
VDD ×
0.3
V
−
VOUT
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Enabling pin input voltage "L"
VCEL
−
Enabling pin input voltage "H"
VCEH
−
Enabling pin input current "L"
Enabling pin input current "H"
Power-down transition time
Enable transition time
Output logic update time after
inputting "H" to enabling pin
ICEL
ICEH
tOFF
tON
tOE
VDD = 1.85 V, VCE = 0 V
VDD = 1.85 V, VCE = 1.85 V
−
−
−
VDD ×
0.7
−1
−1
−
−
−
−
V
−
−
−
−
−
1
1
100
100
μA
μA
μs
μs
7
8
−
−
−
−
200
μs
−
11
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
2. 3 S-5724JxBxx
Table 14
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Current consumption during
power-down
Symbol
6
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
50
0
50
μs
μs
μs
−
−
−
−
−
−
−
100
VDD ×
0.3
V
−
−
−
V
−
−
−
−
−
1
1
100
100
μA
μA
μs
μs
7
8
−
−
−
200
μs
−
−
1.60
−
1.85
3.50
640.0 1000.0
VDD
IDD
Average value
IDD2
VCE = VSS
−
−
Nch open-drain
outputproduct
−
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Enabling pin input voltage "L"
VCEL
−
Enabling pin input voltage "H" VCEH
−
12
μA
Typ.
Leakage current
Enabling pin input current "L"
Enabling pin input current "H"
Power-down transition time
Enable transition time
Output logic update time after
inputting "H" to enabling pin
1
Min.
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
Output voltage
V
μA
Test
Circuit
−
1
Condition
VOUT
ICEL
ICEH
tOFF
tON
tOE
VDD = 1.85 V, VCE = 0 V
VDD = 1.85 V, VCE = 1.85 V
−
−
−
VDD ×
0.7
−1
−1
−
−
−
Max.
Unit
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
Magnetic Characteristics
Table 15
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
S pole
Release point*2
N pole
Hysteresis width*3
Symbol
BOP
BRP
BHYS
Condition
−
−
BHYS = BOP − BRP
Min.
1.4
−4.0
−
Typ.
3.0
−3.0
6.0
Max.
4.0
−1.4
−
Unit
mT
mT
mT
Test Circuit
5
5
5
*1. BOP: Operation point
BOP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied
to the S-5724 Series by the magnet (S pole) is increased (by moving the magnet closer).
VOUT retains the status until a magnetic flux density of the N pole higher than BRP is applied.
*2. BRP: Release point
BRP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied
to the S-5724 Series by the magnet (N pole) is increased (by moving the magnet closer).
VOUT retains the status until a magnetic flux density of the S pole higher than BOP is applied.
*3. BHYS: Hysteresis width
BHYS is the difference between BOP and BRP.
Remark The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss.
13
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
Test Circuits
1. Product without power-down function
A
*1
R
100 kΩ
VDD
VDD
S-5724
Series OUT
S-5724
Series OUT
VSS
VSS
A
V
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 8 Test Circuit 1
VDD
VDD
S-5724
Series OUT
VSS
A
R*1
100 kΩ
VDD
S-5724
Series OUT
V
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 12 Test Circuit 5
14
S-5724
Series OUT
VSS
V
Figure 10 Test Circuit 3
VSS
Figure 9 Test Circuit 2
A
V
Figure 11 Test Circuit 4
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
2. Product with power-down function (SNT-4A)
A
CE
VDD
R*1
100 kΩ
CE
S-5724
Series OUT
VDD
S-5724
Series OUT
VSS
VSS
A
V
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 13 Test Circuit 1
CE
Figure 14 Test Circuit 2
VDD
CE
S-5724
Series OUT
VSS
A
V
A
*1
VDD
S-5724
Series OUT
CE
V
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 17 Test Circuit 5
A
Figure 16 Test Circuit 4
R
100 kΩ
VSS
S-5724
Series OUT
VSS
V
Figure 15 Test Circuit 3
CE
VDD
VDD
R*1
100 kΩ
S-5724
Series OUT
VSS
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 18 Test Circuit 6
15
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
A
CE
VDD
S-5724
Series OUT
VSS
Figure 19 Test Circuit 7
16
A
CE
VDD
S-5724
Series OUT
VSS
Figure 20 Test Circuit 8
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
Standard Circuits
1. Product without power-down function
*1
R
100 kΩ
VDD
S-5724 Series
OUT
VSS
CIN
0.1 μF
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 21
2. Product with power-down function (SNT-4A)
*1
R
100 kΩ
VDD
VDD
or
VSS
CE S-5724 Series
OUT
VSS
CIN
0.1 μF
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 22
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
17
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
Operation
1. Direction of applied magnetic flux
The S-5724 Series detects the magnetic flux density which is vertical to the marking surface.
Figure 23 and Figure 24 show the direction in which magnetic flux is being applied.
1. 1 SOT-23-3
1. 2 SNT-4A
N
S
N
S
Marking surface
Marking surface
Figure 23
Figure 24
2. Position of Hall sensor
Figure 25 and Figure 26 show the position of Hall sensor.
The center of this Hall sensor is located in the area indicated by a circle, which is in the center of a package as
described below.
The following also shows the distance (typ. value) between the marking surface and the chip surface of a package.
2. 1 SOT-23-3
2. 2 SNT-4A
Top view
Top view
The center of Hall sensor;
in this φ 0.3 mm
1
2
1
The center of Hall sensor;
in this φ 0.3 mm
4
2
3
3
0.16 mm (typ.)
0.7 mm (typ.)
Figure 25
18
Figure 26
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
Rev.1.3_00
S-5724 Series
3. Basic operation
The S-5724 Series changes the output voltage (VOUT) according to the level of the magnetic flux density and a polarity
change (N pole or S pole) applied by a magnet.
Definition of the magnetic field is performed every operating cycle indicated in " Electrical Characteristics".
3. 1 Product with VOUT = "L" at S pole detection
When the magnetic flux density of the S pole perpendicular to the marking surface exceeds the operation point
(BOP) after the S pole of a magnet is moved closer to the marking surface of the S-5724 Series, VOUT changes from
"H" to "L". When the N pole of a magnet is moved closer to the marking surface of the S-5724 Series and the
magnetic flux density of the N pole is higher than the release point (BRP), VOUT changes from "L" to "H". In case of
BRP < B < BOP, VOUT retains the status.
Figure 27 shows the relationship between the magnetic flux density and VOUT.
VOUT
BHYS
H
L
N pole
0
BRP
BOP
S pole
Magnetic flux density (B)
Figure 27
3. 2 Product with VOUT = "H" at S pole detection
When the magnetic flux density of the S pole perpendicular to the marking surface exceeds BOP after the S pole of a
magnet is moved closer to the marking surface of the S-5724 Series, VOUT changes from "L" to "H". When the N
pole of a magnet is moved closer to the marking surface of the S-5724 Series and the magnetic flux density of the N
pole is higher than BRP, VOUT changes from "H" to "L". In case of BRP < B < BOP, VOUT retains the status.
Figure 28 shows the relationship between the magnetic flux density and VOUT.
VOUT
BHYS
H
L
N pole
BRP
0
BOP
S pole
Magnetic flux density (B)
Figure 28
19
LOW VOLTAGE OPERATION HIGH-SPEED BIPOLAR HALL EFFECT LATCH IC
S-5724 Series
Rev.1.3_00
Precautions
• If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feedthrough current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.
• Note that the IC may malfunction if the power supply voltage rapidly changes.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Large stress on this IC may affect the magnetic characteristics. Avoid large stress which is caused by bend and
distortion during mounting the IC on a board or handle after mounting.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
20
2.9±0.2
1
2
3
+0.1
0.16 -0.06
0.95±0.1
1.9±0.2
0.4±0.1
No. MP003-C-P-SD-1.1
TITLE
SOT233-C-PKG Dimensions
No.
MP003-C-P-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
4.0±0.1
2.0±0.1
+0.25
ø1.0 -0
0.23±0.1
4.0±0.1
1.4±0.2
3.2±0.2
1
2
3
Feed direction
No. MP003-C-C-SD-2.0
TITLE
SOT233-C-Carrier Tape
No.
MP003-C-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.2±0.5
Enlarged drawing in the central part
ø13±0.2
No. MP003-Z-R-SD-1.0
SOT233-C-Reel
TITLE
MP003-Z-R-SD-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
1.2±0.04
3
4
+0.05
0.08 -0.02
2
1
0.65
0.48±0.02
0.2±0.05
No. PF004-A-P-SD-6.0
TITLE
SNT-4A-A-PKG Dimensions
No.
PF004-A-P-SD-6.0
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
4.0±0.1
2.0±0.05
0.25±0.05
+0.1
1.45±0.1
2
1
3
4
ø0.5 -0
4.0±0.1
0.65±0.05
Feed direction
No. PF004-A-C-SD-2.0
TITLE
SNT-4A-A-Carrier Tape
No.
PF004-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PF004-A-R-SD-1.0
TITLE
SNT-4A-A-Reel
No.
PF004-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
1.16
2
0.52
0.35
1.
2.
0.3
1
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
0.03 mm
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
TITLE
SNT-4A-A
-Land Recommendation
PF004-A-L-SD-4.1
No.
No. PF004-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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