MC74HC245A
Octal 3-State Noninverting
Bus Transceiver
High–Performance Silicon–Gate CMOS
The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pull–up
resistors, they are compatible with LSTTL outputs.
The HC245A is a 3–state noninverting transceiver that is used for
2–way asynchronous communication between data buses. The device
has an active–low Output Enable pin, which is used to place the I/O
ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A.
•
•
•
•
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•
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MARKING
DIAGRAMS
MC74HC245AN
AWLYYWW
20
Output Drive Capability: 15 LSTTL Loads
1
Outputs Directly Interface to CMOS, NMOS, and TTL
PDIP–20
N SUFFIX
CASE 783
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Moisture Sensitivity: MSL1 for All Packages
•
• Chip Complexity: 308 FETs or 77 Equivalent Gates
HC245A
AWLYYWW
20
1
SO–20
DW SUFFIX
CASE 751D
20
1
HC245A
ALYW
TSSOP–20
DT SUFFIX
CASE 948E
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74HC245AN
PDIP–20
18 Units/Rail
MC74HC245ADW
SOIC–20
38 Units/Rail
MC74HC245ADWR2
SOIC–20 1000 Tape & Reel
MC74HC245ADT
TSSOP–20
75 Units/Rail
MC74HC245ADTR2 TSSOP–20 2500 Tape & Reel
Semiconductor Components Industries, LLC, 2001
July, 2001 – Rev. 10
1
Publication Order Number:
MC74HC245A/D
MC74HC245A
DIRECTION
1
20
VCC
A1
2
19
OUTPUT ENABLE
A2
3
18
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
A6
7
14
B5
A7
8
13
B6
A8
9
12
B7
10
11
B8
GND
Figure 1. Pin Assignment
FUNCTION TABLE
Control Inputs
Output
Enable
Direction
L
L
Data Transmitted from Bus B to Bus A
L
H
Data Transmitted from Bus A to Bus B
H
X
Buses Isolated (High–Impedance State)
Operation
X = don’t care
A1
A2
A3
A
DATA
PORT
A4
A5
A6
A7
A8
DIRECTION
OUTPUT ENABLE
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
1
19
PIN 10 = GND
PIN 20 = VCC
Figure 2. Logic Diagram
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2
B1
B2
B3
B4
B5
B6
B7
B8
B
DATA
PORT
MC74HC245A
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
Value
Unit
0.5 to 7.0
V
0.5 to VCC 0.5
V
0.5 to VCC 0.5
V
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
IIK
DC Input Diode Current
20
mA
IOK
DC Output Diode Current
35
mA
IOUT
DC Output Sink Current
35
mA
ICC
DC Supply Current per Supply Pin
75
mA
IGND
DC Ground Current per Ground Pin
75
mA
TSTG
Storage Temperature Range
65 to 150
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
C
TJ
Junction Temperature Under Bias
150
C
JA
Thermal Resistance
PDIP
SOIC
TSSOP
67
96
128
C/W
PD
Power Dissipation in Still Air at 85C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ESD Withstand Voltage
Human Body Model (Note 3.)
Machine Model (Note 4.)
Charged Device Model (Note 5.)
2000
200
1000
V
ILATCH–UP
Latch–Up Performance
Above VCC and Below GND at 85C (Note 6.)
300
mA
(Note 2.)
Level 1
Oxygen Index: 30% to 35%
UL 94 V–0 @ 0.125 in
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 20 ounce copper trace with no air flow.
2. IO absolute maximum rating must observed.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 3)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
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3
Min
Max
Unit
2.0
6.0
V
0
VCC
V
–55
+125
C
0
0
0
1000
500
400
ns
MC74HC245A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
–55 to 25C
85C
125C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = VCC – 0.1 V
|Iout| 20 A
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V
|Iout| 20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High–Level Output
Voltage
Vin = VIH
|Iout| 20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Symbol
Parameter
Test Conditions
|Iout| 2.4 mA
|Iout| 6.0 mA
|Iout| 7.8 mA
Vin = VIH
VOL
Maximum Low–Level Output
Voltage
Vin = VIL
|Iout| 20 A
|Iout| 2.4 mA
|Iout| 6.0 mA
|Iout| 7.8 mA
Vin = VIL
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
A
IOZ
Maximum Three–State Leakage
Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 A
6.0
4.0
40
160
A
7. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor
High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
VCC
V
Guaranteed Limit
–55 to 25C
85C
125C
Unit
tPLH,
tPHL
Maximum Propagation Delay,
A to B, B to A
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
55
15
13
95
70
19
16
110
80
22
19
ns
tPLZ,
tPHZ
Maximum Propagation Delay,
Direction or Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tPZL,
tPZH
Maximum Propagation Delay,
Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tTLH,
tTHL
Maximum Output Transition Time,
Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
Cin
Maximum Input Capacitance (Pin 1 or Pin 19)
—
10
10
10
pF
Cout
Maximum Three–State I/O Capacitance
(I/O in High–Impedance State)
—
15
15
15
pF
Symbol
Parameter
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
40
CPD
Power Dissipation Capacitance (Per Transceiver Channel) (Note 9.)
pF
9. Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
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4
MC74HC245A
VCC
DIRECTION
50%
GND
tf
tr
INPUT
A OR B
VCC
90%
50%
10%
GND
tPLH
OUTPUT
B OR A
VCC
OUTPUT
ENABLE
50%
GND
90%
50%
10%
A OR B
tTLH
tTHL
Figure 3. Switching Waveform
tPHZ
10%
VOL
90%
VOH
50%
HIGH
IMPEDANCE
Figure 4. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
OUTPUT
CL *
HIGH
IMPEDANCE
50%
tPZH
A OR B
DEVICE
UNDER
TEST
tPLZ
tPZL
tPHL
DEVICE
UNDER
TEST
*Includes all probe and jig capacitance
1 kΩ
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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5
MC74HC245A
A1
2
18
A2
3
17
A3
A5
OUTPUT ENABLE
B7
9
11
DIRECTION
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A
DATA
PORT
B2
4
16
A4
B1
1
19
Figure 7. Expanded Logic Diagram
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6
B8
B
DATA
PORT
MC74HC245A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0
15
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0
15
0.51
1.01
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
A
20
X 45
M
E
h
0.25
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0
7
MC74HC245A
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
20
L/2
M
T U
S
V
S
K
K1
11
B
L
J J1
–U–
PIN 1
IDENT
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
PLANE
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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8
MC74HC245A/D