IS31FL3265B
HIGH-VOLTAGE, 18-CHANNEL LED DRIVER
August 2021
GENERAL DESCRIPTION
FEATURES
The IS31FL3265B is an LED driver with 18 high voltage
(40V) constant current channels. Each channel can be
pulse width modulated (PWM) by 8 bits for smooth LED
brightness control. In addition, each channel has an 8-bit
output current control register which allows fine tuning of
the channel current for rich RGB color mixing, e.g., a
pure white color LED application. The maximum output
current of each channel is designed to be 60mA, which
can be adjusted by one 32 steps global control register.
Proprietary algorithms are used in IS31FL3265B to
minimize audible noise caused by the MLCC decoupling
capacitors. All registers can be programmed via 12MHz
SPI interface.
The IS31FL3265B can be configured to a minimum
current consumption mode by either pulling the SDB pin
low or by using the software shutdown feature.
The IS31FL3265B is available in eTSSOP-28 package. It
operates from 3.0V to 5.5V over the temperature range
of -40°C to +125°C.
APPLICATIONS
LED in white goods application
Smart home devices
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Rev.C, 08/07/2021
3V to 5.5V operating supply
Output current capability and number of outputs:
60mA × 18 outputs, tolerance voltage 40V
12MHz SPI with automatic address increment
Programmable H/L logic: 1.4V/0.4V, 2.4V/0.6V
Accurate Color Rendition
- 32 steps Global current adjust
- 8-bit Dot correction for each channel
- 8-bit PWM for each channel
Selectable PWM method (200Hz or 25kHz)
256-Step
group
blink
with
frequency
programmable from 24Hz to 10.66s and duty
cycle from 0% to 99.6%
Clock IO pin for multi-chip synchronization
Fault report (open detect/thermal roll off /thermal
shutdown)
Thermal roll-off programmable set point
SDB rising edge resets SPI interface
EMI reduction technology
- Spread spectrum
- Selectable 9 phase delay
Operating temperature range, -40°C ~ +125°C
Package: eTSSOP-28
Current accuracy (All output on)
- Bit to bit: < ±4%
- Device to device: < ±6%
1
IS31FL3265B
TYPICAL APPLICATION CIRCUIT
*Note 1
5V
28
1μF
VCC
*Note 2
0.1μF
OUT1
*Note 1
5V
*Note 1
5V
100kΩ
OUT2
5
INTB
3
SCK
2
82R
8 82R
IS31FL3265B
MISO
1
CS
26
SDB
OUT16
OUT17
100kΩ 0.1μF
*Note 3
7
VLED+ =12V
MOSI
4
Micro
Controller
OUT3
6 200R
25
ISET
OUT18
GND
CLKIO
21 200R
22 82R
23 82R
RISET
20kΩ
24
Figure 1
27
Typical Application Circuit
Note 1: VIH is the high level voltage for IS31FL3265B’s INTB, which is usually same as VCC pin and VCC of Micro Controller, e.g. if VCC of
Micro Controller is 3.3V, VCC(IS31FL3265B)=VIH=3.3V, if VCC of Micro Controller is 5V, VCC(IS31FL3265B)=VIH=5V, but VCC(IS31FL3265B)
should not be lower than 3V.
Note 2: These resistors are for offloading the thermal dissipation (I2R) away from the IS31FL3265B.
Note 3: The maximum global output current is set by external resistor, RISET. Please refer to the application information in RISET section.
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2
IS31FL3265B
TYPICAL APPLICATION CIRCUIT (CONTINUED)
CS8
CS2
Micro
Controller
MOSI
MOSI
MOSI
SCK
SCK
SCK
CS1
MISO
SDB
CS2
CS
MISO
MISO
SDB
SDB
MOSI
MOSI
SCK
SCK
CS3
CS
MISO
MISO
SDB
SDB
MOSI
MOSI
SCK
SCK
CS4
CS
MISO
MISO
SDB
SDB
MOSI
SCK
CS
MISO
SDB
100kΩ
CLKIO
CLKIO
Master
CLKIO
MOSI
SCK
CS5
MISO
SDB
CLKIO
Slave 1
CLKIO
MOSI
MOSI
SCK
SCK
CS6
CS
MISO
MISO
SDB
SDB
Slave 4
Figure 2
CLKIO
Slave 2
CLKIO
MOSI
MOSI
SCK
SCK
CS7
CS
MISO
MISO
SDB
SDB
Slave 5
Slave 3
CLKIO
MOSI
MOSI
SCK
SCK
CS8
CS
MISO
MISO
SDB
SDB
Slave 6
MOSI
SCK
CS
MISO
SDB
Slave 7
Typical Application Circuit (Eight Device Synchronization)
Note 4: One system should contain only one master, all slave parts should be configured as slave mode before the master is configured as
master mode. Master or slave mode is specified by the Configuration Register. The master will output a master clock (CLKIO), and all the other
devices configured as slaves will synchronize their CLKIO inputs to the master clock.
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IS31FL3265B
PIN CONFIGURATION
Package
Pin Configuration (Top View)
eTSSOP-28
PIN DESCRIPTION
No.
Pin
Description
1
CS
CS of SPI.
2
MISO
MISO of SPI.
3
MOSI
MOSI of SPI.
4
SCK
SPI clock.
5
INTB
Interrupt output pin. Register 14h can set the function of
the INTB pin and active low when the interrupt event
happens. Can be NC (float) if interrupt function is not
used.
6~23
OUT1~OUT18
Output LED current sink channels 1~18.
24
GND
GND pin for control logic.
25
ISET
Input terminal used to connect an external resistor. This
regulates the global output current.
26
SDB
Shutdown the chip when pulled low.
27
CLKIO
Cascade connection pin.
28
VCC
Power supply.
Thermal Pad
Need to connect to GND.
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4
IS31FL3265B
ORDERING INFORMATION
Automotive Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS31FL3265B-ZLS4-TR
eTSSOP-28, Lead-free
2500
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products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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5
IS31FL3265B
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at CS, SCK, MISO, MOSI, CLKIO, SDB, INTB
Voltage at OUT1 to OUT18
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Package thermal resistance, junction to ambient (4 layer standard
test PCB based on JESD 51-2A), θJA
Package thermal resistance, junction to thermal PAD (4 layer
standard test PCB based on JESD 51-2A), θJP
ESD (HBM)
ESD (CDM)
-0.3V ~ 6.0V
-0.3V ~ VCC+0.3V
-0.3V ~ +40V
+150°C
-65°C ~ +150°C
-40°C ~ +150°C
33.8°C/W
11.08°C/W
±2kV
±750V
Note 5: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VCC= 5V, TA= TJ = -40°C ~ +125°C, Typical values are at TJ = 25°C, unless otherwise noted.
Symbol
VCC
Parameter
Condition
Supply voltage
RISET= 6.8kΩ, GCC= 0x20, Scaling= 0xFF,
PWM= 0xFF, VOUT= 0.8V (Note 6)
Output current
RISET= 20kΩ, GCC= 0x20, Scaling= 0xFF,
PWM= 0xFF
ΔIMAT
IOUT mismatch (bit to bit)
ΔIOUT
VHR
ICC
ISD
Typ.
3
Maximum output current
IOUT
Min.
Max. Unit
5.5
60
mA
20.4
21.8
mA
RISET= 20kΩ, GCC= 0x20, Scaling= 0xFF,
PWM= 0xFF (Note 7)
±2
±6
%
IOUT accuracy (device to
device)
RISET= 20kΩ, GCC= 0x20, Scaling= 0xFF,
PWM= 0xFF (Note 8)
±2
±6
%
Headroom voltage
RISET= 20kΩ, GCC= 0x20, Scaling= 0xFF,
PWM= 0xFF
0.3
0.5
V
RISET= 20kΩ, GCC= 0xFF, Scaling= 0xFF,
PWM= 0
7.5
9
mA
VCC= 3.6V, RISET= 20kΩ, GCC= 0xFF,
Scaling= 0xFF, PWM= 0
7.2
8.5
mA
RISET= 20kΩ, VSDB= 0V or software
shutdown
4
20
μA
VCC= 3.6V, RISET= 20kΩ, VSDB= 0V or
software shutdown
1
12
μA
1.02
V
Quiescent power supply
current
Shutdown current
19
V
VISET
ISET voltage
RISET= 20kΩ, GCC= 0x20, Scaling= 0xFF,
PWM= 0xFF
0.98
1.0
VOD
OUTx pin open detect
threshold
RISET=20kΩ, GCC= 0x20, Scaling= 0xFF,
PWM=0xFF, measured at OUTx
100
150
IOZ
Output leakage current
VSDB= 0V or software shutdown,
VOUT= 40V
fOUT
PWM frequency of output
Frequency setting= 25kHz
TSD
Thermal shutdown
165
°C
TSD_HYS
Thermal shutdown
hysteresis
20
°C
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22
25
mV
1
μA
28
kHz
6
IS31FL3265B
ELECTRICAL CHARACTERISTICS (CONTINUED)
VCC= 5V, TA= TJ = -40°C ~ +125°C, Typical values are at TJ = 25°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
0.4
V
Logic Electrical Characteristics (SCK, MISO, MOSI, CS, SDB, CLKIO)
VIL
Logic “0” input voltage
VCC= 2.7V~5.5V, LGC=0
VIH
Logic “1” input voltage
VCC= 2.7V~5.5V, LGC=0
VIL
Logic “0” input voltage
VCC= 2.7V~5.5V, LGC=1
VIH
Logic “1” input voltage
VCC= 2.7V~5.5V, LGC=1
VOH
H level MISO and CLKIO pin
IOH= -8mA
output voltage
VCC-0.4V
VCC
V
VOL
L level MISO and CLKIO pin
IOL= 8mA
output voltage
0
0.4
V
1.4
V
0.6
2.4
V
V
IIL
Logic “0” input current
VINPUT= 0V (Note 9)
5
nA
IIH
Logic “1” input current
VINPUT= VCC (Note 9)
5
nA
DIGITAL INPUT SPI SWITCHING CHARACTERISTICS (NOTE 9)
Symbol
fC
Parameter
Clock frequency
Min.
Typ.
Max.
Units
12
MHz
tSLCH
CS active set-up time
34
tSHCH
CS not active set-up time
17
ns
tSHSL
CS detect time
167
ns
tCHSH
CS active hold time
34
ns
tCHSL
CS not active hold time
17
ns
tCH
Clock high time
34
ns
tCL
Clock low time
34
ns
tCLCH
Clock rise time
ns
9
9
ns
tCHCL
Clock fall time
tDVCH
Data in set-up time
7
ns
tCHDX
Data in hold time
9
ns
tSHQZ
Output disable time
34
ns
tCLQV
Clock low to output valid
39
ns
tCLQX
Output hold time
tQLQH
Output rise time
17
ns
tQLQH
Output fall time
17
ns
0
ns
ns
Note 6: The recommended minimum value of RISET is 6.8kΩ.
Note 7: IOUT mismatch (bit to bit) is calculated:
I MAT
I OUTn (n 1 ~ 18)
1 100%
I OUT1 I OUT 2 ... I OUT18
18
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IS31FL3265B
Note 8: IOUT accuracy (device to device) is calculated:
I OUT
I OUT 1 I OUT 2 ... I OUT18
I OUT ( IDEAL) )
(
18
100%
I OUT ( IDEAL)
Where IOUT(IDEAL)= 20.4mA (RISET= 20kΩ, GCC= 0x20, Scaling= 0xFF, PWM= 0xFF).
Note 9: Guaranteed by design.
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IS31FL3265B
DETAILED DESCRIPTION
SPI INTERFACE
ADDRESS AUTO INCREMENT
IS31FL3265B uses a SPI protocol to control the chip’s
function with four wires: CS, SCK, MOSI and MISO. SPI
transfer starts form CS pin from high to low controlled
by Master (Microcontroller), and IS31FL3265B latches
data when clock rising.
To write multiple bytes of data into IS31FL3265B, load
the address of the data register that the first data byte
is intended for. During the 8th rising edge of receiving
the data byte, the internal address pointer will
increment by one. The next data byte sent to
IS31FL3265B will be placed in the new address, and
so on. The auto increment of the address will continue
as long as data continues to be written to
IS31FL3265B (Figure 6).
SPI data format is 8-bit length. The register byte must
be sent first, and is followed by register address byte
then the register data. If the R/W bit is “0”, it will be write
operation and Master (Micro-controller) can write the
register data into the register.
The maximum SCK
IS31FL3265B is 12MHz.
frequency
supported
All of the registers can be read (Table 1).
To read the registers, the D7 of the register byte needs
to be set to “1”. If read one register, as shown in Figure
7, read the MISO data after sending the command
byte and register address. If read more registers, as
shown in Figure 8, the register address will auto
increase during the 8th rising edge of receiving the last
bit of the previous register data.
Figure 3
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in
READING OPERATION
SPI Input Timing
9
IS31FL3265B
Figure 4
MOSI
1
2
3
4
5
A7 A6 A5 A4 A3
SPI Input Timing
6
7
8
A2 A1 A0
1
2
D7 D6
3
4
5
6
7
D5 D4 D3 D2 D1
8
D0
SCK
Register Address Byte
CS
Figure 5
MOSI
Data Byte
SPI writing to IS31FL3265B (Typical)
1
2
3
4
5
A7 A6 A5 A4 A3
6
7
8
A2 A1 A0
1
2
D7 D6
3
4
5
6
7
D5 D4 D3 D2 D1
8
D0
SCK
Register Address Byte
CS
MOSI
1
2
3
4
5
A7 A6 A5 A4 A3
6
7
8
A2 A1 A0
Data 1 Byte
1
2
D7 D6
3
4
5
6
7
D5 D4 D3 D2 D1
8
D0
SCK
Data (n-1) Byte
CS
Figure 6
Data n Byte
SPI writing to IS31FL3265B (Automatic address increment)
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IS31FL3265B
1
2
D7 D6
MISO
MOSI
1
2
3
4
5
A7 A6 A5 A4 A3
6
7
8
A2 A1 A0
1
2
3
4
5
6
7
D5 D4 D3 D2 D1
3
4
5
6
7
8
D0
8
SCK
Register Address Byte
CS
Figure 7
Data Byte
SPI Reading From IS31FL3265B (Typical)
1
2
D7 D6
MISO
MOSI
1
2
3
4
5
A7 A6 A5 A4 A3
6
7
8
A2 A1 A0
1
2
3
4
5
6
7
D5 D4 D3 D2 D1
3
4
5
6
7
8
D0
8
SCK
Register Address Byte
CS
MISO
MOSI
1
2
D7 D6
1
2
3
4
5
6
7
D5 D4 D3 D2 D1
3
4
5
6
7
Data 1 Byte
1
2
8
D0 D7 D6
8
1
2
3
4
5
6
7
D5 D4 D3 D2 D1
3
4
5
6
7
8
D0
8
SCK
Data (n-1) Byte
CS
Figure 8
Data n Byte
SPI Reading From IS31FL3265B (Automatic Address Increment)
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IS31FL3265B
REGISTER DEFINITIONS
Table 1 Register Function
Address
Name
Function
Table
Default
2
0000 0000
3
0011 1111
Control each channel’s DC current
4
1111 1111
Open Detect Enable Register
Open detect enable
5
0000 0011
LED Open Status Register
(Read Only)
Open information
6
0000 0000
Write
Read
00h
80h
Configuration Register
01h
81h
Global Current Control Register Control Global DC current
02h~13h
Power control register
82h~93h Scaling Register
14h
94h
15h~17h
95h~97h
18h
98h
Temperature Sensor Register
Temperature information
7
0000 0000
19h
99h
Spread Spectrum Register
Spread spectrum control register
8
0000 0000
Disable PWM function
9
0000 0000
Phase Delay and Clock Phase
10
0000 0000
1Ah~1Ch 9Ah~9Ch DC PWM Register
1Dh~1Eh 9Dh~9Eh
Phase Delay and Clock Phase
Register
1Fh~30h
9Fh~B0h PWM Register
Channel [18:1] PWM register byte
11
0000 0000
31h~33h
B1h~B3h Blinking Enable Register
Enable Blinking state for each LED
12
0000 0000
34h
B4h
Blinking Frequency Register
Blinking frequency setting
13
0000 0000
35h
B5h
Blinking Duty Cycle Register
Blinking duty cycle setting
14
0000 0000
36h
B6h
Scaling Update Register
Update the scaling registers
-
0000 0000
37h
B7h
Update Register
Update the PWM and blinking
registers
-
0000 0000
3Fh
BFh
Reset Register
Reset all registers
-
0000 0000
Table 2
00h
Bit
D7
Name
-
Default
0
Configuration Register
D6
D5
D4 D3
LGC CM PFS
0
0
0
D2:D1
D0
-
SYNC
SSD
0
00
0
The Configuration Register sets high/low logic, current
multiplier, PWM frequency, synchronization mode and
software shutdown mode for the IS31FL3265B.
When SSD bit is “0”, the IS31FL3265B is in software
shutdown mode. For normal operation the SSD bit
should be set to “1”.
SYNC bits configure the device into Master or Slave
mode. The CLKIO pin has an internal weak pulldown
resistor. When the SYNC bits are “10”, the CLKIO pin
is configured as the master and will output a clock
signal for distribution to the slave configured devices.
To be configured as a slave device and accept an
external clock input the slave device’s SYNC bits must
be set to “11”. The CLKIO clock is only used
synchronizing the blink function, and CLKIO frequency
is same as blinking setting from 24Hz to 10.66s. There
should only be one master and all other CLKIO
connected devices should first be configured in slave
mode before the master is configured as master mode.
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The PFS bit sets the operating PWM frequency, default
PWM frequency is 25kHz, when PFS is set to “1”, the
PWM frequency will change to 200Hz.
CM bit is a current multiplier of all output’s current.
When CM=’0’, IOUT(MAX) follow the formula below or
refer to RISET section in Application Information.
I OUT
( MAX )
x
V ISET
R ISET
(1)
x = 408, VISET = 1V.
When CM= “1”, the output current will become 1/8 of
above setting, which is:
I OUT
( MAX )
x V ISET
8 R ISET
(1)
x = 408, VISET = 1V.
For applications of IOUT(MAX)=6mA~60mA, CM should
be set to “0”.
For applications of IOUT(MAX)=0~7.5mA, recommend to
set CM to “1” to ensure good ΔIMAT and ΔIOUT.
When LGC bit is set to “1”, the high/low logic will
change to 2.4V/0.6V.
12
IS31FL3265B
SSD
0
1
Software Shutdown Control
Software shutdown
Normal operation
SYNC
00/11
10
Table 4
11
Master or Slave Mode
no function, CLKIO pull-low
Master and CLKIO has square wave output,
CLKIO frequency is same as blinking
frequency
Slave and CLKIO is clock input
PFS
0
1
PWM Frequency Setting
25kHz
200Hz
CM
0
1
Current Multiplier
6~60mA
1~10mA
LGC
0
1
H/L Logic
1.4V/0.4V
2.4V/0.6V
Table 3
01h
Bit
D7:D6
D5:D0
Name
-
GCC
Default
00
11 1111
GCC and SL control the IOUT as shown in Formula (2).
)
( MAX
GCC
SL
32
256
(2)
If GCC ≤ 31(’01 1111’),
GCC
5
D [n] 2 n
(3)
n0
If GCC ≥ 32(’10 0000’), GCC=32.
Where IOUT(MAX) is the maximum output current decided
by RISET (Check RISET section for more information)
The IOUT of each channel is set by the SL bits of LED
Scaling Register (02h~13h). Please refer to the detail
information in Table 5.
If GCC=0x05, SL=0xFF, GCC ≤ 31 so GCC=5,
I OUT I OUT
( MAX )
5
255
32 256
(2)
If GCC=0x2F, SL=0xFF, GCC ≥ 32 so GCC=32,
I OUT I OUT
( MAX )
255
256
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Scaling Register
Bit
D7:D0
Name
SL[7:0]
Default
1111 1111
Each output has 8 bits to modulate DC current in 256
steps.
The value of the SL Registers scales the IOUT current
of each output channel.
IOUT computed by Formula (2):
I OUT I OUT
Global Current Control Register
I OUT I OUT
02h~13h
( MAX )
GCC
SL
32
256
(2)
Where IOUT(MAX) is the maximum output current set by
RISET. GCC (D5~D0) are the global current setting bits.
SL D7~D0=0xFF is the default value, resulting in no
LED current, for LEDs to function need to program
these bits to a value from 0x01 to 0xFF.
Scaling Registers 02h~13h must be updated by writing
to the Scaling Update Register 36h. For DC mode
(PWM disabled), each register will be updated
immediately when it is written. For PWM mode, each
register will be updated at the PWM falling edge,
except not on the first PWM cycle.
Table 5
14h
Open Detect Enable Register
Bit
D7:D2
D1
D0
Name
-
ODF
ODE
Default
00000
1
1
ODE enables Open LED detection and stores this
open information in LED Open status registers
15h~17h. The open information will continue updating
until detection is disabled by writing ‘0’ to ODE. Writing
a ‘1’ to ODF bit enables reporting of the open
information on the INTB pin. When ODF is ‘1’, any
detected open LED condition on OUT1~OUT18 will
cause the INTB pin to go logic low.
ODE
0
1
Open Detect Enable
Detect disable
Detect enable
ODF
0
1
Open Report Enable
Report disable
Report enable
(2)
13
IS31FL3265B
Table 6-1 15h
LED Open Status Register 1
Bit
D7
D6:D4
D3
D2:D0
Name
-
OP[6:4]
-
OP[3:1]
Default
0
000
0
000
Table 6-2 16h
LED Open Status Register 2
Bit
D7
D6:D4
D3
D2:D0
Name
-
OP[12:10]
-
OP[9:7]
Default
0
000
0
000
Table 6-3 17h
LED Open Status Register 3
Bit
D7
D6:D4
D3
D2:D0
Name
-
OP[18:16]
-
OP[15:13]
Default
0
000
0
000
Open status registers 15~17h are updated if there is
an open LED condition and if bit ODE of register 14h
was set to “1”. Register 15~17h will be cleared upon
reading the register.
OPx
0
1
Table 7
Bit
18h
D7
0
00
01
10
11
TS
00
01
10
11
TSDF
0
1
Thermal Shutdown Flag
No thermal shutdown happens
Thermal shutdown happens
TRDE
0
Thermal roll off Detect Enable
Disable the thermal roll off detect,
thermal roll off information will not store
in TF
Enable the thermal roll off detect,
thermal roll off information stored in TF
1
TSDDE
0
Thermal Shutdown Detect Enable
Disable thermal shutdown detect,
thermal shutdown information will not be
stored in TSDF
Enable thermal shutdown detect thermal
shutdown information will be stored in
TSDF
1
Table 8
Bit
D7:D5
D4
D3:D2
D1:D0
Temperature Status Register
Name
-
SSP
RNG
CLT
Default
000
0
00
00
D6
D5
0
0
D4 D3:D2 D1:D0
TF TROF
0
00
TS
19h
Spread Spectrum Register
This register enable the spread spectrum function,
adjust the cycle time and range.
00
This register stores the temperature point of the IC.
When TF=1, the IC die temperature has exceeded the
temperature point. When thermal shutdown happens,
the TSDF will set to “1” to flag the thermal shutdown
has occurred.
Write 18h with C0h to enable read back if die
temperature has or has not exceeded the set point.
TROF
Temperature Flag
Set point not reached
Reached the set point
Open Information of OUT18:OUT1
No LED open detected
LED open detected
Name TSDDE TRDE TSDF
Default
TF
0
1
Percentage of output current before
thermal shutdown happens
100%
75%
55%
30%
SSP
0
1
Spread Spectrum Enable
Disable
Enable
CLT
00
01
10
11
Spread Spectrum Cycle Time
1980μs
1200μs
820μs
660μs
RNG
00
01
10
11
Spread Spectrum Range
±5%
±15%
±24%
±34%
Temperature Point, Thermal roll-off start
point
140°C
120°C
100°C
90°C
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Rev.C, 08/07/2021
14
IS31FL3265B
Table 9-1 1Ah
DC PWM Register (PWM=256/256)
Table 11
1Fh~30h
PWM Register
Bit
D7
D6:D4
D3
D2:D0
Name
-
DP[6:4]
-
DP[3:1]
Name
PWM
Default
0
000
0
000
Default
0000 0000
Table 9-2 1Bh
DC PWM Register (PWM=256/256)
Bit
D7
D6:D4
D3
D2:D0
Name
-
DP[12:10]
-
DP[9:7]
Default
0
000
0
000
Table 9-3 1Ch
Bit
Each OUTx has 1 byte to modulate the PWM duty
cycle in 256 steps.
The value of the PWM Registers decides the average
current of each OUTx LED noted ILED.
ILED computed by Formula (4):
DC PWM Register (PWM=256/256)
Bit
D7
D6:D4
D3
D2:D0
Name
-
DP[18:16]
-
DP[15:13]
Default
0
000
0
000
D7:D0
I LED
PWM
I OUT
256
(4)
7
n 0
When DPx bit is set to 1, the associated OUTx PWM
will become 256/256, the OUTx current is a DC value,
not PWM controlled.
DPx
0
1
DC PWM command of OUT18:OUT1
PWM decided by Registers 1Fh-30h
no PWM, DC output
Table 10-1 1Dh
Register 1
Bit
Phase Delay and Clock Phase
I OUT I OUT
D6:D4
D3:D1
D0
Name
-
Default
0
PS[3:1]
-
PDE
000
000
0
Table 10-2 1Eh Phase Delay and Clock Phase
Register 2
Bit
D7
D6:D4
D3
D2:D0
Name
-
PS[9:7]
-
PS[6:4]
Default
0
000
0
000
IS31FL3265B features a 9 phase delay function
enabled by PDE bit.
PDE
0
1
Phase Delay Enable
Phase delay disable
Phase delay enable
PSx
0
Phase select
OUTx x2 Phase delay 0D， PS1 is for OUT1
&OUT2, PS2 is for OUT3 & OUT4…
OUTx x2 Phase delay 180D， PS1 is for
OUT1 &OUT2, PS2 is for OUT3 & OUT4…
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Rev.C, 08/07/2021
( MAX
(5)
GCC
SL
)
32
256
(2)
Where IOUT(MAX) is the maximum output current decided
by RISET, GCC is the global current setting(GCC), and
SL is the 8-bit scaling of each output.
For example, if the data in OUT1 PWM register is
“0000 0100”, then the associated PWM is the fourth
step (4/256).
Table 12-1
D7
1
PWM D[n] 2 n
31h
Blinking Enable Register
Bit
D7
D6:D4
D3
D2:D0
Name
-
BP[6:4]
-
BP[3:1]
Default
0
000
0
000
Table 12-2
32h
Blinking Enable Register
Bit
D7
D6:D4
D3
D2:D0
Name
-
BP[12:10]
-
BP[9:7]
Default
0
000
0
000
Table 12-3
33h
Blinking Enable Register
Bit
D7
D6:D4
D3
D2:D0
Name
-
BP[18:16]
-
BP[15:13]
Default
0
000
0
000
The Blinking Enable Registers store the Blinking mode
enable bit of each OUTx channel. The data sent to the
registers will be stored in temporary registers only, a
write operation of “0000 0000” value to the Update
Blinking Register (37h) is required to update it.
BPx
0
1
Blinking Enable Bit
PWM Mode
Blinking Mode
15
IS31FL3265B
Table 13
34h
Bit
Blinking Frequency Register
D7:D0
Name
BLF
Default
0000 0000
The Blinking Frequency Register stores the blinking
frequency of the outputs. The blinking period is
controlled through 256 linear steps from 00h (41 ms,
frequency 24 Hz) to FFh (10.66 s). Blinking frequency
is computed by:
Blinking frequency (Hz) = 24/(BLF[7:0] + 1)
The data sent to the Blinking Frequency Register will
be stored in temporary bits, a write operation of “0000
0000” value to the Update Register (37h) is required to
update it.
Table 14
35h
Blinking Duty Cycle Register
Bit
D7:D0
Name
BLD
Default
0000 0000
The Blinking Duty Cycle Register stores blinking duty
cycle information (ON/OFF ratio in %). The blinking
duty cycle can be linearly programmed from 0%
(BLD=0x00) to 99.6% (BLD=0xFF). Blinking duty cycle
computed by:
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Rev.C, 08/07/2021
Blinking duty cycle = BLD[7:0] / 256
The data sent to the Blinking Duty Cycle Register will
be stored in temporary bits, a write operation of “0000
0000” value to the Update Register (37h) is required to
update it.
36h Scaling Update Register
A Write of 00h to the Scaling Update Register is
required to update the Scaling Registers (02h~13h)
values.
37h Update Register
A Write of 00h to Update Register is required to update
the PWM Registers and Blinking Frequency Register/
Blinking Duty Cycle Register (1Fh~30h, 34h~35h)
values.
3Fh
Reset Register
A write of 0xAE to the Reset Register will reset all the
IS31FL3265B registers to their default values. On
initial power-up, the IS31FL3265B registers are reset
to their default values for a blank display. A write of “1”
to the SSD bit in the Configuration Register 00h is
required to enable the IS31FL3265B since the SSD
default value is “0” or software shutdown.
16
IS31FL3265B
APPLICATION INFORMATION
RISET
of
The
maximum
output
current
IOUT(MAX)
OUT1~OUT18 can be adjusted by external resistor,
RISET, as described in Formula (1).
I OUT
( MAX )
V
x ISET
R ISET
(1)
x = 408, VISET = 1V.
Registers can also be referred to as white balance
registers.
PWM CONTROL
The 18 PWM Registers (1Fh~30h) can modulate the
average LED brightness of each 18 channels with 256
steps. For example, if the data in OUT1 PWM register
is “0000 0100”, then the associated PWM is the fourth
step (4/256).
The max IOUT result is based on register setting as
below (CM is D5 of Configuration Register (00h)):
Continuously updating new values to the PWM
registers will modulate the brightness of the LEDs to
achieve a breathing effect.
When CM= “0”, GCC= 0x20, Scaling= 0xFF, PWM=
0xFF
PWM FREQUENCY SELECT
The recommended minimum value of RISET is 6.8kΩ.
When RISET=20kΩ, IOUT(MAX)=20.4mA.
When RISET=6.8kΩ, IOUT(MAX)=60mA.
When CM= “1”, GCC= 0x20, Scaling= 0xFF, PWM=
0xFF
The output current will become 1/8 of above setting,
which is:
I OUT
( MAX )
x V ISET
8 R ISET
(1)
x = 408, VISET = 1V.
When RISET=20kΩ, IOUT(MAX)=2.55mA.
The IS31FL3265B output channels operate with a
default 8 bit PWM resolution and a PWM frequency of
200Hz or 25kHz (register selectable). Because all the
OUTx channels are synchronized, the DC power
supply mau experience large instantaneous current
surges when the OUTx channels turn ON. These
current surges will generate an AC ripple on the power
supply which cause stress to the decoupling capacitors.
When the AC ripple is applied to a monolithic ceramic
capacitor chip (MLCC) it will expand and contract
causing the PCB to flex and generate audible hum in
the PWM frequency range. To avoid this hum, there
are many countermeasures, such as selecting the
capacitor type and value which will not cause the PCB
to flex and contract.
RISET should be close to pin 25 and the ground side
should connected to a nearby GND plane.
An additional option for avoiding audible hum is to set
the
IS31FL3265B’s
output
PWM
frequency
above/below the audible range. The Control Register
(00h) can be used to set the switching frequency to
200Hz or 25kHz, to avoid the audible range.
CURRENT SETTING
OPEN DETECT FUNCTION
The maximum output current is set by the external
resistor RISET. The current of each output can be
adjusted with the SL 8 bits of LED Scaling Register
(02h~13h).
IS31FL3265B has open detect bit for each LED.
When RISET=6.8kΩ, IOUT(MAX)=7.5mA.
Some applications may require the IOUT of each
channel to be adjusted independently. For example, if
OUT1 drives 1 LED and OUT2 drives 2 parallel LEDs,
and they should have the same average current of
10mA, we can set RISET=20kΩ for IOUT of 20.4mA, and
configure the following registers 01h=0x20 (GCC= 32),
02h=0x80 (Scaling OUT1), and 03h=0xFF (Scaling
OUT2). The result is OUT1 sinks 10mA and OUT2
sinks 20.4mA which will be shared by the two LEDs in
parallel (10mA each).
Another example, for an RGB LED, OUT1 is Red,
OUT2 is Green and OUT 3 is Blue, with the same GCC
(01h) SL (02h~13h) bits and PWM value, the LED may
looks a pinkish, or not so white. In this case, the SL
bits can be used to adjust the current of the RGB
IOUTx to create a pure white color. These Scaling
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Rev.C, 08/07/2021
By setting the ODE bit of Open Detect Enable Register
(14h) from “0” to “1” (store open information), the LED
Open Register will store the open LED information so
the MCU can read LED status from registers 95h~97h.
The open information will continue updating until ODE
is set to ‘0’. The ODF bit can be set to “1” to enable
reporting of open LED information on the INTB pin.
When ODF is ‘0’, the open LED information will not be
reported on the INTB pin. When ODF is ‘1’, any OUTx
with a detected open LED will cause the INTB pin to go
logic LOW.
The Global Current Control Register (01h) needs to set
to a value in the range of 0x0F~0x3F in order to
correctly detect an open LED.
SPREAD SPECTRUM FUNCTION
PWM current switching of LED outputs can be
particularly troublesome Electromagnetic Interference
(EMI) is of concern. To optimize EMI performance, the
17
IS31FL3265B
IS31FL3265B spread spectrum function can be
enabled. By setting the RNG bit of the Spread
Spectrum Register (19h), a Spread Spectrum range
can be selected from ±5% /±15% /±24% /±34%.
Spread spectrum can spread the total electromagnetic
emitting energy into a wider frequency range that
significantly lowers the peak radiated energy. With
spread spectrum enabled and proper PCB layout, it is
possible to pass EMI tests which were previously
difficult to pass.
Thermal Consideration
The over temperature of the chip may result in
deterioration of the properties of the chip.
The maximum IC junction temperature should be
restricted to 150°C under normal operating conditions.
The maximum power dissipation can be calculated
using the following equation:
p D ( MAX )
SHUTDOWN MODE
T J (max) T A
JA
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
Where PD(MAX) is the maximum allowable power
dissipation, TJ(MAX) is the maximum allowable junction
temperature, TA is ambient temperature of the device
Software Shutdown
For example, when TA=25°C
By setting the SSD bit of the Control Register (00h) to
“0”, the IS31FL3265B will operate in software
shutdown mode. When the IS31FL3265B is in
software shutdown, all current sources are switched off,
so the LEDs are OFF but all registers remain
accessible. Typical current consumption is 3μA
(VCC=5V).
PD ( MAX )
Figure 9, shows the power derating of the
IS31FL3265B on a JEDEC boards (in accordance with
JESD 51-5 and JESD 51-7) standing in still air.
4
Hardware Shutdown
The IS31FL3265B exits shutdown when the SDB pin is
pulled high. The rising edge of SDB pin will reset the
SPI module, but all the register information is retained.
During hardware shutdown the registers are
accessible.
If the VCC supply drops below 1.75V but remains
above 0.1V while the SDB pin is pulled low, all
Function Registers must be re-initialized before the
SDB pin is pulled high.
LAYOUT
The IS31FL3265B consumes lots of power so proper
PCB layout will help improve itsreliability. Below are
basic PCB layout factors to consider.
Power Supply Lines
When designing the PCB layout, the first step to
consider is the power supply traces and GND
connection. High current traces, digital and analog
supply traces and GND traces should be separated to
avoid noise contamination from the switching digital
block from affecting the analog block.
At least one 0.1μF capacitor, if possible in parallel with
a 1μF capacitor is recommended to connect from the
power supply pin of the chip directly to ground. To be
effective, these capacitors must be placed close to the
chip and the capacitor ground should be well
connected to the GND plane.
Lumissil Microsystems – www.lumissil.com
Rev.C, 08/07/2021
3.5
Power Dissipation (W)
The IS31FL3265B enters hardware shutdown when
the SDB pin is pulled low. All current sources are
disabled during hardware shutdown, typical the current
consumption is 3μA (VCC=5V).
150 C 25 C
3.7W
33 .8C / W
eTSSOP-28
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
120
140 150
Temperature (°C)
Figure 9
Dissipation Curve
The thermal pad of IS31FL3265B should connect to a
large copper GND net (preferably double sided PCB).
Use 9 or 16 vias to connect the GND copper area
directly under the IC thermal pad with a copper pad on
the opposite layer (2 layer PCB). The grounded copper
area should be as large area as possible to help
distribute the thermal energy from the IS31FL3265B.
Current Rating Example
For RISET=20kΩ (IOUT(MAX)=20.4mA), the current rating
for each net is as follows:
• VCC pin maximum current (ICC) is 10mA when
VCC=5V, the total OUTx current can as much as
20.4mA×18=367.2mA, the recommended trace width
for VCC pin: 0.20mm~0.3mm, recommend trace width
for VLED+ net: 0.30mm~0.5mm,
18
IS31FL3265B
• Output pins=20.4mA, recommend trace width is
0.2mm~0.254mm
• All other pins
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