IS32LT3129A
TRIPLE CHANNEL LINEAR LED DRIVER
WITH I2C INTERFACE AND FADE ON/OFF
February 2020
GENERAL DESCRIPTION
FEATURES
The IS32LT3129A is a programmable triple channel
linear current regulator; two channels of up to 150mA
each for LED lighting and a single channel of up to
30mA for illuminating switches. The device operates
as a fully configurable theatrical dimming LED driver;
External resistors will program the current levels as
well as the LED fade ON/OFF ramp rate.
In additional, the I2C interface supports writing/reading
function for MCU to select switch type (momentary
contact or latched), individually configure the output
current levels and fade on/off ramp rate, or get the
state of device and the fault flag of open/short circuit
and thermal shutdown.
An integrated debounce and latch circuit on the
channel enable pin (EN1/2) is enabled when the
device is configured for a momentary contact switch
interface. The other option is to configure the EN pins
to accept a static level signal for operation with latched
switches. If configured for Internal-PWM-Dimming
mode, the integrated PWM source will be triggered by
an I2C command. This enables LED dimming without
the need for an external PWM input. The I2C
command input has a higher priority and will override
EN inputs. See Figure 63~69 for the details.
The device integrates a 63 step fade ON/OFF
algorithm (Gamma correction) which causes the output
LED brightness to gradually ramp up to the full source
value after the EN1/2 pins are triggered or send I2C
commands
(when
configured
for
Internal-PWM-Dimming mode). The same controller
causes the LED brightness to gradually ramp down to
zero if the EN1/2 pins are triggered or send I2C
commands
(when
configured
for
Internal-PWM-Dimming mode) while the output
channel is ON. The fade ramp can be interrupted
mid-cycle before completion of the ramp cycle.
The IS32LT3129A is targeted at the automotive market
with end applications to include map and dome lighting
as well as exterior accent lighting. For 12V automotive
applications the low dropout driver can support 1 to 3
LEDs per channel. It is offered in a small thermally
enhanced eTSSOP-20 package.
Lumissil Microsystems – www.lumissil.com
Rev. A, 01/14/2020
Operating voltage range, 5V to 42V
1MHz I2C-compatible interface
Dual channel current sources
- Individual programmable current via a single
external resistor and I2C
- Configurable from 20mA to 150mA
Single channel 30mA (Max.) current source for
switch illumination
EN input supports either momentary contact or
latched switch
- Input is debounced and latched
- Lower priority than I2C input
- Gamma corrected Fade ON/OFF algorithm
- Pull down resistors or I2C set independent fade
ON and OFF ramp time
Selectable internal PWM source
- Internal 220Hz PWM source with Gamma
corrected algorithm for automatic dimming the
current source
Fault Protection:
- Fault Reporting
LED strings short
LED strings open
Over temperature thermal shutdown
- ISET pin shorted to GND
- Over temperature current roll off
Operating temperature range from -40°C ~ +125°C
AEC-Q100 Qualified
APPLICATIONS
Automotive Interior:
- Map/Dome light
- Puddle lamp in doors
- Glove box light
- Vanity mirror light
1
IS32LT3129A
TYPICAL APPLICATION CIRCUIT
VBattery
18
VCC
OUT1
OUT2
10 F
8
1 F
47k
2k
2k
470
9
470
10
Micro
Controller
7
2
11
Momentary
Contact
S1
4
S2
3
6,17
Figure 1
OUT3
VIO
1
SCL
SDA
Backlight LED
IS32LT3129A
FAULTB
EN3
ISET1
AD
ISET2
EN1
ISET3
EN2
TSET_UP
GND
TSET_DN
18
VCC
OUT1
OUT2
10 F
8
47k
20
12 RISET1
13 RISET2
14 RISET3
15 RTSET_UP
16 RTSET_DN
Typical Application Circuit with Momentary Contact Switch
VBattery
1 F
19
2k
2k
470
9
470
10
Micro
Controller
7
2
VCC
S1
Latched
Switch
S2
VIO
11
4
3
6,17
Figure 2
OUT3
VIO
SCL
SDA
19
20
1
Backlight LED
IS32LT3129A
FAULTB
EN3
ISET1
AD
ISET2
EN1
ISET3
EN2
TSET_UP
GND
TSET_DN
12 RISET1
13 RISET2
14 RISET3
15 RTSET_UP
16 RTSET_DN
Typical Application Circuit with Latched Switch
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Rev. A, 01/14/2020
2
IS32LT3129A
PIN CONFIGURATION
Package
Pin Configuration (Top View)
eTSSOP-20
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Rev. A, 01/14/2020
3
IS32LT3129A
PIN DESCRIPTION
No.
Pin
Description
1
OUT3
Maximum 30mA output current source for switch backlight LEDs.
2
EN3
Internally deglitch input pin for control of OUT3 current. Pull high (>VIH) to
enable OUT3 current. Pull low ( 6V to IOUT< -5mA (Note 3)
OUT1/2 limit current
(Note 4)
VHR= 2V, OUT1/2 sourcing current, VISET1/2= GND
-240
-205
-160
OUT3 limit current
(Note 4)
VHR= 2V, OUT3 sourcing current, VISET3= GND
-48
-40
-32
OUT1/2 output current
RISET1/2= 15kΩ, VHR= 1V, -40°C< TJ< +125°C
(Note 4)
-105
-100
-95
OUT3 output current
(Note 4)
RISET3= 15kΩ, VHR= 1V, -40°C< TJ< +125°C
-22
-20
-18
-50mA≤ IOUT1/2≤ -20mA, VHR= 1V,
-40°C< TJ< +125°C
-8
8
%
-150mA≤ IOUT1/2< -50mA, VHR= 1V,
-40°C< TJ< +125°C
-6
6
%
4
%
6
%
100
μs
OUT1/2 absolute
current accuracy
(Note 4)
400
mA
mA
OUT1/2 current
IOUT1/2= -100mA, VHR= 1V, TJ= 25°C
matching in case of
the same RISET1/2 value
IOUT1/2= -100mA, VHR= 1V, -40°C< TJ< +125°C
(Note 4,5)
Current slew time
μs
Current rise/fall between 0%~100%, VTSET= GND
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Rev. A, 01/14/2020
45
75
6
IS32LT3129A
ELECTRICAL CHARACTERISTICS (CONTINUE)
TJ= -40°C ~ +125°C, VCC= 12V, the detail refer to each condition description. Typical values are at TJ= 25°C.
Symbol
fINTPWM
tSW
UVLO
Parameter
Condition
Min.
Internal PWM frequency
Typ.
Max.
220
Input pin debounce time (EN1/2
pins and I2C command latency in
internal PWM mode)
Unit
Hz
25
37
50
ms
Release from under voltage lock
out VCC voltage
VCC rising release from UVLO
4.4
4.6
4.8
V
Into under voltage lock out VCC
voltage
VCC falling into UVLO
4.2
4.5
4.7
V
TSET_UP, TSET_DN and VIO
VTSET
Voltage reference of TSET_UP and
TSET_DN
TACC
Fade timing accuracy
VIO
VIO pin output voltage
1
*Neglecting the RTSET Tolerance*
RTSET_UP= 100kΩ, TJ= 25°C
-5
V
5
4.3
%
V
Logic Input EN1/2/3
VIL
Input low voltage
VIH
Input high voltage
VIN_HY
IPU
IPD
0.8
2
Input hysteresis
(Note 3)
EN1/2 internal pull-up current
150
V
V
350
mV
EN_M bit= 1, VEN1/2= GND
67
μA
EN1/2 internal pull-down current
EN_M bit= 0, VEN1/2= 12V
50
μA
EN3 internal pull-down current
VEN3= 12V
28
μA
Protection
VSCD
OUTx pins short detect voltage
Measured at OUTx, voltage falling
VSCD_HY
OUTx pins short detect voltage
hysteresis
(Note 3)
220
mV
OUTx pins open threshold
Measured at (VCC-VOUTx), voltage
rising
200
mV
Measured at (VCC-VOUTx) (Note 3)
130
mV
110
µs
5
ms
VOCD
VOCD_HY OUTx pins open hysteresis
tFD_OC
Open fault detect persistence time DELAY bits= 0001 (Default)
tFD_SC
Short fault detect persistence time
VFAULTB FAULTB pin voltage
1.2
1.8
Sink current= 5mA
22
80
V
mV
TRO
Thermal roll off threshold
(Note 3)
145
°C
TSD
Thermal shutdown threshold
Temperature increasing (Note 3)
175
°C
THY
Thermal shutdown hysteresis
Recovery = TSD - THY (Note 3)
30
°C
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Rev. A, 01/14/2020
7
IS32LT3129A
ELECTRICAL CHARACTERISTICS (CONTINUE)
TJ= -40°C ~ +125°C, VCC= 12V, the detail refer to each condition description. Typical values are at TJ= 25°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
0.8
V
I2C Logic Electrical Characteristics (SDA, SCL, AD)
VIL
Logic “0” input voltage
(Note 3)
VIH
Logic “1” input voltage
(Note 3)
2
Input schmitt trigger hysteresis
(Note 3)
150
IIL
Logic “0” input current
IIH
Logic “1” input current
VHYS
V
350
mV
VINPUT= 0V (Note 3)
5
nA
VINPUT= VIO (Note 3)
5
nA
DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 3)
Symbol
Parameter
Fast Mode
Min.
Typ.
Fast Mode Plus
Typ.
Max.
Units
Max.
Min.
-
400
-
1000
kHz
fSCL
Serial-clock frequency
tBUF
Bus free time between a STOP and a START
condition
1.3
-
0.5
-
μs
tHD, STA
Hold time (repeated) START condition
0.6
-
0.26
-
μs
tSU, STA
Repeated START condition setup time
0.6
-
0.26
-
μs
tSU, STO
STOP condition setup time
0.6
-
0.26
-
μs
tHD, DAT
Data hold time
-
-
-
-
μs
tSU, DAT
Data setup time
100
-
50
-
ns
tLOW
SCL clock low period
1.3
-
0.5
-
μs
tHIGH
SCL clock high period
0.7
-
0.26
-
μs
tR
Rise time of both SDA and SCL signals,
receiving
-
300
-
120
ns
tF
Fall time of both SDA and SCL signals,
receiving
-
300
-
120
ns
Note 2: IOUT output current in case of VCC-VOUT=VHR called IOUT_VHR. IOUT output current in case of VCC-VOUT=2V called IOUT_VHR2V, VHR accuracy is
computed as |IOUT_VHR-IOUT_VHR2V|/IOUT_VHR2VVIH) and keep it
at high level, after a period of time that exceeds the
debounce time (Typ. 37ms) that will cause the
corresponding output to be toggled from the OFF
condition to the current source condition. When this
happens, the corresponding output current gradually
ramps up from zero mA to the programmed value (set
by RISET1/2 and 05h/06h register) over the time set by
the resistor (RTSET_UP) attached to the TSET_UP pin or
03h register. Conversely, if ENx is already kept in high
level and the output is in the source condition, the ENx
pin is pulled to low level, then the corresponding output
current will begin to ramp down towards zero mA in the
time period as programmed by the resistor (RTSET_DN)
attached to the TSET_DN pin or 04h register. So a
regular latched switch can be used in this mode.
Debounce – Output control is provided by a
debounced switch input, providing an ON/OFF toggle
action for various switch or button characteristics. An
internal debounce circuit will condition the EN input
signal so a single press of the mechanical switch
Figure 60
doesn’t appear like multiple presses. The EN input is
debounced by typically 37ms.
Note: The debounce time applies to both falling and
rising edges of the EN signal.
EN3 PIN OPERATION
The EN3 pin or EN3 bit of 02h register is the enable
control of OUT3. There is no fade ON/OFF function as
with the EN1/2 pins. EN3 pin is internally pulled down
by a 100kΩ resistor to ground. The latency time from
EN3 pin pull high over VIH to OUT3 output current rise
to 10% is 6µs (Typ.). Float or pull down EN3 to ground
to disable OUT3. An external PWM signal driving EN3
pin can implement OUT3 dimming by modulating PWM
duty cycle.
The recommended PWM signal frequency range is
50Hz-300Hz. The duty cycle can be 0~100%. The
output current of the PWM dimming is given by
Equation (3):
I OUT 3 _ PWM
300
DPWM
RISET 3
(3)
Where, DPWM is the duty cycle of the PWM.
In the meantime, the OUT3_C bits of 02h register can
be used to adjust the OUT3 current in 8 steps based
on above resistor setting.
EN1/2 in Low Pulse Mode (Momentory Contact Switch)
Figure 61
EN1/2 in Level Control Mode (Latched Switch)
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Rev. A, 01/14/2020
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IS32LT3129A
FADE ON AND FADE OFF DIMMING
The OUT1/2 LED fade function can be accomplished
in one of two methods; 1) by I2C refreshing the
PWM_E bit, or 2) when the EN1/2 pin is toggled.
I2C Dimming
The PWM_E bit in 07h register will simultaneously
control the both OUT1/2 channels. There are two kinds
of dimming modes via I2C: External-PWM-dimming
and Internal-PWM-Dimming. The different mode is
chosen by PWM_M bit in 01h register. PWM_M=1 for
External-PWM-dimming mode and PWM_M=0 for
Internal-PWM-Dimming mode.
External-PWM-dimming (PWM_M=1):
In this mode, the OUT1/2 can be driven by an external
I2C signal refreshing PWM_E bit to accomplish both
channels simultaneously dimming. The integrated
gamma correction and fade ON/OFF ramp functions
are disabled when actively driving this bit.
To get better dimming ratio, the recommended
refreshing PWM_E bit frequency range is 50Hz-300Hz.
The duty cycle can be 0-100%. The output current of
the PWM dimming is given by Equation (4):
Figure 62
I OUT 1/ 2
1500
DPWM
RISET 1/ 2
(4)
Where, DPWM is the duty cycle of the external I2C
signal refreshing PWM_E bit. Please refer to Figure
35~40 for the delay time of I2C command to current
change edge.
Internal-PWM-Dimming (PWM_M=0):
In this mode, the integrated PWM source is operational.
PWM_E=1 can trigger this PWM source. When
PWM_E is changed the logic state and after a period
of time that exceeds the debounce time (37ms), the
both output current will either gradually ramp up from
zero mA to the programmed value (set by RISET1/2 and
05h/06h register) over the time set by the resistor
(RTSET_UP) attached to the TSET_UP pin (or 03h
register), or gradually ramp down from programmed
value to zero mA over the time set by the resistor
(RTSET_DN) attached to the TSET_DN pin (or 04h
register). The ramping up (or down) is accomplished
by the internal 220Hz PWM source digitally modulating
the both output current simultaneously with 63 steps
gamma correction, that will perform an extremely
visual linear light to human eye.
Ineternal-PWM-Dimming for OUT1/2
THE PRIORITY OF EN1/2 AND PWM DIMMING
EN1/2 pins can individually control the OUT1/2 while
PWM_E bit can simultaneously control the both
outputs. The Figure 63~69 lists some critical priority
logic of them:
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Rev. A, 01/14/2020
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IS32LT3129A
PWM_E Bit
Figure 63
Priority Logic 1 of EN1/2 in Low Pulse Mode
Figure 64
Priority Logic 2 of EN1/2 in Low Pulse Mode
Figure 65
Priority Logic 3 of EN1/2 in Low Pulse Mode
PWM_E Bit
PWM_E Bit
PWM_E Bit
Figure 66
Priority Logic 1 of EN1/2 in Level Control Mode
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Rev. A, 01/14/2020
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IS32LT3129A
Figure 67
Priority Logic 2 of EN1/2 in Level Control Mode
Figure 68
Priority Logic 3 of EN1/2 in Level Control Mode
Figure 69
Priority Logic 4 of EN1/2 in Level Control Mode
UNDERVOLTAGE LOCKOUT
IS32LT3129A integrates an undervoltage lockout
function to prevent mis-operation of the device during
low input voltage conditions.
Should the VCC pin voltage fall below 4.5V (Typ.), the
device will turn OFF the current source and maintain
the EN latch status as long as the VCC pin voltage
remains above 4.0V (Typ.). An external capacitor
(Figure 70) is necessary to help maintain the VCC pin
voltage >4.0V (Typ.) and to supply current to the
device status latch circuitry. However, should the
voltage drop below 4.0V (Typ.), the internal latch will
be reset to the power on default status (LED initial off
state).
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Rev. A, 01/14/2020
The current source will be turned ON when the input
voltage is re-applied and the VCC pin rises above 4.6V
(Typ.).
Figure 70
Capacitor For Latch Status
SETTING THE FADE TIME
The fade time can be configured by either the external
resistors or I2C register, which is decided by the FIT
and FOT bit of 01h register.
28
IS32LT3129A
When FIT (or FOT) bit is set to “1”, the fade time is
programmed by 03h (or 04h) 8 bits register with each
7ms per step over time range of 7ms~1785ms.
When FIT (or FOT) bit is set to “0”, the fade time is
programmed by two external programming resistors;
RTSET_UP and RTSET_DN. The RTSET_UP connected to the
TSET_UP pin configures the fade ramp ON time while
the RTSET_DN connected to the TSET_DN pin
configures the fade ramp OFF time. The fade time (ON
or OFF) is programmable by Equation (5):
t RTSET 2.5s
(5)
For example, RTSET=100kΩ, Fade ON/OFF time is
about 0.25s.
Note: In order to get the optimized effect, the
recommended fading time is between 1.5s (RTSET=
600kΩ) and 0.25s (RTSET= 100kΩ).
If either the TSET_UP or TSET_DN pin is tied directly
to GND or 03h/04h register set to “0000 0000”, the
corresponding fade function is canceled and the ramp
time is about 75µs, or “instant on”. However, the
debounce feature of the EN pin is not disabled.
Table 2 63 Gamma Steps Correction
C(0)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
0
2
4
6
8
10
12
16
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
20
24
28
32
36
42
48
54
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
60
66
72
80
88
96
104
112
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
C(31)
120
130
140
150
160
170
180
194
C(32)
C(33)
C(34)
C(35)
C(36)
C(37)
C(38)
C(39)
208
222
236
250
264
282
300
318
C(40)
C(41)
C(42)
C(43)
C(44)
C(45)
C(46)
C(47)
336
354
372
394
416
438
460
482
C(48)
C(49)
C(50)
C(51)
C(52)
C(53)
C(54)
C(55)
504
534
564
594
624
654
684
722
C(56)
C(57)
C(58)
C(59)
C(60)
C(61)
C(62)
760
798
836
874
914
956
1000
1000
900
GAMMA CORRECTION
Gamma correction, also known as gamma
compression or encoding, is used to encode linear
luminance to match the non-linear characteristics of
display. Gamma correction will vary the step size of the
current such that the fading of the light appears linear
to the human eye. Even though there may be 1000
linear steps for the fading algorithm, when gamma
corrected, the actual number of steps could be as low
as 63.
800
LED Current Duty
In order to perform a better visual LED breathing effect
we recommend using a gamma corrected value to set
the LED intensity. This results in a reduced number of
steps for the LED intensity setting, but causes the
change in intensity to appear more linear to the human
eye.
700
600
500
400
300
200
100
0
0
5
10
15
20
25
30
35
40
45
50
55
60 62
Gamma Steps
Figure 71
Gamma Correction (63 Steps)
FAULT DETECTION
When VCC voltage exceeds the voltage level which is
set by F_UVLO bits in 08h register, the LED open fault
detection is enabled. The intention is to prevent false
fault reporting during abnormal VCC condition. Such
as power up or EMS test condition. An output open
circuit fault is detected if the voltage of VCC to OUTx
drops below open circuit detection threshold VOCD
(Typ. 200mV) and remains for tFD_OC (programmed by
DELAY bits in 08h register). The channel (OUT1/2/3)
will keep normal sourcing but the corresponding output
open circuit flag bit in 07h register will be set to “1” to
report the fault and FAULTB pin will be pulled low.
When the open condition is removed, the
corresponding output open circuit flag bit in 07h
register will be reset to “0” and FAULTB pin will
recovery to high impedance.
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IS32LT3129A
An output shorted to GND fault is detected if the output
voltage on a channel drops below the low voltage
threshold VSCD (Typ. 1.8V) and remains below the
threshold for tFD_SC (Typ. 5ms). The channel
(OUT1/2/3) with the short condition will reduce its
output current to 4mA and set the corresponding
output short circuit flag bit in 07h register to “1” and
FAULTB pin will be pulled low. When the short
condition is removed, the output current will recover to
original value and the corresponding output short
circuit flag bit in 07h register will be reset to “0” and
FAULTB pin will recovery to high impedance.
The FAULTB pin is an open drain structure. When a
fault is asserted, the pin will change from high
impedance to pull low state. If it is externally connected
to a pull-up resistor, it will be at the pull-up voltage after
fault is released.
The detect action and FAULTB pin reporting of the
open/short circuit can be disabled by 0Ah register. A
FAULTB pin assertion of open detection can be
delayed that can be set by DELAY bits in 08h register.
When the ISET pin is shorted to GND and output
current is larger than limit value, about 205mA for
OUT1/2 and 40mA for OUT3, the output current will be
clamped. Once the short fault condition is removed,
the output current will recover to its original value.
OVERTEMPERATURE PROTECTION
The device features an integrated thermal rollback
feature which will reduce the output current in a linear
fashion if the silicon temperature exceeds 145°C
(Typ.). In the event that the die temperature continues
to increase, the device will enter thermal shutdown if
the temperature exceeds 175°C.
The FAULTB pin reporting of the thermal shutdown
protection can be disabled by TSDREN bit in 0Ah
register.
THERMAL CONSIDERATIONS
The package thermal resistance, θJA, determines the
amount of heat that can pass from the silicon die to the
surrounding ambient environment. The θJA is a
measure of the temperature rise created by power
dissipation and is usually measured in degree Celsius
per watt (°C/W). The junction temperature, TJ, can be
calculated by the rise of the silicon temperature, ∆T,
the power dissipation, PD, and the package thermal
resistance, θJA, as in Equation (6):
3
PD VCC I CC (VCC VLEDx ) I OUTx
and,
TJ TA T TA PD JA
When operating the chip at high ambient temperatures,
or when driving maximum load current, care must be
taken to avoid exceeding the package power
dissipation limits. The maximum power dissipation can
be calculated using the following Equation (8):
PD PD ( MAX )
THERMAL SHUTDOWN
In the event that the die temperature exceeds 175°C,
the output channel will go to the “OFF” state and TSD
bit in 07h register will be set to “1” and FAULTB pin will
be pulled low. At this point, the IC presumably begins
to cool off. Any attempt to toggle the channel back to
the source condition before the IC cooled to < 145°C
will be blocked and the IC will not be allowed to restart.
Once restart, the TSD bit in 07h register will be reset to
“0” and FAULTB pin will recovery to high impedance.
125C 25C
(8)
JA
So,
PD
125C 25C
2.94W
34C / W
Figure 72, shows the power derating of the
IS32LT3129A on a JEDEC board (in accordance with
JESD 51-5 and JESD 51-7) standing in still air.
3.5
eTSSOP-20
Power Dissipation (W)
The thermal rolloff function can be disabled by the TEN
bit in 01h register.
(7)
Where ICC is the IC quiescent current, VCC is the supply
voltage, VLED is the voltage across VCC to OUT and TA
is the ambient temperature.
THERMAL ROLLOFF
The output current will be equal to the set value as
long as the die temperature of the IC remains below
145°C (Typ.). If the die temperature exceeds this
threshold, the output current of the device will begin to
reduce at a rate of 3.8%/°C until 5% of IOUT and turn off
after this current level.
(6)
x 1
3
2.5
2
1.5
1
0.5
0
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 72
Lumissil Microsystems – www.lumissil.com
Rev. A, 01/14/2020
Dissipation Curve
30
IS32LT3129A
The thermal resistance is achieved by mounting the
IS32LT3129A on a standard FR4 double-sided printed
circuit board (PCB) with a copper area of a few square
inches on each side of the board under the
IS32LT3129A. Multiple thermal vias, as shown in
Figure 73, help to conduct the heat from the exposed
pad of the IS32LT3129A to the copper on each side of
the board. The thermal resistance can be reduced by
using a metal substrate or by adding a heatsink or
thicker copper plane.
1.2mm
0.3mm
Figure 73
Lumissil Microsystems – www.lumissil.com
Rev. A, 01/14/2020
Board Via Layout For Thermal Dissipation
31
IS32LT3129A
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 74
Classification Profile
Lumissil Microsystems – www.lumissil.com
Rev. A, 01/14/2020
32
IS32LT3129A
PACKAGE INFORMATION
eTSSOP-20
Lumissil Microsystems – www.lumissil.com
Rev. A, 01/14/2020
33
IS32LT3129A
RECOMMENDED LAND PATTERN
eTSSOP-20
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use.
Lumissil Microsystems – www.lumissil.com
Rev. A, 01/14/2020
34
IS32LT3129A
REVISION HISTORY
Revision
A
Detail Information
Initial release
Lumissil Microsystems – www.lumissil.com
Rev. A, 01/14/2020
Date
2020.01.07
35
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