IS32LT3123
QUAD CHANNEL EXTERNAL NMOS FET HIGH CURRENT
AUTOMOTIVE LED CONTROLLER WITH INTERNAL PWM DIMMING
May 2020
GENERAL DESCRIPTION
FEATURES
The IS32LT3123 is a quad channel linear controller
capable of accurately regulating LED current with
external NMOS FETs. It integrates PWM dimming for
two LED brightness levels for RCL (Rear Combination
Lamp) or DRL (Daytime Running Lamp) applications.
It is fully programmable with two LED brightness
levels for the different intensity requirements, such as
“Stop” (full brightness) and “Tail” dim (PWM dimming).
A logic level at the PWMB pin is used to switch
between the two brightness levels. A logic high
provides the highest intensity output, while a logic low
utilizes an internally generated PWM signal to reduce
the intensity of the LEDs’ light output.
Multiple devices also can be connected in parallel in a
master-slave structure for larger lighting applications.
For added system reliability, the IS32LT3123
integrates fault detection circuitry for LED open/short
circuit, input over voltage and over temperature
conditions. The FAULTB pin is dedicated to the fault
conditions reporting and the MODE pin can control
the action of the device in case of a fault condition.
The device also supports the NTC resister to monitor
the LED string temperature. In case of the
temperature exceeds the setting threshold, the device
will reduce the drive current to protect the LED string.
The device package is an eTSSOP-24 with exposed
pad for enhanced thermal dissipation.
Low side external NMOS FETs support high
output current with independent current setting
One resistor to simultaneously adjust all channels
for LED binning
200mV reference feedback voltage for high
efficiency
±4% current accuracy over -40°C ~125°C
5.0V to 40V supply voltage
PWMB voltage input to select between full
brightness and PWM dimming
Flexible LED PWM dimming options
- Internal PWM dimming set by resistors
Programmable duty cycle, 5%~95%
Programmable frequency, 100Hz~1kHz
- External PWM signal input dimming
- Analog voltage input for PWM dimming
PWM slew rate control on each output to optimize
EMI performance
Robust fault protection
- Fault reporting
LED string open/short
Thermal shutdown
- LED string over temperature thermal rolloff
- Input over voltage current derating
- Controller junction over temperature thermal
rolloff
Multiple parallel IC operation for higher number of
strings with fault condition and PWM dimming
sync
AEC-Q100 Qualified
APPLICATIONS
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Rev. A, 05/06/2020
Automotive and avionic lighting
Rear combination light (STOP/TAIL lights)
Center high mounted stop light
Position light
Daytime running light (DRL)
Turn light
1
IS32LT3123
TYPICAL APPLICATION CIRCUIT
Figure 1
Typical Application Circuit of Internal PWM Dimming
Figure 2
Typical Application Circuit of External PWM Dimming
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2
IS32LT3123
Figure 3
Typical Application Circuit of Analog Input PWM Dimming
Connected to VIN of other slaves
D1
Power Supply -1
(PWM Dimming)
D2
Power Supply -2
(Full Brightness)
CVCC
1µF
RPWM1
12
11
12
VIN
PWMB
DET1
GATE1
RPWM2
CVDD
1µF 2
RTAIL1 RTH1
FB1
VDD
Connected to
master device
PWMB pin
24
23
Q1
22
RTH2
VTH
DET4
5
RTAIL2
CTAIL
1nF
RNTC
NTC
CNTC
1nF
MODE
FAULTB
CADJR
10nF 6
RADJR
FB4
MASTER
4
*Placed close
to LED
GATE4
TAIL
7
ADJR
PWMOUT
PWMIN
Connected to
master device
VTH pin
13
14
1
10
VDD
PWMB
VTH
5
Connected to
master device
NTC pin
IS32LT3123
GATE4
TAIL
NTC
FB4
13
14
7
MODE
PWMOUT
GND
Q4
15
RFB4
CNTC
1nF
ADJR
Q1
22
RFB1
PWMIN
RADJR
RFPWM
24
23
SLAVE #1
4
CADJR
10nF 6
8
FB1
DET4
RFB4
RFAULTB
DET1
VDD
CVTH
1nF
Q4
9
GND
3
VDD
15
VIN
GATE1
RFB1
IS32LT3123
11
CVDD
1µF 2
RTRO
3
CVCC
1µF
FAULTB
1
VDD
9
8
10
Connected to
FAULTB of
other slaves
Connected to PWMIN of other slaves
Figure 4
Typical Application Circuit of Several Devices in Parallel (one master with several slaves)
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Rev. A, 05/06/2020
3
IS32LT3123
PIN CONFIGURATION
Package
Pin Configuration (Top View)
eTSSOP-24
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Rev. A, 05/06/2020
4
IS32LT3123
PIN DESCRIPTION
No.
Pin
Function
1
MODE
MODE pin decides the fault mode. Tie to VDD or GND. Do not leave
unconnected.
2
VDD
Internal LDO output. Connect to GND through a 1µF X7R capacitor which should
be placed as close to VDD pin as possible. It is capable to drive external circuitry
with minimum 14mA current capability.
3
VTH
Voltage at this pin sets the VIN over voltage current derating threshold and the VIN
threshold for open LED fault detect.
4
NTC
Connect the NTC resistor divider to set the temperature threshold for the LED
string temperature monitor. As long as the temperature exceeds the threshold,
the reference voltage will be derated linearly according to NTC pin voltage.
5
TAIL
Connect to an external DC voltage below 3.7V for internal PWM mode to adjust
operating duty cycle.
Connect TAIL pin to VDD for external PWM mode. PWM duty cycle is controlled
by the PWM signal on PWMIN pin.
6
ADJR
Connect a proper value resistor from this pin to GND to set the Internal reference
voltage.
7
GND
Ground pin.
8
PWMIN
In internal PWM mode (TAIL pin voltage < 3.7V), the frequency of PWM is set by
a resistor from PWMIN to GND.
In external PWM mode (TAIL pin is connected to VDD), PWM frequency and duty
cycle are determined by external PWM signal on PWMIN pin.
9
PWMOUT
PWM signal output pin.
In internal PWM mode, the output PWM signal is internal PWM generator.
In external PWM mode, the output PWM signal is sync with PWMIN pin.
FAULTB
Open drain I/O diagnostic pin. Active low output driven by the device when it
detects a fault condition. As an input (MODE pin high), this pin will accept an
externally generated FAULTB signal to disable the device output to satisfy the
“One-Fail-All-Fail” function. Note this pin requires an external pull up resistor
(RFAULTB).
11
PWMB
Full brightness mode select input.
When PWMB pin is low, the device is in PWM dimming mode and the output is
dimming by the internal or external PWM signal.
When PWMB pin is high, the device is in full brightness mode, NMOS FET
current 100% duty cycle operation. And the internal and external PWM signal are
overridden.
12
VIN
Power input for the IC.
24,19,18,13
DET1/2/3/4
Detect NMOS FET drain voltage for channel 1/2/3/4 LED string open/short faults.
If any channel is unused, connect its DET pin to used DET pin. For example, if
channel 1/2 are used and channel 3/4 are not used. DET1/2 is connected to the
drain of their NMOS FETs. DET3/4 can be connected to DET1 or DET2.
23,20,17,14
GATE1/2/3/4
Gate driver for external NMOS FET1/2/3/4.
22,21,16,15
FB1/2/3/4
Current sense for channel 1/2/3/4. Connect sense resistors to independently set
current level of channel 1/2/3/4.
Thermal Pad
Must be connected to GND with sufficient copper plate for heat sink.
10
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Rev. A, 05/06/2020
5
IS32LT3123
ORDERING INFORMATION
Automotive Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS32LT3123-ZLA3-TR
eTSSOP-24, Lead-free
2500
Copyright © 2020 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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Rev. A, 05/06/2020
6
IS32LT3123
ABSOLUTE MAXIMUM RATINGS (Note 1)
Voltage at VIN
Voltage at PWMB, FAULTB, DET1~4, PWMIN
Voltage at GATE1~4, FB1~4, PWMOUT
Voltage at VDD, VTH, ADJR, NTC, TAIL, MODE
Operating temperature, TA=TJ
Storage temperature, TSTG
Junction temperature, TJMAX
Package thermal resistance, junction to ambient (4 layer
standard test PCB based on JESD 51-2A), θJA
Package thermal resistance, junction to thermal PAD (4 layer
standard test PCB based on JESD 51-8), θJP
ESD (HBM)
ESD (CDM)
-0.3V ~ +42V
-0.3V ~ +VIN+0.3V
-0.3V ~ +20V
-0.3V ~ +7V
-40°C ~ +150°C
-65°C ~ +150°C
+150°C
28.1°C/W
8.55°C/W
±2kV
±750V
Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Valid at VIN= 7V ~ 19V
“●” symbol indicates specifications across the full operating temperature range with TA= TJ= -40°C to +125°C, other
specifications are at TA= TJ= 25°C; unless noted otherwise.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
40
V
Input Supply
VIN
Operating input voltage range
●
5.0
VIN_UV
VIN undervoltage release
VIN rising
4.5
V
VIN_UVHY
VIN undervoltage lockout
hysteresis
IC disabled
0.15
V
IIN
VIN operational current
VNTC=VVTH=VTAIL=VDD,
PWMB=High
tON
Startup time
VIN>7V, CVDD= 10μF,
VFB= 20mV, PWMB=High
●
13
200
mA
µs
Current Regulation
VREFMAX
Maximum reference voltage on
FB pins
VVTH=VNTC=VADJR=VDD
VREFDR
VIN over voltage derating for
reference voltage
VVTH= 2V, VNTC=VADJR=VDD
VIN≥ 26V
ErrVREF
Matching between FB voltage
(Note 2)
VVTH=VNTC=VADJR=VDD
VREFADJR
Reference voltage adjusted by
ADJR pin
VVTH=VNTC=VDD, RADJR=2kΩ
●
122
VDD pin voltage output
IVDD= 10mA
●
5.0
●
14
VDD
IDD_LIM
VDD pin output current limit
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Rev. A, 05/06/2020
●
VVTH=VNTC=VADJR=VDD
192
200
208
194
200
206
51
mV
%
2
%
132
142
mV
5.25
5.5
V
mA
7
IS32LT3123
ELECTRICAL CHARACTERISTICS (CONTINUE)
Valid at VIN= 7V ~ 19V
“●” symbol indicates specifications across the full operating temperature range with TA= TJ= -40°C to +125°C, other
specifications are at TA= TJ= 25°C; unless noted otherwise.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
8
V
0.2
V
Gate Driver
VGATEH
GATE high-level output
VIN= 12V, PWMIN=High,
VFB= 150mV, VTAIL= VDD
VGATEL
GATE low-level output
PWMIN= Low, PWMB=Low
VGATED
GATE driver dropout
VIN= 7V, VFB= 150mV,
measured as (VIN - VGATE)
1.65
V
IGPU
Gate pull-up current
VFB= 180mV, VGATE= 0V,
VIN= 7V
-0.92
mA
IGPD
Gate pull-down current
VFB= 220mV, VGATE= 7V,
VIN= 7V
8.8
mA
CGISS
External NMOS FET gate
capacitance range (Note 5)
For stable operation
tPD
Propagation delay (Note 5)
Delay from PWMIN to
PWMOUT pin, TAIL
connected to VDD
Internal PWM signal frequency
External RFPWM= 30kΩ,
across PWMIN to GND
fPWM
DPWM7
PWM duty cycle
DPWM90
tDPWM
6
250
2000
0.1
●
pF
µs
180
200
220
VTAIL driven by resistor
divider from VDD, VTAIL/VDD=
0.093, RFPWM= 30kΩ
6.3
7
7.7
VTAIL driven by resistor
divider from VDD, VTAIL/VDD=
0.612, RFPWM= 30kΩ
87
Hz
%
Delay time between PWMIN rising Delay time between PWM
edge to 20% of FB
rising edge to 20% of FB
90
93
23
us
tSR
Current slew time
FB rising from 20% to 90%
levels, for internal reference
ramp
49
70
91
µs
tSF
Current slew time
FB falling from 90% to 20%
levels, for internal reference
ramp
49
70
91
µs
Rise time and fall time mismatch
between four strings (Note 3,4)
Rise and fall time mismatch
between 20% and 90%
levels in all strings
5
%
tSRMS
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Rev. A, 05/06/2020
8
IS32LT3123
ELECTRICAL CHARACTERISTICS (CONTINUE)
Valid at VIN= 7V ~ 19V
“●” symbol indicates specifications across the full operating temperature range with TA= TJ= -40°C to +125°C, other
specifications are at TA= TJ= 25°C; unless noted otherwise.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
0.8
V
Logic Pins
VIL
MODE, PWMIN, FAULTB pins
input low voltage
Below VIL level, input voltage
considered as logic LOW
●
VIH
MODE, PWMIN, FAULTB pins
input high voltage
Above VIH level, input
voltage considered as logic
HIGH
●
VOL
FAULTB, PWMOUT pins output
low voltage
IOL= 1mA
●
VOH
PWMOUT pin output high voltage IOH= –1mA
VILF
PWMB pin input low voltage
VIHF
PWMB pin input high voltage
2
V
0.4
V
●
4
V
Below VILF level, input
voltage on PWMB pin will
disable PWM dimming mode
●
0.85
1.15
V
Above VIHF level, input
voltage on PWMB pin will
enable PWM dimming mode
●
1.06
1.44
V
21.7
V
Protection
VINth(L)
Input over voltage derates VFB by
10%
VVTH= 2V
VINthd
Input over voltage derating range
(VIN_180mV to VIN_120mV)
VREF drops from 180mV to
120mV
VSCV
VIN to drain short detect voltage
Measured as (VIN - VDET)
●
0.5
0.8
1.1
V
VOCV
Open LED fault detect voltage
Measured at DET,
VIN>VOCVEN
●
0.2
0.25
0.3
V
VOCVEN
Open LED detect enable voltage
VVTH= 2V
VNTC10
NTC derates VFB by 10%
VNTC90
NTC derates VFB by 90%
TJH
Thermal rolloff activation
temperature (Note 5)
TJL
19.7
20.7
2.16
V
10
1.9
2.0
V
2.12
V
0.43
V
VFB derated by 10%
148
°C
Thermal rolloff low-current
temperature (Note 5)
VFB derated by 65%
163
°C
TSD
Over temperature shutdown
(Note 5)
Temperature increasing
170
°C
TSDHY
Over temperature hysteresis
(Note 5)
Recovery= TSD -TSDHY
30
°C
Note 2: Reference matching is defined as: (VFB(max) – VFB(min)) / VFB(AVG) . Where VFB(AVG) is the average of all VFB.
Note 3: Rise Time to Fall Time Matching is defined as the maximum difference between the rise time and the fall time of the same string.
Note 4: Rise Time to Fall Time Mismatch between all strings is defined as the maximum ratio of the difference between either the rise time or
the fall time to the average of the rise time or fall times between all strings.
Note 5: Guaranteed by design.
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Rev. A, 05/06/2020
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IS32LT3123
FUNCTIONAL BLOCK DIAGRAM
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Rev. A, 05/06/2020
10
IS32LT3123
TYPICAL PERFORMANCE CHARACTERISTICS
12
11.5
12
VIN = 12V
VNTC = VVTH = VTAIL = VDD
PWMB = High
VNTC = VVTH = VTAIL = VDD
PWMB = High
TA = 25°C
11.5
11
IIN (mA)
IIN (mA)
11
10.5
10.5
10
9.5
10
9
9.5
9
-40
8.5
8
-25
-10
5
20
35
50
65
80
95
110
125
7
10
13
16
IIN vs. Temperature
Figure 6
VDD (V)
VDD (V)
5
4.5
34
37
40
31
34
37
40
31
34
37
40
IIN vs. Supply Voltage
5.0
4.5
-25
-10
5
20
35
50
65
80
95
110
4.0
125
7
10
13
16
Figure 7
19
22
25
28
Supply Voltage (V)
Temperature (°C)
VDD vs. Temperature
Figure 8
VDD vs. Supply Voltage
150
150
VIN = 12V
RADJR = 2kΩ
VNTC = VVTH = VTAIL = VDD
RADJR = 2kΩ
VNTC = VVTH = VTAIL = VDD
TA = 25°C
145
140
140
VREF (mV)
VREF (mV)
31
5.5
5.5
135
130
135
130
125
125
120
-40
28
TA = 25°C
VIN = 12V
145
25
6.0
6
4
-40
22
Supply Voltage (V)
Temperature (°C)
Figure 5
19
-25
-10
5
20
35
50
65
80
95
110
125
120
7
10
13
16
VREF vs. Temperature
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Rev. A, 05/06/2020
22
25
28
Supply Voltage (V)
Temperature (°C)
Figure 9
19
Figure 10
VREF vs. Supply Voltage
11
IS32LT3123
215
215
205
200
195
190
185
-40
RADJR = 5kΩ
VNTC = VVTH = VTAIL = VDD
TA = 25°C
210
VREFMAX (mV)
VREFMAX (mV)
210
VIN = 12V
RADJR = 5kΩ
VNTC = VVTH = VTAIL = VDD
205
200
195
190
-25
-10
5
20
35
50
65
80
95
110
185
125
7
10
13
16
Temperature (°C)
Figure 11 VREFMAX vs. Temperature
Figure 12
Duty Cycle (%)
Dury Cycle (%)
31
34
37
40
34
37
40
VREFMAX vs. Supply Voltage
9
9
6
3
8
7
6
-25
-10
5
20
35
50
65
80
95
110
5
125
7
10
13
16
Temperature (°C)
Figure 13
19
22
25
28
31
Supply Voltage (V)
Duty Cycle vs. Temperature (Internal PWM)
Figure 14
100
Duty Cycle vs. Supply Voltage (Internal PWM)
100
90
VIN = 12V
VTAIL /VDD = 0.612
80
70
60
50
VTAIL /VDD = 0.362
40
60
50
40
30
20
20
10
10
-10
5
20
35
50
65
80
95
110
125
VTAIL /VDD = 0.612
70
30
-25
TA = 25°C
80
Duty Cycle (%)
Duty Cycle (%)
28
VTAIL /VDD = 0.093
TA = 25°C
12
0
-40
25
10
VIN = 12V
VTAIL /VDD = 0.093
90
22
Supply Voltage (V)
15
0
-40
19
0
VTAIL /VDD = 0.362
7
10
Temperature (°C)
Figure 15
Duty Cycle vs. Temperature (Internal PWM)
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Rev. A, 05/06/2020
13
16
19
22
25
28
31
34
37
40
Supply Voltage (V)
Figure 16
Duty Cycle vs. Supply Voltage (Internal PWM)
12
IS32LT3123
220
220
RFPWM = 30kΩ
TA = 25°C
VIN = 12V
RFPWM = 30kΩ
210
fPWM (Hz)
fPWM (Hz)
210
200
190
200
190
180
-40
-25
-10
5
20
35
50
65
80
95
110
180
125
7
10
13
16
22
25
28
31
34
37
40
110
125
Supply Voltage (V)
Temperature (°C)
Figure 17
19
fPWM vs. Temperature (Internal PWM)
fPWM vs. Supply Voltage (Internal PWM)
Figure 18
5
23
VVTH = 2V
4.9
22
4.8
21
VIN_UV (V)
VINth(L) (V)
4.7
20
19
18
Rising
4.6
4.5
4.4
Falling
4.3
17
4.2
16
15
-40
4.1
-25
-10
5
20
35
50
65
80
95
110
4
-40
125
-25
-10
5
Temperature (°C)
Figure 19
35
50
65
80
95
Temperature (°C)
VINth(L) vs. Temperature
Figure 20
12.0
VIN_UV vs. Temperature
100
VVTH = 2V
VIN = 12V
TA = 25°C
90
11.5
80
Duty Cycle (%)
11.0
VOCVEN (V)
20
10.5
10.0
9.5
70
60
50
40
30
9.0
20
8.5
8.0
-40
10
-25
-10
5
20
35
50
65
80
95
110
125
0
0
0.5
Temperature (°C)
Figure 21
VOCVEN vs. Temperature
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Rev. A, 05/06/2020
1
1.5
2
2.5
3
3.5
4
VTAIL (V)
Figure 22
Duty Cycle vs. VTAIL (Internal PWM)
13
IS32LT3123
12
6
TA = 25°C
11.5
5.6
VOCVEN / VVTH
VINth(L) / VVTH
TA = 25°C
5.8
11
10.5
10
5.4
5.2
5
4.8
4.6
4.4
9.5
4.2
9
1
1.5
2
2.5
3
3.5
4
4
1
1.5
2
2.5
VVTH (V)
Figure 23
3.5
4
VVTH (V)
VINth(L) /VVTH vs. VVTH
Figure 24
250
VOCVEN /VVTH vs. VVTH
250
VIN = 12V
RADJR = 5kΩ
TA = 25°C
VVTH = 2V
TA = 25°C
230
210
VREF (mV)
200
VREF (mV)
3
150
100
190
170
150
130
110
50
90
70
0
0
0.5
1
1.5
2
50
2.5
16
18
20
VNTC (V)
Figure 25
24
26
28
30
Supply Voltage (V)
VREF vs. VNTC
Figure 26
VIN OVP
250
1000
VIN = 12V
VTAIL = 2V
TA = 25°C
900
Output Current (mA)
800
700
fPWM (Hz)
22
600
500
400
300
200
VIN = 12V
TA = 25°C
External PWM =100Hz, 500Hz, 1kHz
150
100
50
200
100
0
5
15
25
35
45
55
65
75
0
0
10
20
30
RFPWM (kΩ)
Figure 27
fPWM vs. RFPWM (Internal PWM)
Lumissil Microsystems – www.lumissil.com
Rev. A, 05/06/2020
40
50
60
70
80
90
100
PWM Duty Cycle (%)
Figure 28
External PWM Dimming
14
IS32LT3123
250
220
VIN = 12V
VNTC = VVTH = VTAIL = VDD
TA = 25°C
200
VIN = 12V
VNTC = VVTH = VTAIL = VDD
RADJR = 5kΩ
200
180
140
150
VREF (mV)
VREF (mV)
160
100
120
100
80
60
50
40
20
0
0
0.5
1
1.5
2
2.5
RADJR (kΩ)
Figure 29
VREF vs. RADJR
Lumissil Microsystems – www.lumissil.com
Rev. A, 05/06/2020
3
3.5
0
125 130
140
150
160
170
180
Temperature (°C)
Figure 30
Thermal Rolloff
15
IS32LT3123
APPLICATION INFORMATION
The IS32LT3123 is a programmable linear controller
capable of regulating high constant current in four LED
strings with external NMOS FETs. A dedicated pin
(PWMB) is able to switch the output current between
full brightness mode (high current) and PWM dimming
mode (low current) by an external logic level. In the
PWM dimming mode, the PWM dimming can be either
the internal PWM generator, whose duty cycle and
frequency are programmed by TAIL and PWMIN pins,
or an external PWM signal fed on PWMIN pin.
Mounting different value resistors on ADJR pin can
fine tune the output peak current for binning purpose.
With a NTC resistor divider placed close to LED strings,
IS32LT3123 can monitor the temperature of the LED
strings and realize current derating if the temperature
exceeds the setting thermal threshold, which
effectively prevents the LED strings from thermal
runaway damage. A settable input over voltage
detection is provided to sense the input voltage and
reduce the output current if the input voltage exceeds
the targeted threshold. IS32LT3123 also integrates
fault detection and protection circuitry for the LED
string open/short and over temperature fault conditions
and reports fault conditions by a dedicated pin
(FAULTB). In the case of fault conditions, the MODE
pin can control the action to be either “one fail all fail”
or “one fail all on”. The FAULTB pins of multiple
devices can be tied together for fault condition sharing
to achieve simultaneous “one fail all fail”.
VREF can be controlled by ADJR resistor (RADJR), NTC
thermal rolloff protection, input over voltage protection
and thermal rolloff protection actions. If RADJR≥3kΩ and
no protection actions, VREF is maximum value, VREFMAX
(Typ. 0.2V). The feedback resistor value can be
computed using the following:
RFB
VREFMAX
I OUT _ FULL
(1)
Where IOUT_FULL is output current of full brightness
mode (without PWM dimming) in Amp and RFB is in Ω.
It is recommend that RFB be a 1% accuracy resistor
with good temperature characteristic to ensure stable
and precise output current.
When the desired current is high, the power rating also
should be considered. The maximum power
dissipation on the RFB resistor is calculated by:
PRFB VREFMAX I OUT _ FULL (2)
A single high wattage resistor or several small wattage
resistors in parallel can be used to sustain the power
dissipation.
Driver
+
UNDER VOLTAGE LOCKOUT (UVLO)
IS32LT3123 features an under voltage lockout (UVLO)
function on the VIN pin to prevent misoperation at too
low input voltages. UVLO threshold is an internally
fixed value and cannot be adjusted. The device is
enabled when the VIN voltage exceeds VIN_UV (Typ.
4.5V), and disabled when the VIN voltage falls below
(VIN_UV-VIN_UVHY) (Typ. 4.35V).
LINEAR REGULATOR VDD
The device incorporates a linear regulator (VDD)
output with a minimum 14mA current capability to
power external circuitry. It requires a low ESR, X7R
type ceramic capacitor from VDD pin to GND for
proper operation; this capacitor must be placed as
close to VDD pin as possible. To drive the external
circuitry, the recommended capacitor value is 1µF.
Figure 31
Constant Current Regulation
If any channel is unused, connect its FB pin to GND
and leave its GATE pin floating. To avoid false
protection triggering, its DET pin must be tied to one of
the used channel’s DET pin as Figure 32.
FB2
GATE2
OUTPUT CURRENT SETTING
The IS32LT3123 provides 4 channels of low-side
current drive via 4 external NMOS FETs. The negative
feedback loops drive the GATEs of NMOS FETs to
maintain the current feedback voltage of FB pins equal
to the internal reference voltage, VREF. All channels
share the same reference voltage source. So VREF
decides the output current. The regulated maximum
LED current of each NMOS FET is individually set by
its corresponding feedback resistor (RFB). As Figure 31.
Lumissil Microsystems – www.lumissil.com
Rev. A, 05/06/2020
DET2
IS32LT3123
DET1
GATE1
FB1
Figure 32
Unused Channel (CH1 Used and CH2 Unused)
16
IS32LT3123
CURRENT ADJUSTMENT BY ADJR
The ADJR pin is a dedicated pin for output current fine
tuning. Connecting a proper range value resistor,
RADJR, from this pin to GND can adjust the output
current, which can be used for LED binning or output
power ranking purpose. As Figure 31, there is a
precise constant current source, IADJR (typ. 1mA),
inside ADJR pin. When RADJR is connected, IADJR going
through this resistor creates a voltage drop on AJDR
pin which is detected by the internal Reference
Voltage Generator circuit to generate the internal
reference voltage, VREF, for output current regulation.
If RADJR value is greater than or equal to 3kΩ, the VREF
is clamped at maximum value, VREFMAX (typ. 0.2V). The
output current will be the maximum setting value,
IOUT_FULL in Equation (1).
RADJR. Once VNTC
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