IS32LT3124A/B/C/D/E/F
QUAD CHANNEL, LINEAR LED DRIVER WITH FAULT REPORTING
AND DYNAMIC HEADROOM CONTROL (DHC)
January 2019
GENERAL DESCRIPTION
FEATURES
The IS32LT3124 is a linear programmable current
regulator consisting of 4 output channels capable of up
to 150mA each. Individual external resistors set the
maximum current level for each channel. The outputs
can be combined to provide a higher current drive
capability up to 600mA (Max.).
The IS32LT3124 features Dynamic Headroom Control
(DHC) with an optional external PMOS FET to
minimize IC thermal stress when the supply voltage
exceeds the LED string forward voltage. It includes two
modes for different output power: Shunt Regulator
mode and Series Regulator mode. It can operate with
power supply modulation (PSM) for applications
requiring dimming without use of the EN pin.
For added system reliability, the IS32LT3124
integrates fault detection circuitry for open/short circuit
and over temperature conditions. The fault pins (FLTB)
can all be tied together to disable the device and other
IS32LT3124 devices on the same parallel circuit.
To handle all these different fault detection and
reporting features, the IS32LT3124 has six different
versions: A, B, C, D, E and F. All of them can support
the above features. See table 1 for the major
difference. In IS32LT3124A/B/D/E, if any fault
condition occurs, all output currents will be disabled. In
IS32LT3124B/C/E/F, individual ISET pin for each LED
channel is redefined as individual PWM dimming
control, thus ISET open detection function is removed.
The EN pin of IS32LT3124B/C/E/F is featured as the
enable signal of the internal fault reporting block. See
Table 4 for complete fault listing.
The IS32LT3124 is targeted at the automotive market
such as interior accent lighting and exterior tail lighting.
It is offered in a thermally enhanced eTSSOP-16
package.
APPLICATIONS
5.0V to 28V input supply voltage range
- Withstand 42V load dump
Four output channels can source up to 150mA
each
- Four current set resistors
- ±5% output current accuracy
- Low dropout voltage of 1V (Max.) at 100mA
- Combined for higher current capability with same
current accuracy
PWM dimming and shutdown control input
- 100Hz~300Hz power supply modulation (PSM)
- 100Hz~1kHz individual dimming via resistors of
ISETx pins (IS32LT3124B/C/E/F only)
Optional Dynamic Headroom Control (DHC) with
an external PMOS FET to minimize IC thermal
stress
- Shunt regulator mode for heavy load
- Series regulator mode for light load
Additional external UVLO (Under Voltage Lockout
Threshold) is programmable via EN pin
(IS32LT3124A/D only)
Fault protection and reporting
- Externally enable/disable fault reporting
(IS32LT3124B/C/E/F only)
- Programmable fault reporting output delay time
Fault
condition
disables
all
output
(IS32LT3124A/B/D/E only)
- Parallel fault connection (one-fail-all-fail)
- LED string open/short
- Single LED short (Conditional, IS32LT3124B/C/D
only)
- ISET pin short
- ISET pin open (IS32LT3124A/D only)
- Over temperature
AEC-Q100 Qualified
Operating temperature range (-40°C ~ +125°C)
Automotive LED driver
RGBW automotive ambient lighting
Tail light
Turn light
Daytime running light
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Rev. A, 01/02/2019
1
IS32LT3124A/B/C/D/E/F
Table 1 Major Difference Of Different Versions
Outx Pin Short To
GND Threshold
VSCD
Support LED String
Voltage
IS32LT3124A PSM dimming or Simultaneous dimming by EN pin
Typ. 1.22V
≥1 LED(s)
IS32LT3124B PSM dimming or Individual dimming by ISET resistors
Typ. 4.8V
IS32LT3124C PSM dimming or Individual dimming by ISET resistors
Typ. 4.8V
Version
Dimming
Fault Protection Action
(See Table 4 For More Details)
One channel fails all channels off
One channel fails all channels off
> (VSCD_MAX+VSCD_HY)
One channel fails all channels on
IS32LT3124D PSM dimming or Simultaneous dimming by EN pin
Typ. 4.8V
IS32LT3124E PSM dimming or Individual dimming by ISET resistors
Typ. 1.22V
≥1 LED(s)
One channel fails all channels off
One channel fails all channels off
IS32LT3124F PSM dimming or Individual dimming by ISET resistors
Typ. 1.22V
≥1 LED(s)
One channel fails all channels on
TYPICAL APPLICATION CIRCUIT
VBattery
D1
4
CVCC
VCC
CVICC
0.1µF
16
VICC
REN1
R1
RHR
1
HRSET
EN
2
REN2
RFLTD
10
RISET1
5
RISET2
6
RISET3
7
RISET4
8
IS32LT3124
FLTB
15
OUT1
14
OUT2
FLTD
13
OUT3
ISET1
C1
22nF
3
ERC
11
Q1
12
OUT4
ISET2
ISET3
ISET4
9
GND
Figure 1 Typical Application Circuit
VBattery
4
D1
CVCC_1
Connected to VCC
and VICC pins of
next device
CVCC_2
1
REN1_1
VCC
VICC
EN
HRSET
REN2_1
ERC
RFLTD_1 10
RISET1_1 5
RISET2_1 6
RISET3_1 7
8
11
IS32LT3124
FLTD
ISET1
ISET2
OUT1
OUT2
OUT3
CVICC
0.1µF
16
2
RHR_1
3
15
14
13
FLTB
Q1
C1
22nF
4
REN1_2
GND
OUT4
9
12
1
VCC
EN
VICC
HRSET
REN2_2
ERC
RFLTD_2 10
RISET1_2
RISET2_2
RISET3_2
ISET3
ISET4
R1
5
6
7
8
11
IS32LT3124
FLTD
ISET1
ISET2
OUT1
OUT2
OUT3
16
2
RHR_2
3
15
14
13
ISET3
ISET4
FLTB
GND
OUT4
9
12
Connected to HRSET
pin of next device
Connected to FLTB pin of next device
Figure 2
Typical Application Circuit (Several Devices in Parallel Share One External PMOS FET)
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2
IS32LT3124A/B/C/D/E/F
VBattery
4
D1
CVCC_1
1
REN1_1
VCC
VICC
EN
HRSET
REN2_1
ERC
RFLTD_1 10
RISET1_1 5
RISET2_1 6
RISET3_1 7
RISET4_1 8
11
IS32LT3124
FLTD
OUT1
OUT2
ISET1
OUT3
ISET2
OUT4
ISET3
CVCC_2
16
4
REN1_2
2
1
Figure 3
EN
HRSET
ERC
RFLTD_2 10
15
14
RISET1_2 5
13
RISET2_2 6
12
RISET3_2 7
ISET4
GND
VICC
REN2_2
3
RISET4_2 8
FLTB
VCC
9
11
IS32LT3124
OUT1
FLTD
OUT2
ISET1
OUT3
ISET2
OUT4
ISET3
16
2
3
15
14
13
12
ISET4
FLTB
GND
9
Typical Application Circuit (Several Devices in Parallel without External PMOS FET)
VBattery
4
RHR
EN
HRSET
ERC
11
RFLTD 10
RISET1
5
RISET2
6
RISET3
7
RISET4
8
Q2
Q3
Q4
Q5
Figure 4
IS32LT3124B/C/E/F
FLTB
FLTD
ISET1
OUT1
OUT2
OUT3
OUT4
2
3
Q1
C1
22nF
15
14
13
12
ISET2
ISET3
ISET4
GND
9
RLED1
1
REN2
PWM Input
R1
RLED2
REN1
VICC
CVICC
0.1µF
RLED3
CVCC
VCC
16
RLED4
D1
* RLED1~RLED4 are necessary
for IS32LT3124E/F If PWM
dimming is required
Typical Application Circuit with Additional Switches driving RISET Individual PWM Dimming (IS32LT3124B/C/E/F only)
When PWM Generator is Far Away from Device
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3
IS32LT3124A/B/C/D/E/F
VBattery
4
RHR
EN
HRSET
ERC
11
RFLTD 10
MCU
RISET1
5
RISET2
6
RISET3
7
RISET4
8
IS32LT3124B/C/E/F
FLTB
FLTD
ISET1
OUT1
OUT2
OUT3
OUT4
2
3
Q1
C1
22nF
15
14
13
12
ISET2
ISET3
ISET4
GND
9
RLED1
1
REN2
Open Drain I/O
R1
RLED2
REN1
VICC
CVICC
0.1µF
RLED3
CVCC
VCC
16
RLED4
D1
* RLED1~RLED4 are necessary
for IS32LT3124E/F If PWM
dimming is required
Figure 5
Typical Application Circuit With Open Drain I/O driving RISET Individual PWM Dimming (IS32LT3124B/C/E/F only)
When PWM Generator is Close to Device
Note 1: The C1 and CVICC are fixed value.
Note 2: For PSM dimming application, high CVCC capacitor value will affect the dimming accuracy. To get better dimming performance,
recommend 0.1µF for it.
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4
IS32LT3124A/B/C/D/E/F
PIN CONFIGURATION
Package
Pin Configuration (Top View)
eTSSOP-16
PIN DESCRIPTION
No.
Pin
Description
IS32LT3124A/D
Device enable pin. Pull low to disable all the outputs. Input
a PWM signal will achieve all channels simultaneous
dimming.
1
EN
2
HRSET
With the external PMOS FET, connect a resistor to VICC pin to set the maximum
working headroom for the current sources.
3
ERC
Gate driver of external PMOS FET to achieve dynamic headroom control.
4
VCC
Raw supply voltage.
Internal fault flag report enable pin. Pull it low to disable
IS32LT3124B/C/E/F fault reporting, the output currents and the response to a
fault remain functional except FLTB is not pulled low.
IS32LT3124A~F
Resistor on this pin to GND sets the maximum output
current for channel OUT1~OUT4.
5~8
ISET1~ISET4
The internal ISET open detection is removed. Therefore,
PWM dimming and current adjust via the resistors of ISETx
IS32LT3124B/C/E/F
pins is feasible. Float the ground terminal of the resistor to
turn off the corresponding output and ground to turn on.
9
GND
Ground pin.
10
FLTD
Resistor on this pin to GND sets the fault reporting output delay time.
11
FLTB
Fault reporting output pin. Active low. Internally pulled up to 4.5V by a resistor. It
is also an input pin (IS32LT3124A/B/D/E only). Pulling it low will disable all output
currents.
12~15
OUT4~OUT1
Output current source for Channel 4~Channel 1.
16
VICC
Regulated LED string voltage from external PMOS FET.
Thermal Pad
Must be connected to GND with sufficient copper plate for heat sink.
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5
IS32LT3124A/B/C/D/E/F
ORDERING INFORMATION
Automotive Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS32LT3124A-ZLA3-TR
IS32LT3124B-ZLA3-TR
IS32LT3124C-ZLA3-TR
IS32LT3124D-ZLA3-TR
IS32LT3124E-ZLA3-TR
IS32LT3124F-ZLA3-TR
eTSSOP-16, Lead-free
2500
Copyright © 2019 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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6
IS32LT3124A/B/C/D/E/F
ABSOLUTE MAXIMUM RATINGS
VCC, VICC, EN, ERC, HRSET
OUT1~ OUT4
ISET1~ISET4, FLTD, FLTB
Operating junction temperature, TA=TJ
Maximum continuous junction temperature, TJ(MAX)
Storage temperature range, TSTG
Power dissipation, PD(MAX)
Junction Package thermal resistance, junction to ambient (4
layer standard test PCB based on JESD 51-2A), θJA
Package thermal resistance, junction to thermal PAD (4 layer
standard test PCB based on JESD 51-8), θJP
ESD (HBM)
ESD (CDM)
-0.3V ~ +42V (Note 3)
-0.3V ~ VVICC+0.3V
-0.3V ~ +7.0V
-40°C ~ +125°C
+150°C
-65°C ~ +150°C
2.12W
47.1°C/W
1.62°C/W
±2kV
±750V
Note 3: The device can operate at 42V continuously subject only to thermal dissipation limit.
Note 4: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Valid are at VCC= 12V, TJ= -40°C ~ +125°C, typical value at 25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
28
V
Power Up Parameter
VCC
Supply voltage range
5
ICC
VCC supply current
RISETx= 20kΩ, VHR= 1V
VUVLO
VCC supply threshold voltage
(when device logic is enabled)
Voltage rising
VUVLO_HY
VCC supply voltage hysteresis
8
10
12
mA
4.3
4.5
4.7
V
0.2
0.25
0.3
V
Shutdown current in normal
mode (IS32LT3124A/D only)
VCC= VICC= 12V, RFLTD= 20kΩ,
EN= Low, TA= 25°C
0.8
1.1
1.3
mA
Shutdown current as FAULTB
pin externally pulled low
(IS32LT3124A/B/D/E only)
VCC= VICC= 12V, EN= High, FLTB=
Low, RFLTD= 20kΩ, TA= 25°C
1.0
1.35
1.5
mA
tON
Startup turn on time
(IS32LT3124A/D only)
IOUT= -150mA, VCC= VICC= 12V,
VEN> 1.23V (Note 5)
20
μs
tSD
The low time of EN pin to
shutdown the IC
(IS32LT3124A/D only)
60
ms
tPC
Power cycle ON (minimum)
0.1
ms
ISD
ISD_FLT
20
38
(Note 5)
Channel Parameter
VISETx
VISET_SC
VISET_SCHY
The ISETx voltage
1
V
ISETx pin short circuit detection
Voltage falling
threshold
100
200
250
mV
ISETx pin short circuit detection
threshold hysteresis
50
100
150
mV
-105
-100
-95
mA
-10
mA
-160
mA
IOUT
Output current per channel
IOUT_R
Output current per channel
range
-150
IOUT_L
Output limit current
-220
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Rev. A, 01/02/2019
RISETx= 20kΩ, VHR= 1V
-190
7
IS32LT3124A/B/C/D/E/F
ELECTRICAL CHARACTERISTICS (CONTINUE)
Valid are at VCC= 12V, TJ= -40°C ~ +125°C, typical value at 25°C, unless otherwise noted.
Symbol
Parameter
Conditions
∆IS/IS
Channel current matching
RISETx= 20kΩ
ILEAK
Leakage current per channel
(IS32LT3124A/D only)
EN= Low, VOUT= 0V, VCC= 28V
VHRSET_MAX The maximum headroom set
VHRSET
-3
(Note 5)
Headroom voltage set accuracy RHR= 2kΩ (Note 6)
VHR
Minimum headroom voltage
IERC
ERC pin current capability
Min. Typ. Max. Unit
0.8
1.0
3
%
1
μA
3.0
V
1.2
V
RISETx= 20kΩ (Note 6)
1.0
RISETx= 13.3kΩ (Note 6)
1.3
(Note 5)
V
40
μA
1.23
V
Fault Protect Parameter
VFLTD
Fault delay pin voltage
tFLTD
Fault delay time
RFLTD= 20kΩ
RFLT
FLTB pull up resistor
(Note 5)
50
VFAULTB
FAULTB pin voltage
Sink current = 1mA
0.4
VFAULTB_H
FAULTB pin high enable
threshold
(IS32LT3124A/B/D/E only)
Voltage rising
VFAULTB_L
FAULTB pin low disable
threshold
(IS32LT3124A/B/D/E only)
Voltage falling
Fault deglitch time
Fault must be present at least this long
to trigger the fault detect
VSCD
OUTx pin short to GND
threshold
Measured at OUTx IS32LT3124A/E/F
voltage falling
IS32LT3124B/C/D
VSCD_HY
OUTx pin short to GND
hysteresis
Measured at OUTx
VOD
OUTx pin open threshold
VOD_HY
tFD
9
9.6
10.5
kΩ
0.6
2.5
20
ms
V
V
40
1
V
60
μs
1.15 1.22 1.30
V
4.5
4.8
5.0
IS32LT3124A/E/F
150
250
350
IS32LT3124B/C/D
150
200
250
Measured at (VICC-VOUTx) decreasing
150
220
300
mV
OUTx pin open hysteresis
Measured at (VICC-VOUTx)
50
120
200
mV
TSD
Thermal shutdown threshold
(Note 5)
165
°C
THY
Over-temperature hysteresis
(Note 5)
25
°C
1.18 1.23 1.28
V
mV
Logic Input EN
VEN_TH
Input enable voltage threshold
VHY
Input hysteresis
fPWM
PWM frequency
Voltage rising
20
40
70
mV
1
kHz
tISET_DLY1
ISET PWM dimming turn on
The time between RISET grounding and
delay time (IS32LT3124B/C/E/F output current reaching 90% maximum
only)
(Note 5)
3
7
11
μs
tISET_DLY2
ISET PWM dimming turn off
The time between RISET floating and
delay time (IS32LT3124B/C/E/F output current reaching 10% maximum
only)
(Note 5)
0.4
4
7
μs
Note 5: Guarantee by design.
Note 6: It is a recommended value to ensure a better line regulation.
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8
IS32LT3124A/B/C/D/E/F
FUNCTIONAL BLOCK DIAGRAM
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Rev. A, 01/02/2019
9
IS32LT3124A/B/C/D/E/F
TYPICAL PERFORMANCE CHARACTERISTICS
102
103
RISET = 20kΩ
Output Current (mA)
102.5
Output Current (mA)
VCC = 12V
RISET = 20kΩ
101.9
TJ = 125°C
102
TJ = 25°C
101.5
TJ = -40°C
101
TJ = 125°C
101.8
TJ = 25°C
101.7
101.6
101.5
101.4
TJ = -40°C
101.3
101.2
100.5
101.1
100
5
8
11
14
17
101
20
2
4
6
Supply Voltage (V)
140
RISET = 20kΩ
120
100
80
60
40
140
RISET = 20kΩ
120
100
80
60
40
RISET = 200kΩ
20
0
RISET = 13kΩ
VCC = 12V
TJ = 25°C
160
Output Current (mA)
Output Current (mA)
Figure 7 IOUT vs. VOUT
180
RISET = 13kΩ
VCC = 12V
TJ = -40°C
160
RISET = 200kΩ
20
0.1
1
2
3
4
5
6
7
8
9
0
10
0.1
1
2
3
Headroom Voltage (V)
160
140
RISET = 20kΩ
120
6
7
180
Output Current (mA)
Output Current (mA)
160
5
8
9
10
110
125
Figure 9 IOUT vs. VHR
RISET = 13kΩ
VCC = 12V
TJ = 125°C
4
Headroom Voltage (V)
Figure 8 IOUT vs. VHR
180
100
80
60
40
RISET = 13kΩ
VCC = 12V
140
120
RISET = 20kΩ
100
80
60
40
RISET = 200kΩ
20
0
10
Output Voltage (V)
Figure 6 IOUT vs. VCC
180
8
RISET = 200kΩ
20
0.1
1
2
3
4
5
6
7
Headroom Voltage (V)
Figure 10 IOUT vs. VHR
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Rev. A, 01/02/2019
8
9
10
0
-40
-25
-10
5
20
35
50
65
80
95
Temperature (°C)
Figure 11 IOUT vs. TJ
10
IS32LT3124A/B/C/D/E/F
200
1.08
VCC = 12V
VHR = 2V
RISET = 5kΩ
OUT1
190
OUT3
185
VCC = 12V
RHR = 2kΩ
TJ = -40°C
1.07
Headroom Voltage (V)
Output Current (mA)
195
OUT2
180
OUT4
175
170
1.06
RISET = 20kΩ
1.05
1.04
1.03
RISET = 200kΩ
1.02
1.01
1.0
165
0.99
160
-40
-25
-10
5
20
35
50
65
80
95
110
0.98
125
5
6
7
10
11
1.08
VCC = 12V
RHR = 2kΩ
TJ = 25°C
1.06
RISET = 20kΩ
1.05
1.04
RISET = 13kΩ
RISET = 200kΩ
1.03
1.02
1.01
1.06
1.02
1.01
0.99
0.98
8
9
10
RISET = 200kΩ
1.03
0.99
7
RISET = 13kΩ
1.04
1.0
6
RISET = 20kΩ
1.05
1.0
5
VCC = 12V
RHR = 2kΩ
TJ = 125°C
1.07
Headroom Voltage (V)
1.07
Headroom Voltage (V)
9
Figure 13 VHR vs. VOUT
Figure 12 IOUT_L vs. TJ
1.08
11
5
6
7
8
9
10
11
Output Voltage (V)
Output Voltage (V)
Figure 15 VHR vs. VOUT
Figure 14 VHR vs. VOUT
15
VOUT = 4V
RHR = 2kΩ
RISET = 100kΩ
1.08
HR3
HR1
1.06
1.04
HR2
HR4
1.02
1
Supply Current (mA)
1.1
Headroom Volrage (V)
8
Output Voltage (V)
Temperature (°C)
0.98
RISET = 13kΩ
VOUT = 4V
RISET = 20kΩ
RFLTD = 20kΩ
12
9
6
3
0.98
0.96
5
10
15
20
25
30
Supply Voltage (V)
Figure 16 VHR vs. VCC
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35
40 42
0
5
10
15
20
25
30
35
40 42
Supply Voltage (V)
Figure 17 ICC vs. VCC
11
IS32LT3124A/B/C/D/E/F
1.8
RFLTD = 20kΩ
EN = Low
1.2
RFLTD = 20kΩ
EN = High
FLTD = Low
1.6
Shutdown Current (mA)
Shutdown Current (mA)
1.4
1
0.8
0.6
0.4
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.2
5
10
15
20
25
30
0
40 42
35
5
10
15
Supply Voltage (V)
Figure 18 ISD vs. VCC for IS32LT3124A/D
Shutdown Current (mA)
Shutdown Current (mA)
VCC = 12V
RFLTD = 20kΩ
EN = Low
0.3
-25
-10
5
20
35
50
65
80
95
110
1.2
0.9
0.6
VCC = 12V
RFLTD = 20kΩ
EN = High
FLTD = Low
0.3
0
-40
125
-25
-10
5
Temperature (°C)
20
35
50
65
80
95
110
125
110
125
Temperature (°C)
Figure 20 ISD vs. TJ for IS32LT3124A/D
Figure 21 ISD_FLT vs. TJ for IS32LT3124A/B/D/E
1.05
14
VCC = 12V
RISET = 20kΩ
RFLTD = 20kΩ
1.04
VCC = 12V
1.03
10
1.02
VISET (V)
Supply Current (mA)
40 42
35
Figure 19 ISD_FLT vs. VCC for IS32LT3124A/B/D/E
0.6
12
30
1.5
0.9
0
-40
25
Supply Voltage (V)
1.5
1.2
20
8
6
1.01
VISET1,VISET3,VISET4
1
0.99
VISET2
0.98
4
0.97
2
0
-40
0.96
-25
-10
5
20
35
50
65
80
Temperature (°C)
Figure 22 ICC vs. TJ
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95
110
125
0.95
-40
-25
-10
5
20
35
50
65
80
95
Temperature (°C)
Figure 23 VISET vs. TJ
12
IS32LT3124A/B/C/D/E/F
4.6
1.25
VCC = 12V
VCC = 12V
EN_H
1.23
UVLO_H
4.5
VUVLO (V)
VEN (V)
4.4
1.21
EN_L
1.19
4.3
UVLO_L
4.2
1.17
4.1
1.15
-40
-25
-10
5
20
35
50
65
80
95
110
4
-40
125
-25
-10
Temperature (°C)
Figure 24 VEN_TH vs. TJ
90
Output Current (mA)
1.24
EN_H
VEN (V)
1.22
1.21
1.2
EN_L
10
25
30
35
0
40 42
0
20
Supply Voltage (V)
Figure 26 VEN_TH vs. VCC
40
60
80
100
80
100
Figure 27 PWM Dimming at 100Hz
100
VCC = 12V
RISET = 20kΩ
PWM Dimming 500Hz
TJ = -40°C, 25°C, 125°C
80
70
60
50
40
80
70
60
50
40
30
30
20
20
10
10
0
20
VCC = 12V
RISET = 20kΩ
PWM Dimming 1kHz
TJ = -40°C, 25°C, 125°C
90
Output Current (mA)
90
Output Current (mA)
125
PWM Duty Cycle (%)
100
0
110
40
1.16
20
95
50
20
15
80
60
1.17
10
65
70
30
5
50
VCC = 12V
RISET = 20kΩ
PWM Dimming 100Hz
TJ = -40°C, 25°C, 125°C
80
1.18
1.15
35
Figure 25 VUVLO vs. TJ
100
1.19
20
Temperature (°C)
1.25
1.23
5
40
60
PWM Duty Cycle (%)
Figure 28 PWM Dimming at 500Hz
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80
100
0
0
20
40
60
PWM Duty Cycle (%)
Figure 29 PWM Dimming at 1kHz
13
IS32LT3124A/B/C/D/E/F
100
80
70
60
50
40
80
70
60
50
40
30
30
20
20
10
10
0
0
20
PSM = 12V, 300Hz
RISET = 20kΩ
TJ = -40°C, 25°C, 125°C
90
Output Current (mA)
90
Output Current (mA)
100
PSM = 12V, 100Hz
RISET = 20kΩ
TJ = -40°C, 25°C, 125°C
40
60
80
100
0
0
20
40
PSM Duty Cycle (%)
VCC = 12V
RFLTD = 20kΩ
TJ = -40°C
LED Open Fault
100
Figure 31 PSM Dimming at 300Hz
VFLTB
5V/Div
VOUT
5V/Div
VOUT
5V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (4ms/Div)
VCC = 12V
RFLTD = 20kΩ
TJ = 25°C
LED Open Fault
Time (4ms/Div)
Figure 32 tFLTD
VFLTB
5V/Div
80
PSM Duty Cycle (%)
Figure 30 PSM Dimming at 100Hz
VFLTB
5V/Div
60
VCC = 12V
RFLTD = 20kΩ
TJ = 125°C
LED Open Fault
VOUT
5V/Div
Figure 33 tFLTD
VCC = 12V
RFLTD = 0Ω
TJ = -40°C
LED Open Fault Recover
VFLTB
2V/Div
VOUT
5V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (4ms/Div)
Time (20µs/Div)
Figure 34 tFLTD
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Figure 35 tFD
14
IS32LT3124A/B/C/D/E/F
VCC = 12V
RFLTD = 0Ω
TJ = 25°C
LED Open Fault Recover
VCC = 12V
RFLTD = 0Ω
TJ = 125°C
LED Open Fault Recover
VFLTB
2V/Div
VFLTB
2V/Div
VOUT
5V/Div
VOUT
5V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (20µs/Div)
Time (20µs/Div)
Figure 36 tFD
Figure 37 tFD
VCC = 12V
RISET = 20kΩ
TJ = -40°C
VCC = 12V
RISET = 20kΩ
TJ = -40°C
VEN
1V/Div
VEN
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (2µs/Div)
Figure 38 PWM Off Delay Time for IS32LT3124A/D
Time (2µs/Div)
Figure 39 PWM On Delay Time for IS32LT3124A/D
VCC = 12V
RISET = 20kΩ
TJ = 25°C
VCC = 12V
RISET = 20kΩ
TJ = 25°C
VEN
1V/Div
VEN
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (2µs/Div)
Figure 40 PWM Off Delay Time for IS32LT3124A/D
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Time (2µs/Div)
Figure 41 PWM On Delay Time for IS32LT3124A/D
15
IS32LT3124A/B/C/D/E/F
VCC = 12V
RISET = 20kΩ
TJ = 125°C
VCC = 12V
RISET = 20kΩ
TJ = 125°C
VEN
1V/Div
VEN
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (2µs/Div)
Time (2µs/Div)
Figure 42 PWM Off Delay Time for IS32LT3124A/D
Figure 43 PWM On Delay Time for IS32LT3124A/D
VCC = 12V
RISET = 20kΩ
TJ = -40°C
VCC = 12V
RISET = 20kΩ
TJ = -40°C
Floating
RISET Ground
Terminal
1V/Div
Floating
RISET Ground
Terminal
1V/Div
Grounded
Grounded
IOUT
50mA/Div
IOUT
50mA/Div
Time (4µs/Div)
Time (4µs/Div)
Figure 44 ISET PWM Off Delay Time for IS32LT3124B/C/E/F
Figure 45 ISET PWM On Delay Time for IS32LT3124B/C/E/F
Note: Reference Figure 4 and 5
Note: Reference Figure 4 and 5
VCC = 12V
RISET = 20kΩ
TJ = 25°C
VCC = 12V
RISET = 20kΩ
TJ = 25°C
Floating
Floating
RISET Ground
Terminal
1V/Div
Grounded
IOUT
50mA/Div
RISET Ground
Terminal
1V/Div
Grounded
IOUT
50mA/Div
Time (4µs/Div)
Time (4µs/Div)
Figure 46 ISET PWM Off Delay Time for IS32LT3124B/C/E/F
Figure 47 ISET PWM On Delay Time for IS32LT3124B/C/E/F
Note: Reference Figure 4 and 5
Note: Reference Figure 4 and 5
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IS32LT3124A/B/C/D/E/F
VCC = 12V
RISET = 20kΩ
TJ = 125°C
VCC = 12V
RISET = 20kΩ
TJ = 125°C
Floating
Floating
RISET Ground
Terminal
1V/Div
Grounded
IOUT
50mA/Div
RISET Ground
Terminal
1V/Div
Grounded
IOUT
50mA/Div
Time (4µs/Div)
Time (4µs/Div)
Figure 48 ISET PWM Off Delay Time for IS32LT3124B/C/E/F
Figure 49 ISET PWM On Delay Time for IS32LT3124B/C/E/F
Note: Reference Figure 4 and 5
Note: Reference Figure 4 and 5
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = -40°C
Without PMOS
PSM
5V/Div
PSM
5V/Div
VOUT
10V/Div
VOUT
10V/Div
VISET
1V/Div
VISET
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (10µs/Div)
Time (10µs/Div)
Figure 50 PSM On
Figure 51 PSM On
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 25°C
Without PMOS
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 25°C
With PMOS
PSM
5V/Div
PSM
5V/Div
VOUT
10V/Div
VOUT
10V/Div
VISET
1V/Div
VISET
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (10µs/Div)
Figure 52 PSM On
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RISET = 20kΩ
PSM = 12V, 100Hz
TJ = -40°C
With PMOS
Time (40µs/Div)
Figure 53 PSM On
17
IS32LT3124A/B/C/D/E/F
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 125°C
With PMOS
PSM
5V/Div
PSM
5V/Div
VOUT
10V/Div
VOUT
10V/Div
VISET
1V/Div
VISET
1V/Div
IOUT
50mA/Div
Time (10µs/Div)
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 125°C
Without PMOS
IOUT
50mA/Div
Time (20µs/Div)
Figure 54 PSM On
PSM
5V/Div
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = -40°C
Without PMOS
Figure 55 PSM On
PSM
5V/Div
VOUT
10V/Div
VOUT
10V/Div
VISET
1V/Div
VISET
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (40µs/Div)
Time (40µs/Div)
Figure 57 PSM Off
Figure 56 PSM Off
PSM
5V/Div
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 25°C
Without PMOS
PSM
5V/Div
VOUT
10V/Div
VOUT
10V/Div
VISET
1V/Div
VISET
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (40µs/Div)
Figure 58 PSM Off
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RISET = 20kΩ
PSM = 12V, 100Hz
TJ = -40°C
With PMOS
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 25°C
With PMOS
Time (40µs/Div)
Figure 59 PSM Off
18
IS32LT3124A/B/C/D/E/F
PSM
5V/Div
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 125°C
Without PMOS
PSM
5V/Div
VOUT
10V/Div
VOUT
10V/Div
VISET
1V/Div
VISET
1V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (40µs/Div)
RISET = 20kΩ
PSM = 12V, 100Hz
TJ = 125°C
With PMOS
Time (40µs/Div)
Figure 60 PSM Off
VEN
2V/Div
VCC = 12V
RISET = 20kΩ
TJ = -40°C
Figure 61 PSM Off
VEN
2V/Div
VISET
1V/Div
VISET
1V/Div
VFLTB
2V/Div
VFLTB
2V/Div
IOUT
50mA/Div
IOUT
50mA/Div
Time (10ms/Div)
Figure 62 tSD for IS32LT3124A/D
VEN
2V/Div
VCC = 12V
RISET = 20kΩ
TJ = 25°C
Time (10ms/Div)
Figure 63 tSD for IS32LT3124A/D
VCC = 12V
RISET = 20kΩ
TJ = 125°C
VISET
1V/Div
VFLTB
2V/Div
IOUT
50mA/Div
Time (10ms/Div)
Figure 64 tSD for IS32LT3124A/D
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19
IS32LT3124A/B/C/D/E/F
APPLICATION INFORMATION
The IS32LT3124 is a 4-channel linear constant current
regulator capable of sourcing 150mA per channel. The
device integrates one EN input control and four output
currents with individual current set resistors; one for
each of the four output current channels. The device
can operate with a Power Supply Modulation (PSM)
input at the VCC pin input. To minimize device thermal
stress, an optional external shunt resistor and PMOS
FET can be driven by the IS32LT3124 to share the
power dissipation. FLTB pin can be used in a parallel
combination to disable multiple IS32LT3124A/B/D/E
devices once a fault condition is detected by any one
of the devices (One-Fail-All-Fail).
the ISET open fault will be ignored and the channel will
be recognized as unused.
UNDER VOLTAGE LOCKOUT (UVLO)
EN PIN OPERATION
IS32LT3124 features an under voltage lockout (UVLO)
function for the VCC pin. This is an internally fixed
value and cannot be adjusted. The device is enabled
when the VCC voltage rises to exceed VUVLO (Typ.
4.5V), and disabled when the VCC voltage falls below
(VUVLO-VUVLO_HY) (Typ. 4.25V). For the IS32LT3124A/D,
the EN pin can be used to set additional UVLO via a
resistor divider. Please refer to the EN PIN
OPERATION section for more details.
IS32LT3124A/D:
OUTPUT CURRENT SETTING
The regulated LED current (up to 150mA) from each
channel is individually set by its corresponding
reference resistor (RISETx). The programming resistors
may be computed using the following Equation (1):
RISET
V
ISET 2000
I OUT
(1)
(13.3kΩ≤RISET≤200kΩ) and VISET=1V (Typ.)
It is recommend that RISETx be a 1% accuracy resistor
with good temperature characteristic to ensure stable
output current.
The current outputs can be connected in parallel for a
combined 600mA or can be left unused as required.
Several channels combined in parallel will have the
same current accuracy as the independent channel.
In case of some channels are unused, please follow
Table 2 to configure the corresponding ISETx and
OUTx pins.
RISET1
RISET2
RISET3
5
6
7
8
OUT1
ISET1
OUT2
ISET2
OUT3
ISET3
OUT4
ISET4
15
14
13
12
IS32LT3124B/C/E/F
GND
Figure 65
9
IS32LT3124B/C/E/F Unused Channel Configuration
(OUT4 Unused)
EN is the device enable pin. The EN voltage must be
higher than VEN_TH to enable all outputs and lower than
(VEN_TH-VHY) to disable them.
The EN pin of the IS32LT3124A/D can accept a PWM
signal to implement simultaneous dimming of all LED
strings. The average LED current for each channel can
be computed using the following Equation (2).
I LED DPWM
VISET
2000
RISET
(2)
DPWM is PWM duty cycle and VISET=1V (Typ.).
So as to guarantee a reasonably good dimming effect,
the recommended PWM frequency range is 100Hz ~
1kHz. Driving the EN pin with a PWM signal can
effectively adjust the LED intensity. The PWM signal
voltage levels must meet the EN pin input voltage
levels, (VEN_TH-VHY) and VEN_TH. Note: because of the
40µs (typ.) fault deglitch time tFD, the PWM on-time
should be greater than 40us to avoid undetermined
fault response.
The IC has an internal fixed VCC UVLO set at VUVLO,
4.5V (Typ.). However, it may be desirable to externally
set UVLO to track the number of LED’s used in the
string. For PSM dimming application, the higher UVLO
will track the PSM off time to get more accurate PSM
dimming. The EN pin can be used to set a VCC under
voltage lockout threshold via a resistor divider.
Table 2 Unused Channel Configuration
Unused ISETx
Unused OUTx
Device
Pins
Pins
IS32LT3124A/D
Floating
Connect to VICC
Connected to
IS32LT3124
Floating
used OUT (refer
B/C/E/F
to Figure 65)
Note: for IS32LT3124A/D, when the ISET pin is
floating and the corresponding OUT pin is tied to VICC,
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Figure 66
EN Pin Set External UVLO
The UVLO threshold voltage can be computed using
the following Equation (3):
20
IS32LT3124A/B/C/D/E/F
VCC _ UVLO VEN _ TH
REN 1 REN 2
REN 2
(3)
IS32LT3124B/C/E/F:
The EN pin is fault reporting enable pin, when pulled
low to disable fault reporting, the output currents and
the internal IC fault action operate normally but no fault
output is generated. The EN voltage is higher than
VEN_TH to enable fault reporting (FLTB low output) and
lower than (VEN_TH-VHY) to disable all fault reporting
(FLTB low output).
In some applications, the IS32LT3124A/B/C/D/E/F with
a resistor divider from VCC as Figure 66, helps prevent
false LED open detection due to the LED string losing
its headroom voltage, such as when VCC rises up from
zero during power up or PSM dimming. The
recommended VCC_UVLO setting level is:
VCC _ MIN VCC _ UVLO VOUT _ MAX VHRSET
VCC
IS32LT3124
ERC
HRSET
3
DYNAMIC HEADROOM CONTROL (DHC) AND
THERMAL CONSIDERATIONS
The power dissipation of a linear constant current LED
driver depends on the ratio of the output and input
voltages. When the input and output voltages are
determined, an increase in output current will increase
power dissipation on the driver IC and it can be
calculated by the following Equation:
(5)
Where, VHR is the headroom voltage, which is the
voltage drop on the OUTx pin. Due to the limited driver
IC power rating, a typical linear constant current LED
driver cannot be used for high current applications. To
solve this power dissipation issue, IS32LT3124
features a Dynamic Headroom Control (DHC) function
which splits the power dissipation among the driver IC
and external components to significantly minimize the
driver IC thermal. This enables the IS32LT3124 to
support up to 600mA total output current with
acceptable heat, independent of the output to input
voltage ratio.
VDROP
R1
2
C1
22nF
RHR
Must be >5V
VICC
16
VHR_MIN
(4)
Where, VCC_MIN is the minimum VCC voltage, VOUT_MAX
is the maximum forward voltage of 4 LED strings and
VHRSET is the setting minimum headroom voltage (refer
to DYNAMIC HEADROOM CONTROL section).
PIC (VCC VOUT ) I OUT VHR I OUT
The DHC can be configured into two modes: Shunt
Regulator mode and Series Regulator mode. The
Series Regulator mode is recommended for the
application of ≤300mA total output current and the
Shunt Regulator mode is good for >300mA application.
The basic circuits of both modes are the same
however R1 value decides the operating mode. To
optimize the stability of the PMOS FET control loop,
please use the fixed value for them: C1=22nF and
CVICC=0.1µF.
CVICC
0.1µF
OUT1 15 VOUT_MAX
OUT2 14
OUT3 13
OUT4 12
GND
9
Figure 68
DHC Operating
Series Regulator Mode:
Choose 1kΩ value for R1 and the DHC circuit will
operate in Series Regulator mode. The integrated
circuit compares the minimum headroom voltage of all
four output channels against the headroom setting
VHRSET, which is set by the resistor RHR from the
HRSET and VICC pins, and dynamically drives the
external power PMOS FET to maintain this minimum
headroom voltage always equal to VHRSET. As Figure
69 shows, the minimum headroom voltage will appear
on the channel with the maximum LED string forward
voltage. Therefore, the output voltage of the Series
Regulator, VVICC, can be calculated by the Equation (6)
and (7):
VVICC VOUT _ MAX VHRSET
(6)
1V
VHRSET RHR
2000
(7)
Where, VOUT_MAX is the maximum voltage of four OUTx
pins.
Figure 67
DHC Circuit
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Rev. A, 01/02/2019
According to Equation (6), once the LED strings are
determined and the input voltage is sufficient higher
than VVICC, the VVICC is constant if RHR is fixed. No
matter how high the input voltage is, the headroom
voltage of each channel is constant all the time, so the
21
IS32LT3124A/B/C/D/E/F
power dissipation on IS32LT3124 is constant as well
(ICC current is negligible and ignored in following
calculation). However, it can be programmed by the
VHRSET setting; the higher VHRSET the larger power
dissipation on IS32LT3124. The remaining power
dissipation is dropped on the external PMOS FET.
Their power consumption can be calculated by:
splits it into two areas: constant headroom area and
headroom increasing area.
In the Constant Headroom Area, the DHC circuit
regulates the minimum headroom voltage equal to
VHRSET, same as the Series Regulator mode. So the
IS32LT3124 power dissipation is constant:
4
4
P3124 (VVICC VOUTx ) I OUTx
(8)
PPMOS (VCC VVICC ) I TOT
(9)
P3124 (VVICC VOUTx ) I OUTx
x 1
Where, ITOT is the total current of all output channels.
While the PMOS FET and R1 share the remaining
power dissipation which will vary following the input
voltage. Their power dissipation in the Constant
Headroom Area can be calculated by:
PR1
Power Dissipation
Figure 69
PPMOS ( I TOT
(VCC VVICC ) 2
R1
(11)
VCC VVICC
) (VCC VVICC )
R1
(12)
The power dissipation of the PMOS FET peaks at the
center point of (VTR-VVICC) and decreases to zero at
VTR. The transition point VTR can be adjusted by the R1
value:
Power Dissipation Distribution in Series Regulator Mode
Shunt Regulator Mode:
In the Series Regulator mode, the headroom voltage is
constant however the external PMOS FET must
support any excess voltage. When the total output
current exceeds 300mA, the V×I power dissipation on
the PMOS FET may be excessive. To prevent thermal
run away, the Shunt Regulator mode could be
considered. Choose a proper value (lower than 1KΩ)
for R1, DHC circuit will operate in Shunt Regulator
mode which manages the power dissipation among
the IS32LT3124, external PMOS FET, and the shunt
resistor R1. R1 sharing the power dissipation will
significantly minimize the power dissipation on the
PMOS FET.
VTR VVICC R1 I TOT
(13)
Beyond the transition line VTR is the Headroom
Increasing Area. DHC is no longer effective since the
PMOS FET is off. PMOS FET has no power
dissipation anymore and the power dissipation is solely
shared by IS32LT3124 and R1. The power dissipation
of R1 becomes constant while the power dissipation of
the IS32LT3124 starts to increase following the input
voltage. Their power dissipation in the Headroom
Increasing Area can be calculated by:
4
P3124 (VCC I TOT R1 VOUTx ) I OUTx
(14)
x 1
2
PR1 I TOT R1
PPMOS 0
(15)
(16)
In the Headroom Increasing Area, the system relies on
the thermal shutdown protection feature of the
IS32LT3124. Select a proper R1 value so the Constant
Headroom Area covers the desired operating voltage
range. For instance, the required operating voltage
range is 9V~16V. The VICC should be set below 9V
and set VTR above 16V.
Power Dissipation
Figure 70
(10)
x 1
Power Dissipation Distribution in Shunt Regulator mode
As Figure 70 shows, the power dissipation has
different distribution in different areas. When the input
voltage is higher than VVICC, the transition line (VTR)
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Lumissil has a downloadable Excel spread sheet to
calculate the power dissipation of these key
components: IS32LT3124, PMOS FET and shunt
resistor. In the Shunt Regulator mode, the shunt
resistor R1 sustains plenty of power dissipation at high
input voltage. Please make sure the R1 has sufficient
power rating to avoid thermal stress of the resistor.
22
IS32LT3124A/B/C/D/E/F
Several large package resistors in parallel should be
used for R1.
EXTERNAL PMOS FET SELECT (OPTIONAL)
The PMOS FET must be chosen with its drain voltage
rating VDS greater than the Transient Voltage
Suppressor (TVS) clamp voltage of the load dump
protection. The IS32LT3124 integrates a 15V
overvoltage protect circuit to clamp the voltage
between VCC and ERC pins for PMOS FET gate
protection purpose. So the gate to source maximum
voltage rating VGS of the PMOS FET should be greater
than 15V to avoid accidental damage. And its current
rating should be greater than the total current of all
channels. Moreover, the static drain to source on
resistance (RDS_ON) of the PMOS FET should be
considered. It affects the minimum voltage drop across
VCC to VICC:
VDROP _ MIN VCC _ MIN VVICC (17)
VDROP_ MIN RDS_ON IOUT1 IOUT2 IOUT3 IOUT4 (18)
Where, VCC_MIN is the minimum input voltage.
In addition, because the PMOS FET doesn’t have an
over temperature protection mechanism, the power
rating of the PMOS FET should be carefully
considered to sustain the maximum power dissipation
on it. A PMOS FET with a big thermal PAD and low
thermal resistance is preferred, such as a D-PAK or
SOT-223 package. When several devices are
connected in parallel to share one PMOS FET (as
Figure 2), all the output currents of those devices
without PMOS FET should be calculated together as
the total current thru the PMOS FET.
1V
RHR
VOUT _ MAX 5V
2000
(20)
Therefore in low LED string voltage application, e.g.
one RED LED with around 2V forward voltage, some
appropriate value power resistors in series with LED
strings should be used to increase the maximum
voltage of four OUTx pins. The power resistor value RP
can be calculated by:
VVICC VOUT _ MAX
I OUT _ X
RP
5V VOUT _ MAX
I OUT _ X
(21)
Where, VOUT_MAX is the maximum voltage of four OUTx
pins without any power resistor and IOUT_X is the
current of this channel.
Note: the approach of adding the series power resistor
is only available for IS32LT3124A/E/F versions. The
IS32LT3124B/C/D using the series power resistor
would falsely trigger short fault protection and latched
all outputs off. So IS32LT3124B/C/D only can drive the
LED
string
with
the
forward
voltage
>
(VSCD_MAX+VSCD_HY).
DYNAMIC HEADROOM CONTROL (DHC) SHARING
The DHC function is not necessary for the IS32LT3124
in low current applications. Such as when the total
output current is much lower than 300mA. If not used,
the external PMOS FET can be omitted and VICC
should be tied to VCC pin, and leave HRSET and ERC
pins floating (as Figure 3).
To save the cost and PCB space in some application,
several devices can be connected in parallel to share
one PMOS FET (as Figure 2). This scheme is
available for both the Series Regulator and the Shunt
Regulator modes. The IC connected to system voltage
(Supervisor) must connect one output channel (with its
ISET pin left floating) to the HRSET pin of the next
device (with ECR pin floating and same value RHR as
the supervisor). The supervisor IC’s DHC circuit will
manage the power dissipation of the devices without
PMOS FET along with itself. In this way, the power
dissipation on the PMOS FET and R1 should be
carefully considered to make sure its junction
temperature won’t exceed its maximum rating in
extreme ambient temperature. This approach is
suitable for applications with low per channel current.
HEADROOM SETTING
POWER SUPPLY MODULATION (PSM) DIMMING
As previously stated, the headroom voltage is set by
the resistor RHR from the HRSET and VICC pins:
The IS32LT3124 can support Power Supply
Modulation (PSM), which implements LED dimming by
pulse width modulated on the power supply rail. The
IS32LT3124 closed loop stability is not affected by
PSM operation with or without an external PMOS FET.
The HRSET and ERC controls can respond within the
tPC period when the supply VCC threshold voltage to
properly drive and bias the PMOS FET in a linear
fashion. To get better dimming linearity, the
recommended PSM frequency should be in the range
of 100Hz to 300Hz (200Hz Typ.) and the input
capacitor, CVCC, should be low value (0.1uF typical) to
ensure rapid discharge during PSM low period.
1V
VHRSET RHR
2000
(19)
The IS32LT3124 internally limits the maximum VHRSET
to 3.0V (typical) to ensure reasonable thermal on the
IS32LT3124. A headroom voltage setting of 1.5V~2.5V
is recommended for most application.
To maintain the normal operation of the internal
detection circuit and the dynamic head room control,
the VICC voltage must be set above 5V, otherwise the
DHC circuit will be abnormal and the VHR_MIN cannot be
maintained at set value.
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23
IS32LT3124A/B/C/D/E/F
FAULT REPORTING OPERATION
For robust system reliability, the IS32LT3124
integrates the detection circuitry to protect various fault
conditions and report the fault by the FLTB pin which
can be monitored by an external host. The FLTB pin is
internally pulled up to 4.5V by a resistor RFLT and so it
can be left floating, or unconnected. The FLTB pin will
go low when the device enables fault detection and
detects a fault condition such as LED string open,
short to GND, thermal shutdown, or ISET pin
open/short (refer to Table 4). For IS32LT3124B/C/E/F,
the fault detection and actions are always active,
however the FLTB reporting is not active until EN pin
voltage rise above VEN_TH. For the IS32LT3124A/D,
ISET open fault detection is disabled when the voltage
of the OUTx pins are not floating or grounded, unused
OUTx pins should be tied to VICC for unused purpose.
In PSM dimming application, with a fault condition, the
fault reporting will be reset as VCC voltage goes low.
So the external fault reporting monitor should checking
cycle by cycle, and keep at least 100µs monitor
blanking time after VCC rising up to prevent some
spurious fault as shown in Figure 71.
will be limited to a minimum value, 40µs. Except for
being grounded, the RFLTD value must be ≥ 5kΩ.
FLTB PARALLEL INTERCONNECTION
FLTB is a fault reporting output pin and it also is an
input pin (IS31FL3124A/B/D/E only). Externally pulling
FLTB pin low will disable all the output channels. For
LED lighting systems which require the complete
lighting system be shutdown when a fault is detected,
the FLTB pin can be used in a parallel connection with
multiple IS32LT3124A/B/D/E devices as shown in
Figures 2 and 3. A detected fault output by any device
will pull low the FLTB pins of the other parallel
connected devices and simultaneously turn them off.
This satisfies the “One-Fail-All-Fail” operating
requirement.
LED STRING OPEN DETECTION
Detection of an open-load condition occurs when the
measured voltage across any one of the four OUTx
pins to VICC is lower than VOD. When this condition is
present for longer than the fault deglitch tFD, then
IS32LT3124A/D:
It turns off all of the other channels. The FLTB pin goes
low after fault delay time.
IS32LT3124B/E:
It turns off all of the other channels. If VEN>VEN_TH, the
FLTB pin goes low after fault delay time.
IS32LT3124C/F:
Figure 71
External Fault Reporting Monitor During PSM Dimming
FAULT REPORTING DELAY TIME SETTING
The IS32LT3124 supports programmable fault
reporting delay time, as shown in Table 3. A fault
reporting delay time is used to introduce a delay to the
FLTB output signal when detecting a device fault
condition. This delay is meant to avoid detecting and
reporting a spurious fault.
Table 3 Fault Delays
It keeps all the other channels normal working. If
VEN>VEN_TH, the FLTB pin goes low after fault delay
time.
The device recovers after deglitch time tFD as removal
of the open condition and FLTB goes back high.
LED STRING SHORT-CIRCUIT DETECTION
The LED string short circuit is detected if the measured
voltage across any of OUTx pin drops below OUTx pin
short to GND threshold, VSCD.
IS32LT3124B/C/D:
FLTD Pin State
Report Fault Delay Time
GND
40µs
RFLTD= 5kΩ
4.65ms
RFLTD= 20kΩ
9.60ms
RFLTD= 250kΩ
85.5ms
Floating
340ms
The delay time can be computed using the following
Equation (22):
t FLTD (ms ) 3.3 RFLTD 10 3
4
(22)
Note: When FLTD pin is grounded, the fault delay time
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After VEN>VEN_TH, when any of OUTx pin voltage drops
below VSCD (typical 4.8V) and is present for longer than
the fault deglitch time tFD, IS32LT3124B/D will turn off
all the other channels and reserve 4mA in faulty
channel for recovery detection purpose, while all
channels of IS32LT3124C will continue sourcing
current. And the FLTB pin goes low after fault delay
time. The channel recovers after deglitch time tFD upon
removal of the short condition and FLTB goes back
high.
Since VSCD of IS32LT3124B/C/D is higher than one
LED forward voltage, it only can drive the LED string
with the forward voltage > (VSCD_MAX+VSCD_HY) then it is
possible to detect both LED string short (as Figure
72-1) and single LED in multi-LEDs string short
24
IS32LT3124A/B/C/D/E/F
detection with appropriate forward voltage LEDs (as
Figure 72-2).
VSCD=4.8V
Since VSCD of IS32LT3124A/E/F is lower than one LED
forward voltage, it can only detect OUTx short to GND
condition, as Figure 73.
OUTx
VSCD=1.22V
OUTx
(1)
IS32LT3124B/C/D
Whole
String
Shorted
VSCD=4.8V
Figure 73
OUTx
(2)
IS32LT3124B/C/D
Figure 72
IS32LT3124A/E/F
Whole
String
Shorted
IS32LT3124A/E/F LED Short Detection
ISET OVER CURRENT OR SHORT DETECTION
Single
LED
Shorted
IS32LT3124B/C/D LED Short Detection
To achieve single LED short detection, please ensure
that a single LED short can reduce the LED string
voltage below VSCD_MIN. So the LED string voltage must
be set within the range of:
(VSCD _ MIN V f _ MIN ) VSTRING VSCD _ MAX
(23)
Where, VSCD_MAX and VSCD_MIN is the maximum and
minimum value of the OUTx short detect threshold,
Vf_MIN is the minimum forward voltage of the LED.
IS32LT3124A:
After the device being enabled (VEN>VEN_TH), when any
of OUTx pin voltage drops below VSCD (typical 1.22V)
and is present for longer than the fault deglitch time tFD,
it will turn off all the other channels. The FLTB pin goes
low after fault delay time. The channel recovers after
deglitch time tFD upon removal of the short condition
and FLTB goes back high.
IS32LT3124E:
When any OUTx pin voltage drops below VSCD (typical
1.22V) for longer than the fault deglitch time tFD, it turns
off all the other channels. If VEN>VEN_TH, the FLTB pin
goes low after fault delay time. The device recovers
after deglitch time tFD upon removal of the short
condition and FLTB goes back high.
IS32LT3124F:
When any OUTx pin voltage drops below VSCD (typical
1.22V) for longer than the fault deglitch time tFD, all
channels will continue sourcing current. If VEN>VEN_TH,
the FLTB pin goes low after fault delay time. The
channel recovers after deglitch time tFD upon removal
of the short condition and FLTB goes back high. Note:
An LED short will cause a larger headroom voltage on
the faulty channel that may significantly increase the
power dissipation on IS32LT3124F, especially in high
output current applications.
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The device is protected from an output overcurrent
condition caused by ISETx pins. When a too low value
resistor is connected to any ISET pin but pin voltage
still is above VISET_SC (typical 0.2V), the corresponding
channel current will be internally limited at 190mA
(typical). If an excessive low value resistor is
connected or accidental short circuit to pull ISETx pin
voltage below 0.2V, the corresponding channel will be
turned off with fault reporting after fault delay time tFLTD
and IS32LT3124A/B/D/E will turn off the other
channels as well, while IS32LT3124C/F will keep the
other channels operating normally. The device
recovers after deglitch time tFD upon removal of the
fault condition and FLTB goes back high.
ISET OPEN DETECTION AND INDIVIDUAL PWM
DIMMING
IS32LT3124A/D:
If ISETx pin is open and VEN > VEN_TH, all output
channels will be turned off and FLTB will go low after
fault delay time tFLTD to report fault condition. The
device recovers after deglitch time tFD upon removal of
the open condition and FLTB goes back high. Due to
this protection, IS32LT3124A/D cannot support
individual ISETx PWM dimming. However, if the ISET
pin is floating and the corresponding OUT pin is tied to
VICC, the ISET open fault will be ignored and the
channel will be recognized as unused.
IS32LT3124B/C/E/F:
In these two devices, the ISETx pin open detection is
removed, then ISETx pin is able to implement the
individual PWM dimming to the corresponding output
channel. When ISETx pin is floating, the corresponding
OUTx is turned off. Ground it via a resistor (RISETx) to
enable the output source. Refer to Figure 4 and 5.
When the PWM generator is far away from the device,
use Figure 4 approach to prevent noise coupling due
to the long trace. When the PWM generator is close to
the device, use open drain structure I/O of the MCU to
directly control each ISETx pin. Since Push-pull I/Os
will force current into ISETx pins, only open drain
structure I/Os are acceptable.
With this individual PWM dimming, the LED current is
inversely proportional to the source PWM duty cycle
25
IS32LT3124A/B/C/D/E/F
(due to the open drain inversion). That is, when the
source PWM signal is 100% duty cycle, the output
current is minimum, ideally zero, and when the PWM
signal is 0% duty cycle, the output current is maximum.
LED current is computed using the following Equation
(24).
2.5
VISET
2000
RISET
(24)
eTSSOP-16
Note: because of the 40µs (typ.) fault deglitch time tFD,
the PWM on-time should be greater than 40us to avoid
undetermined fault response.
THERMAL SHUTDOWN
In the event that the die temperature exceeds 165°C,
all four output channels will go to the ‘OFF’ state and
the FLTB pin will go low if VEN > VEN_TH. At this point,
the IC should begin to cool off. Any attempt to enable
one or all four of the channels before the IC has cooled
to < 140°C will be ignored by the IC.
2
1.5
1
0.5
0
-40
-25
-10
THERMAL CONSIDERATIONS
When operating the IS32LT3124 at high ambient
temperatures, or when driving high load current, care
must be taken to avoid exceeding the package power
dissipation limits. The major power components are IC,
PMOS FET and shunt resistor. Therefore their
temperature should be carefully calculated and
considered.
In the application with the DHC function, the power
dissipation of these three components is described in
the “DYNAMIC HEADROOM CONTROL (DHC) AND
THERMAL CONSIDERATIONS” section.
In the application without the DHC function, the power
dissipation on the IS32LT3124 can be computed by:
4
P3124 VCC I CC (VCC VOUTx ) I OUTx
(25)
x 1
The maximum power dissipation of the IS32LT3124
and PMOS FET can be calculated using the following
Equation (26):
PD ( MAX )
TJ ( MAX ) TA
125C 25C
2.12W
47.1C / W
Figure 74, shows the power derating of the
IS32LT3124 on a JEDEC boards (in accordance with
JESD 51-5 and JESD 51-7) standing in still air.
Power Dissipation (W)
I LED (1 DPWM )
PD ( MAX )
5
20
35
50
65
80
95
110 125
Temperature (°C)
Figure 74
IS32LT3124 Dissipation Curve
The PMOS FET maximum power rating can be
achieved by the same calculation method.
In the Shunt Regulator mode, R1 will share quite a lot
power dissipation. Its package power rating should be
sufficient to prevent heat run away.
When designing the Printed Circuit Board (PCB) layout,
double-sided PCB with a large copper area on each
side of the board directly under the IS32LT3124
(eTSSOP-16 package), PMOS FET and the shunt
resistor must be used. Multiple thermal vias, as shown
in Figure 75, will help to conduct heat from the
exposed pad of the IS32LT3124, PMOS FET and
shunt resistor to the copper on each side of the board.
The thermal resistance can be further reduced by
using a metal substrate or by adding a heat sink. To
avoid heat buildup, these power components should
be spread out on the PCB board with some distance.
(26)
JA
Where, TJ(MAX) is the maximum operating junction
temperature which can be found from their datasheets,
TA is the ambient temperature, and θJA is the junction
to ambient thermal resistance. P3124 should not exceed
PD(MAX).
For IS32LT3124, the recommended maximum
operating junction temperature, TJ(MAX), is 125°C and
so maximum ambient temperature is determined by
the junction to ambient thermal resistance, θJA.
Therefore the maximum power rating at TA= 25°C is:
Figure 75
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Board Via Layout For Thermal Dissipation
26
IS32LT3124A/B/C/D/E/F
Table 4 DIFFERENT FAULT ACTION OF 3 TYPES
EN
Voltage
VEN_TH
IS32LT3124A/D
Fault Type
Fault Condition
Faulty
Channel
Other
Channels
IS32LT3124B/E
FLTB
Faulty Channel
Other
Channels
IS32LT3124C/F
FLTB
Faulty
Channel
Other
Channels
Auto Recovery
FLTB
ISETx open
ISETx pin current
close to zero
Off
Enabled
Off
Enabled
ISETx pin current
goes back high
ISETx short
ISETx pin voltage
(VISET_SC+VISET_SCHY)
LED string
open
(VICC-VOUTx)(VOD+VOD_HY)
VOUTx>(VSCD+VSCD_HY)
TJ
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