ASNT2111-KMF

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT2111-KMF Programmable CDR DMUX 1-to-2 1:2 demultiplexer (DMUX) with integrated full-rate CDR  Input data range from 18Gb/s to 36Gb/s  NRZ input data format   CML compliant differential input and output high-speed data and clock interfaces 1.3V CMOS 3-wire interface for digital controls  LVDS or CML compliant input reference clock interface  Full-rate clock and retimed data output for 1:1 CDR operation  Half-rate data outputs with toggle synchronization functionality  Signal inversion and muting capabilities in all output buffers  Single +3.3V or -3.3V power supply  Low power consumption of 1.8W at the maximum operational speed  Industrial temperature range  Custom CQFP 64-pin package vee vcc dop vcc don vcc 3wdo 3wdin 3wcin 3wenin vcc c2p vcc c2n vcc vee  ASNT2111 vee vcc q0p vcc q0n vcc nc lolp nc nc vcc q1p vcc nq1n vcc vee vee vcc nc vcc nc vcc nc ftr vcc_vco nc vcc c32p vcc c32n vcc vee vee vee pkdtp pkdtn dcinp vcc vcc dp vcc dn vcc vcc dcinn nc vee vee Rev. 1.0.2 1 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION DOB d dcinp dcinn pkdtp pkdtn Data IB c32 CLK IB D CDR DMX 1:2 c2 onco ondo ond2o DAC rangecrl vcosel tog pol upicpp upicpf COB offcml q0 q1 C2 lolp fltp 3wdin 3wcin 3wenin 3wdo D2OB x2 do 3-Wire Interface Fig. 1. Functional Block Diagram ASNT2111-KMF is a 1:2 demultiplexer (DMUX) with full-rate integrated clock and data recovery (CDR). The IC shown in Fig. 1 functions in CDR mode covering a wide range of input data rates (fbit) by utilizing its six on-chip VCOs (voltage-controlled oscillators). To reduce the physical number of control inputs to the chip, a shift register with a 3-wire input interface (SPI) has been included on chip. The SPI block provides all the digital controls for the chip. It also provides digital controls for digital-to-analog converters (DACs) that handle internal analog DC voltage adjustments. Selection of the desired working data rate of the CDR is accomplished through the digital control vcosel (see Table 1). An external low speed system clock c32p/c32n running at 1/32 the frequency of the active VCO must be applied to the low-speed clock input buffer (CLK IB). The main function of the chip is to convert a RZ or NRZ input data signal dp/dn with a bit rate of fbit accepted by CML buffer (Data IB) into 2 parallel NRZ data signals q0p/q0n and q1p/q1n running at bit rates of fbit/2 and delivered to the outputs by CML data output buffers (D2OBx2). The clock and data are recovered from the input data stream by the CDR. A full rate retimed NRZ data output signal dop/don is also available through the CML data output buffer (DOB) allowing the part to be used as a 1:1 CDR. Half rate clock c2p/c2n delivered through the CML clock output buffer (COB) has a tight phase alignment to the demultiplexed data output signals q0p/q0n and q1p/q1n. Rev. 1.0.2 2 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Data IB can operate with either differential or single-ended input signals. It includes tuning pins dcinp/dcinn for DC offset of the input signals in case of AC termination. When the buffer is operating with a DC-terminated single ended input signal, a correct threshold voltage should be applied to the unused input pin. A peak detector is also included to provide means of demodulating AM components carried by the input data with frequency ranges of up to a few hundred kHz. The peak detector’s output signal is delivered to the differential port pkdtp/pkdtn. All CML I/Os provide on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLY CONFIGURATION). Output buffers DOB, COB, and D2OBx2 can be individually disabled through control bits ondo, onco, and ond2o to save power. Utilizing control bit pol, the deserializer can invert the polarity of the three output data signals. Control bit tog flips the order of q0p/q0n and q1p/q1n signals thus simplifying the interface between the DMUX and a following ASIC. It also allows for synchronization of the bit order of two or more DMUXes working in parallel. A loss of lock CMOS alarm signal lolp is generated by the CDR to indicate its locking state. An off chip passive filter is required by the CDR, and should be connected to pin ftr (see CDR). The deserializer is characterized for operation from 0°C to 125°C of junction temperature. The package temperature resistance is 15°C /W. Data IB The Data Input Buffer (Data IB) can process an input CML data signal dp/dn in either RZ or NRZ format due to its high analog bandwidth. It provides on-chip single-ended termination of 50Ohm to vcc for each input line. The buffer can also accept a single-ended signal to one of its input ports dp or dn with a threshold voltage applied to the unused pin in case of DC termination. In case of AC termination, tuning pins dcinp/dcinn allow for data common mode adjustment. The tuning pins have 1kOhm terminations to vcc and allow the user to change the slicing level before the data is sampled by the recovered clock. Tuning voltages from vcc to vee deliver 150mV of DC voltage shift. Also included in Data IB is an input signal peak detector that delivers its response through the output differential signal pkdtp/pkdtn. The detector can demodulate AM component(s) carried by the input data with frequency ranges of up to a few hundred kHz. The detector’s output impedance is 4kOhm single ended to vcc. CLK IB The Clock Input Buffer (CLK IB) consists of a proprietary universal input buffer (UIB) that can operate in either CML or LVDS mode depending on the state of digital control bit offcml. This control should be set to “low” for CML mode and to “high” for LVDS mode. Depending on the mode of operation, the input impedance switches between 50 Ohms to vcc single-ended in CML mode, and 100 Ohms differential in LVDS mode. The input buffer exceeds LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is designed to accept differential signals with a speed up to 1Gb/s, DC common mode voltage variation between vcc and vee, AC common mode noise with a frequency up to Rev. 1.0.2 3 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com 5MHz, and voltage levels ranging from 0 to 2.4V. It can also receive a DC-terminated single-ended signal with a threshold voltage between vcc and vee applied to the unused pin. CDR The Clock and Data Recovery Block (CDR) contains a phase acquisition loop, and a frequency acquisition loop. The frequency loop works in concert with low-speed clock c32p/c32n while the phase loop utilizes input data signal dp/dn. The CDR requires a single off-chip filter shown in Fig. 2 to be connected to the pin ftr. 66Ohm ftr 390pF 22nF Fig. 2. External Loop Filter The main function of the CDR is to frequency-lock the selected on-chip VCO to the input data signal (clock recovery) while phase-aligning it to latch in the incoming data with minimal error (data recovery). By default, the CDR aligns the recovered clock’s working edge in the middle of the incoming data bits. The recovered clock is divided down in frequency by two (C2), and utilized by DMX 1:2 for demultiplexation of the recovered data. By utilizing the 3-bit digital control vcosel, the desired working frequency of the CDR can be selected in accordance with Table 1 below. Table 1. CDR Mode Selection vcosel 0 1 2 3 4 5 6 7 vcosel vcosel vcosel VCO Operation Frequency (GHz) 0 0 0 off 0 0 1 fmin≤16.7, fmax≥24.5 0 1 0 fmin≤19.4, fmax≥28.2 0 1 1 fmin≤22.2, fmax≥31.6 1 0 0 fmin≤25.1, fmax≥34.7 1 0 1 fmin≤27.8, fmax≥37.2 1 1 0 fmin≤31.0, fmax≥39.9 1 1 1 off The loop gain can be adjusted by two control bits upicpp and upicpf that control the charge pump current as shown in Table 2. Table 2. Charge Pump Current Control upicpp upicpf Charge Pump current, mA 0 0 Imax-0.31 0 1 Imax-0.27 1 0 Imax-0.04 1 1 Imax Rev. 1.0.2 4 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com By utilizing the control byte rngcrl the DC current of the control emitter follower of the active VCO can be adjusted linearly. Higher values of the control result in higher emitter follower currents. Higher emitter follower currents result in a more linear VCO frequency dependence on the control voltage at the expense of the frequency range. The lock detect circuitry signals an alarm through the 2.5V CMOS signal lolp when a frequency difference exists between an applied system reference clock c32p/c32n and a recovered full rate clock divided-by-32 that is greater than ±1000ppm. Another feature included in the CDR is the ability to simultaneously invert the polarity of all three data outputs through the 2.5V CMOS input pin pol (pol = “1” (default): direct; pol = “0”: inverted). The order of the half-rate output data streams can be inverted by using the 2.5V CMOS input pin tog, which provides means to synchronize two adjacent DMUXes operating in parallel. The synchronization process may be accomplished by the “blind” toggling in one of the chips and leaving the task of recognizing the “right” position to downstream components (e.g. FEC chip). DMX1:2 The 1 to 2 Demultiplexer (DMX1:2) latches in the retimed data stream D from the CDR on both edges of the half rate clock signal C2. The high speed data signal is subsequently demultiplexed into two half rate NRZ data signals, and delivered to D2OBx2 in parallel fashion as a 2-bit wide word with the order defined by the tog signal. DOB The Data Output Buffer (DOB) receives a full rate retimed serial data stream D from the CDR and converts it into a CML output signal dop/don. This CML buffer requires 50Ohm external termination resistors connected between vcc and each output. The buffer can be enabled or disabled by the control bit ondo (ondo = “1”: enabled; ondo = “0”: disabled). D2OBx2 The Half Rate Data Output Buffer (D2OBx2) receives two half rate data signals from DMX1:2 and converts them into CML output signals q0p/q0n and q1p/q1n. The buffer requires 50Ohm external termination resistors connected between vcc and each output. The buffer can be enabled or disabled by the control bit ond2o (ond2o = “1”: enabled; ond2o = “0”: disabled). COB The Clock Output Buffer (COB) receives a half rate clock signal from DMX1:2 and converts it into CML output signal c2p/c2n. The buffer requires 50Ohm external termination resistors connected between vcc and each output. The buffer can be enabled, or disabled by the control bit onco (onco = “1”: enabled; onco = “0”: disabled). The negative edge of the c2 signal is aligned to the half rate output data crossing points. 3-Wire Interface Control Block To reduce the physical number of control inputs to the chip, a 3-byte shift register with a 3-wire input interface has been included on chip. The SPI block is powered by an internally generated supply voltage of +1.2V from vee. The digital control bits applied through 3wdin input are latched in and shifted down Rev. 1.0.2 5 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com the register with the clock 3wcin. Write enable signal 3wenin must be set to logic “0” during the data read-in phase. The SPI data can be monitored through the output 3wdo. Table 3 presents the byte order of the 3-wire interface block. Table 3. Control Bytes Byte Number 1 2 3 7 6 5 upicpf X upicpp X tog X Bit Number 4 3 rngcrl(7:0) onco ond2o X X 2 1 0 ondo pol offcml vcosel(2:0) SPI load order is illustrated in Fig. 3. 3wcin 3wenin Sample Latch 3wdin X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X Byte 1 Byte N Fig. 3. SPI Load Order Rev. 1.0.2 6 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com POWER SUPPLY CONFIGURATION The ASNT2111-KMF can operate with either a negative supply (vcc = 0.0V = ground and vee = -3.3V), or a positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be needed for each different power supply combination. All the characteristics detailed below assume vcc = 3.3V and vee = 0V (external ground) ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only that are specified in ELECTRICAL CHARACTERISTICS. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee). Table 4. Absolute Maximum Ratings Parameter Supply Voltage (vcc) Power Consumption Input Voltage Swing (SE) Case Temperature*) Storage Temperature Operational Humidity Storage Humidity *) - Operating the part at temperatures over Min -40 10 10 Max +3.8 1.8 1.0 +90 +100 98 98 Units V W V ºC ºC % % this value could/will damage the part. Operating at this temperature or any temperatures above the recommended maximum value specified in ELECTRICAL CHARACTERISTICS does not guarantee correct functionality as is stated above. Rev. 1.0.2 7 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com TERMINAL FUNCTIONS Name vcc vcc_vco vee nc Name Supply and Termination Voltages Description Pin Number Positive power supply (+3.3V) 2, 4, 6, 11, 13, 15, 18, 20, 22, 27, 29, 31, 34, 36, 38, 43, 45, 47, 54, 55, 57, 59, 60 Positive power supply for VCO 9 (+3.3V) Negative power supply (GND or 0V) 1, 16, 17, 32, 33, 48, 49, 50, 63, 64 Not connected pins 3, 5, 7, 10, 23, 24, 26, 62 TERMINAL No. Type dp dn q1p q1n q0p q0n c2p c2n dop don 56 58 21 19 30 28 37 35 46 44 c32p c32n pkdtp pkdtn 3wenin 3wcin 3wdin 3wdo 12 Input 14 51 Output 52 39 1.2V CMOS input 40 41 42 1.2V CMOS output lolp 25 dcinp dcinn ftr Rev. 1.0.2 Input Output Output Output DESCRIPTION High-Speed I/Os CML differential data inputs with internal SE 50Ohm termination to vcc CML differential half rate data outputs. Require external SE 50Ohm termination to vcc CML differential half rate clock outputs. Require external SE 50Ohm termination to vcc CML differential full rate data outputs. Require external SE 50Ohm termination to vcc Low-Speed I/Os CML or LVDS clock input with internal SE 50Ohm SE or differential 100Ohm termination Peak detector outputs Enable input signal for 3-wire interface Clock input signal for 3-wire interface Data input signal for 3-wire interface Data output signal of 3-wire interface Controls LS out, CDR lock indicator (high: no lock; low: locked) 2.5V CMOS 53 LS IN Input data common mode voltage adjustment 61 8 I/O External CDR filter connection 8 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER TYP MAX UNIT COMMENTS General Parameters +3.0 +3.3 +3.6 V ±9% vcc 0.0 V vee Ivcc 535 mA All functions active Power Consumption 1.8 W Junction Temperature -25 50 125 °C Case temperature 75 °C Recommended value HS Input Data (dp/dn) Data Rate 18 36 Gbps NRZ Swing p-p (Diff or SE) 0.05 0.6 V CM Voltage Level vcc-0.8 vcc V LS Input Reference Clock (c32p/c32n) Frequency 562.5 1.125 MHz Swing p-p (Diff or SE) 0.06 0.8 V CM Voltage Level V vee vcc Duty Cycle 40 50 60 % HS Output Full Rate Data (dop/don) Data Rate 18 36 Gbps NRZ Logic “1” level V vcc Logic “0” level vcc -0.4 vcc -0.3 V Jitter 7 8 ps p-p HS Output Half Rate Data (q0p/q0n, q1p/q1n) Data Rate 9 18 Gbps Logic “1” level V vcc Logic “0” level vcc -0.4 V Jitter 7 ps p-p HS Output Half Rate Clock (c2p/c2n) Clock Rate 9 18 GHz 24 to 36Gbps input Logic “1” level V vcc Logic “0” level vcc -0.4 vcc -0.15 V Jitter 5 8 ps p-p Input Data Common Mode Control (dcinp/dcinn) Input DC Voltage V vee vcc Input Data Voltage Shift 0 -150 mV Referenced to vcc Output of Peak Detector (pkdtp/pkdtn) Swing p-p (Diff) -1 1 V Over full input range CM Voltage Level vcc -1.0 V 3-Wire Inputs (3wdin, 3wcin, 3wenin) High voltage level vee+1.1 vee+1.35 V Low voltage level vee vee+0.35 V Clock speed 350 400 MHz Rev. 1.0.2 MIN 9 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com PACKAGE INFORMATION The chip die is housed in a custom 64-pin CQFP package. The dimensioned drawings are shown in Fig. 4. The package’s leads will be trimmed to a length of 1.0mm. After trimming, the package’s leads will be further processed as follows: Fig. 4. CQFP 64-Pin Package Drawing (All Dimensions in mm) Rev. 1.0.2 10 October 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com 1. The lead’s gold plating will be removed per the following sections of J-STD-001D: 3.9.1 Solderability 3.2.2 Solder Purity Maintenance 3.9.2 Solderability Maintenance 3.9.3 Gold Removal 2. The leads will be tinned with Sn63Pb37 solder The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive supply. The part’s identification label is ASNT2111-KMF. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per EU 2011/65/EU for all ten substances. REVISION HISTORY Revision 1.0.2 Date 10-2020 0.0.1 03-2020 Rev. 1.0.2 Changes Official release Corrected frequency range Corrected filter schematic Preliminary release 11 October 2020