ASNT2124-KMM

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT2124-KMM DC-64Gbps Broadband Digital DDR 1:4 Demultiplexer  Differential CML I/O data and clock buffers  Half-rate clock input (DDR mode)  External control of internal clock’s duty cycle  Quarter-rate clock output  Single +3.3V or -3.3V power supply  Power consumption: 1.25W  Fabricated in SiGe for high performance, yield, and reliability  Custom CQFP 44-pin package vcc vee vcc q1p vcc q1n vcc vcc nc vcc dp ASNT2124-KMM q2p vcc q2n vcc vcc dn vcc 1 cep vcc cen vcc vcc q3n vcc dccp vcc dccn vcc vcc vee vcc q3p Rev. 1.2.2 vee vcc Exhibits low jitter and limited temperature variation over industrial temperature range vcc c4op vcc  q0n vcc q0p vcc c4on High speed broadband 1:4 Demultiplexer (DMUX) vcc  May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION 50 Ohm vcc q0p q0n 50 Ohm vcc q1p q1n dp dn q2p q2n 50 Ohm q3p q3n vcc 50 Ohm cep cen c4op c4on DIV 50 Ohm dccp dccn 50 Ohm 1000 Ohm Fig. 1. Functional Block Diagram ASNT2124-KMM is a low power and high-speed digital 1-to-4 deserializer-demultiplexer (DMUX) that functions seamlessly over data rates (fbit) ranging from DC to its maximum speed. The main function of the part shown in Fig. 1 is to demultiplex an incoming high speed serial differential CML data bit stream dp/dn running at a bit rate of fbit into 4 parallel data channels q0p/q0n, q1p/q1n, q2p/q2n, q3p/q3n running at a bit rate of fbit/4. Differential or single-ended half-rate clock cep/cen must be provided by an external source for the part to function properly. The internal clock’s duty cycle can be adjusted through analog ports dccp/dccn. The parallel words and clock divided-by-4 c4op/c4on are transmitted through CML output interfaces. The clock and data outputs are phase-matched to each other resulting in a very little relative skew over the operating temperature range of the device. The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLY CONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, the input termination provides the required common mode voltage automatically. The differential DC signaling mode is recommended for optimal performance. Rev. 1.2.2 2 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com HS CIB The high-speed clock input buffer can accept high-speed clock signals at its differential CML input port cep/cen. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HS CIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended 50Ohm termination to vcc for each input line. The buffer includes two external DC analog ports dccp and dccn for adjustment of its output signal duty cycle. By lowering the voltage of one of the ports below vcc while keeping the other one at vcc or not connected, the common mode voltage of the corresponding clock input can be lowered below vcc. If both control inputs are left not connected the common mode voltages of both clock inputs are at vcc. The dependence of either input clock common mode voltage on the control voltage is shown in Fig. 2. Fig. 2. Dependence of cep (or cen) Common Mode Voltage on dccp (or dccn) Voltage DMX4:1 The 1-to-4 internal demultiplexer utilizes a tree-type architecture which latches in the serial data stream on both edges of the half-rate clock signal that is supplied by the on-chip divider (DIV). The 4-bit wide data word is then delivered to the data output buffers. Data OBs The data output buffers receive high-speed data from DMX4:1 and convert them into differential CML output signals q0p/q0n, q1p/q1n, q2p/q2n, and q3p/q3n. The buffers utilize internal 50Ohm loads to vcc and require matching 50Ohm external termination resistors to be connected from vcc to each output. HS COB The quarter-rate clock output buffer utilizes the same termination scheme as Data OB and can operate at its maximum frequency while producing a full single-ended CML output swing. Rev. 1.2.2 3 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com POWER SUPPLY CONFIGURATION The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be needed for each different power supply combination. All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V. ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground. Table 1. Absolute Maximum Ratings Parameter Supply Voltage (vee) Power Consumption RF Input Voltage Swing (SE) Case Temperature Storage Temperature Operational Humidity Storage Humidity Rev. 1.2.2 Min -40 10 10 4 Max -3.6 1.3 1.0 +100 +100 98 98 Units V W V ºC ºC % % May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com TERMINAL FUNCTIONS TERMINAL Name No. Type q0p q0n q1p q1n q2p q2n q3p q3n c4op c4on cep cen dp dn dccp dccn Name vcc vee nc Rev. 1.2.2 DESCRIPTION Low-Speed I/Os 30 CML Differential quarter-rate data outputs. Require external SE output 50Ohm termination to vcc 32 37 CML output 39 41 CML output 43 4 CML output 6 26 CML Differential quarter-rate clock outputs. Require external SE output 50Ohm termination to vcc 28 High-Speed I/Os 8 CML Differential half-rate clock input signals with internal 50Ohm input termination to vcc 10 19 CML Differential full-rate data input signals with internal 50Ohm input termination to vcc 17 Control Ports 15 Analog Differential or SE tuning ports with internal SE connections to input dp/dn through 1000Ohm resistors 13 Supply and Termination Voltages Description Pin Number Positive power supply 1, 3, 5, 7, 9, 11, 12, 14, 16, 18, 20, 22, 23, 25, 27, (+3.3V or 0) 29, 31, 33, 34, 36, 38, 40, 42, 44 Negative power supply 2, 24, 35 (0V or -3.3V) Not connected pins 21 5 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER vee vcc Ivee Power consumption Junction temperature Data Rate Swing CM Voltage Level Frequency Differential swing CM Voltage Level Duty Cycle Data Rate Logic “1” level Logic “0” level Output Jitter Frequency Logic “1” level Logic “0” level Duty Cycle Output Jitter Voltage range Termination MIN TYP MAX UNIT COMMENTS General Parameters -3.1 -3.3 -3.5 V ±6% 0.0 V External ground 380 mA 1255 mW -40 25 125 °C HS Input Data (dp/dn) DC 40 64 Gb/s 0.2 0.8 V Differential or SE, p-p vcc-0.8 vcc V Must match for both inputs Half-Rate Input Clock (cep/cen) DC 20 32 GHz 0.2 0.8 V Differential or SE, p-p vcc-0.8 vcc V Must match for both inputs 40 50 60 % LS Output Data (q0p/q0n, q1p/q1n, q2p/q2n, q3p/q3n) DC 10 16 Gb/s V vcc vcc-0.44 V With external 50Ohm DC termination 2 ps Peak-to-peak at 10Gb/s LS Output Clock (c4op/c4on) DC 10 16 GHz V vcc vcc-0.4 V With external 50Ohm DC termination 50 % 1 ps Peak-to-peak at 10GHz Analog Control Inputs (dccp/dccn) V vee vcc 1.0 KOhm to corresponding clock input PACKAGE INFORMATION The chip die is housed in a custom, 44-pin CQFP package shown in Fig. 3. The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive supply. Rev. 1.2.2 6 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com The part’s identification label is ASNT2124-KMM. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten substances. Fig. 3. CQFP 44-Pin Package Drawing (All Dimensions in mm) Rev. 1.2.2 7 May 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com REVISION HISTORY Revision 1.2.2 1.1.2 1.1.1 Date 05-2020 07-2019 05-2016 1.0.1 1.0.0 05-2015 09-2014 Rev. 1.2.2 Changes Updated package information Updated Letterhead Corrected pin out diagram Corrected block diagram Corrected the Description section Corrected the HS CIB section Corrected Terminal Functions Corrected Electrical Characteristics Corrected Power Consumption First release Preliminary release 8 May 2020