IS31FL3726A-SALS4-TR 数据手册
IS31FL3726A
16-CHANNEL LED DRIVER
July 2020
GENERAL DESCRIPTION
FEATURES
The IS31FL3726A is an industry standard serial
shift-register-plus latch-type LED driver operating from a 3V
to 5V supply. It is comprised of 16 constant-current open
drain sinks designed for driving common anode LEDs.
The output current value can be set from 5mA to 60mA
by using an external resistor. As a result, all outputs will
have virtually the same current levels. This driver uses a
high-speed 4-wire serial interface of up to 30MHz to
drive 16 constant current outputs, a 16-bit shift register, a
16-bit latch and a 16-bit AND-gate circuit. Serial input
---------------
data appears at the output OUTn channels after 16
clock cycles. Driving the Latch pin will load the 16-bit of
shift-register data into the 16-bit output latch to drive the
LEDs ON or OFF. The Enable pin can be used as a
PWM input to adjust the LED brightness. The
IS31FL3726A operates from a 3V to 5.5V supply, and is
specified over the -40°C to +125°C temperature range.
Output current capability and number of outputs:
60mA × 16 outputs
Current set with external resistor
Constant current range: 5mA to 60mA
IOUT_MAX= 45mA @ VCC= 3V
IOUT_MAX= 60mA @ VCC= 5V
Current accuracy (All output on, IOUT = 25.2mA)
- Bit to bit: < ±4%.
- Device to device: < ±2%.
200mV LED Dropout at 25mA
For common-anode LEDs
Power supply voltage range, VCC= 3.0V to 5.5V
Serial and parallel data transfer rate: 30MHz
(Max. cascade connection)
Operating temperature range, TA= -40°C ~
+125°C
Package: QFN-24 (4mm×4mm), SSOP-24 and
eTSSOP-24
APPLICATIONS
Video display panel LED driver
Point of sale signs
Variable LED signboards
TYPICAL APPLICATION CIRCUIT
VBattery
LDO
3.3V
VCC
1 F
OUT0
0.1 F
OUT1
SERIAL-IN
OUT2
ENABLE
Micro
Controller
LATCH
IS31FL3726A
CLOCK
SERIAL-OUT
R-EXT
REXT
2k
GND
Figure 1
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
OUT13
OUT14
OUT15
Typical Application Circuit
1
IS31FL3726A
TYPICAL APPLICATION CIRCUIT (CONTINUE)
Figure 2
Typical Application Circuit (Serial Synchronization)
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
2
IS31FL3726A
PIN CONFIGURATION
Package
Pin Configuration (Top View)
QFN-24
SSOP-24
eTSSOP-24
GND
1
24
VCC
SERIAL-IN
2
23
R-EXT
CLOCK
3
22
SERIAL-OUT
LATCH
4
21
ENABLE
OUT0
5
20
OUT15
OUT1
6
19
OUT14
OUT2
7
18
OUT13
OUT3
8
17
OUT12
OUT4
9
16
OUT11
OUT5
10
15
OUT10
OUT6
11
14
OUT9
OUT7
12
13
OUT8
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
3
IS31FL3726A
PIN DESCRIPTION
No.
Pin
Description
22
SERIAL-OUT
Output pin for serial data input on SERIAL-IN
terminal.
2
23
R-EXT
Input pin connect to an external resistor to regulate
the output current.
3
24
VCC
Supply voltage pin.
4
1
GND
GND pin for control logic.
5
2
SERIAL-IN
Input pin for serial data for data shift register.
6
3
CLOCK
Input pin for clock for data shift on rising edge.
7
4
-------------------
LATCH
8 ~ 23
5~20
OUT0~OUT15
QFN
SSOP/eTSSOP
1
-------------------
---------------
-------------------
Input pin for data strobe when the LATCH input is
driven low, data is not latched. When it is pulled
high, data is latched.
Constant-current sinks.
Input pin for output enable.
---------------
24
21
-----------------------
ENABLE
Thermal Pad
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
-------------------
All current sinks (OUT0 to OUT15) are turned off,
-----------------------
when the ENABLE pin is driven High and are
turned on, when this pin is driven Low.
Connect to GND.
4
IS31FL3726A
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY
IS31FL3726A-QFLS4-TR
QFN-24, Lead-free
2500/Reel
IS31FL3726A-SALS4-TR
IS31FL3726A-SALS4
SSOP-24, Lead-free
2500/Reel
58/Tube
IS31FL3726A-ZLS4-TR
eTSSOP-24, Lead-free
2500/Reel
Copyright © 2020 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
5
IS31FL3726A
FUNCTIONAL BLOCK DIAGRAM
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
6
IS31FL3726A
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at any input pin
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Junction package thermal resistance, junction to ambient
(4 layer standard test PCB based on JESD 51-2A), θJA
Maximum power dissipation, PDMAX
ESD (HBM)
ESD (CDM)
-0.3V ~ +6.0V
-0.3V ~ VCC+0.2V
+150°C
-65°C ~ +150°C
-40°C ~ +125°C
29.1°C/W (QFN)
70.3°C/W (SSOP)
28.1°C/W (eTSSOP)
3.44W (QFN)
1.42W (SSOP)
3.56W (eTSSOP)
±8kV
±750V
Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITION
TA = 25°C, unless otherwise specified.
Symbol
VOUT
fCLK
Characteristic
Condition
Min.
Output (headroom) voltage
Clock frequency (Note 2)
Cascade connected
-------------------
Typ.
Max.
Unit
0.7
5
V
30
MHz
20
ns
20
ns
ENABLE pulse width (Note 2, 3)
70
ns
tSETUP1
SERIAL-IN set-up time for CLOCK
pin
8
ns
tHOLD1
SERIAL-IN Hold time for CLOCK
pin
8
ns
8
ns
8
ns
twLAT
twCLK
twENA
tSETUP2
tHOLD2
LATCH pulse width
CLOCK pulse width
-----------------------
-------------------
Set-up time for LATCH pin
-------------------
Hold time for LATCH pin
Note 2: Guaranteed by design.
-----------------------
Note 3: When the pulse of the Low level is input to the E N A B L E pin held in the High level.
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
7
IS31FL3726A
ELECTRICAL CHARACTERISTICS
TA = 25°C, VCC= 3.3V ~ 5.5V, unless otherwise specified.
Symbol
VCC
Characteristic
Supply voltage
IOUT
IMAT
Output current error
between bits (Note 5)
IOUT
Output current error
between ICs (Note 6)
Condition
Normal operation
26.5
VOUT= 1V,VCC= 5V
REXT = 750Ω
23.9
25.2
26.5
VOUT = 1V
VCC = 3.3V
REXT = 750Ω
IOUT=25.2mA
-4
4
%
VOUT = 1V
VCC = 5V
REXT = 750Ω
IOUT=25.2mA
-4
4
%
VOUT = 1V
VCC = 3.3V
REXT = 750Ω
IOUT=25.2mA
-2
2
%
VOUT = 1V
VCC = 5V
REXT = 750Ω
IOUT=25.2mA
-2
2
%
0.5
V
1
µA
VOUT = 5.5V
VOH
%/VCC
R(UP)
R(DOWN)
IDD(OFF)2
IDD(ON)1
Logic high level
Logic low level
0.3VCC
IOL = 1.0mA, VCC = 3.3V
0.4
IOL = 1.0mA, VCC = 5V
0.4
IOH = -1.0mA, VCC = 3.3V
2.9
IOH = -1.0mA, VCC = 5V
4.6
When VCC is changed 3.3V to 5.5V,
IOUT= 25.2mA
Pull-up resistor
-----------------------
ENABLE pin
Pull-down resistor
-------------------
Supply current
0.4
0.7VCC
Output current supply
voltage regulation
IDD(OFF)1
V
25.2
Output leakage current
input voltage
SERIAL-OUT pin
voltage
5.5
23.9
IOZ
VOL
Unit
REXT = 750Ω
REXT = 750Ω, IOUT= 25.2mA
VIL
Max.
VOUT= 1V,VCC= 3.3V
Headroom voltage
Input voltage
Typ.
3.0
VHR
VIH
Min.
LATCH pin
VOUT = 5V
VOUT = 5V
All outputs off
VOUT = 0.7V
All outputs on
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
mA
V
V
1
%
500
750
kΩ
REXT = OPEN
0.3
0.6
REXT = 0.75kΩ
REXT = 1.8kΩ
REXT = 0.75kΩ
2.1
1
8.6
2.5
1.2
10
REXT = 1.8kΩ
4.5
6
250
mA
8
IS31FL3726A
SWITCHING CHARACTERISTICS (NOTE 4)
TA = 25°C, unless otherwise specified
Symbol
Characteristic
Condition
——————
Min.
Max.
30
50
—————————
ENABLE = “L”
tpLH2
————————
L A T C H - OUTn , ENABLE = “L”
—————————
30
50
tpLH3
—————————
————————
50
70
20
40
60
100
tpLH
Propagation delay
tpHL1
——————
——————
ENABLE - OUTn , L A T C H = “H”
CLOCK - SERIAL-OUT
——————
————————
CLOCK - OUTn , L A T C H = “H”
—————————
ENABLE = “L”
tpHL2
————————
L A T C H - OUTn , ENABLE = “L”
—————————
60
100
tpHL3
—————————
————————
ENABLE - OUTn , L A T C H = “H”
CLOCK - SERIAL-OUT
70
100
20
40
tpHL
Unit
————————
CLOCK - OUTn , L A T C H = “H”
tpLH1
Typ.
——————
——————
ns
tor
Output rise time
10%~90% of voltage waveform
30
50
ns
tof
Output fall time
90%~10% of voltage waveform
52
80
ns
tr
Maximum CLOCK rise time
500
ns
tf
Maximum CLOCK fall time
500
ns
When not on PCB (Note 7)
Conditions: (Refer to test circuit.)
TA = 25°C, VCC=VIH =3.3V and 5V, VIL =0V, REXT =750Ω, VL =3.0V, RL=60Ω, CL=10.5pF
Note 4: Guaranteed by design.
Note 5: IOUT mismatch (bit to bit)
I MAT
IMAT is calculated:
I OUTn (n 0 ~ 15)
1 100%
I OUT 0 I OUT1 ... I OUT15
16
Note 6: IOUT accuracy (device to device) IOUT is calculated:
I OUT
I OUT 0 I OUT1 ... I OUT15
I OUT ( IDEAL) )
(
16
100%
I OUT ( IDEAL)
Where IOUT(IDEAL)= 10.5mA when REXT= 1800Ω, IOUT(IDEAL)= 25.2mA when REXT= 750Ω.
Note 7:
1. If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data
transfer. Please consider the timings carefully.
-----------------
2. Delay between outputs. The IS31FL3726A has graduated delay circuits between outputs. The fixed delay time is 5ns (typical), OUT1 has
----------------
5ns delay, OUT2 has 10ns delay, etc. This delay prevents large inrush currents, which reduce power supply bypass capacitor requirements
when the outputs turn on. The delay works during switch on and switch off of each output channel. LEDs that have not turned on before
———————
———————
ENABLE is low will still turn on and off at the determined delayed time regardless of the state of ENABLE. Therefore, every LED will be
———————
illuminated for the amount of time ENABLE is pulled high.
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
9
IS31FL3726A
TIMING WAVEFORM
————————
——————————
——————
1. CLOCK, SERIAL-IN, SERIAL-OUT, L A T C H , E N A B L E , OUTn
twCLK
50%
CLOCK
50%
tSETUP1
SERIAL-IN
50%
50%
tHOLD1
50%
SERIAL-OUT
tpLH/tpHL
tHOLD2
50%
LATCH
tSETUP2
50%
twLAT
ENABLE
L = OUTPUT ENABLE
H = OFF
50%
OUTn
L = ON
tpHL1/LH1
tpHL2/LH2
——————
2. OUTn
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
10
IS31FL3726A
Figure 3
Timing Diagram
Warning: The Latch input is a logic levelit is not an edge triggered latch circuit.
Note 8: The serial-in data (SERIAL-IN) will be clocked into a 16 bit shift register synchronized on the rising edge of the clock (CLOCK). The data
‘1’ means the corresponding current output ‘ON’ for output, the data ‘0’ represents for ‘OFF’. The data will be transferred into the 16 bit latch
————————
register when the signal ( L A T C H ) is ‘H’ (level trigger); otherwise, the data will be latched. The trigger timing of the serial-out data
(SERIAL-OUT) will be shifted out on synchronization to the rising edge of the clock. All outputs are turned off while enable terminal
—————————
—————————
( E N A B L E ) is kept at high level. And they are active when E N A B L E turns to low.
Truth Table
CLOCK
__________
____________
LATCH
ENABLE
SERIAL-IN
H
L
L
——————
——————
———————
OUT0 …OUT7 … OUT15
SERIAL-OUT
Dn
Dn …Dn-7 …Dn-15
Dn-15
L
Dn+1
No change
Dn-14
H
L
Dn+2
Dn+2 …Dn-5 …Dn-13
Dn-13
X
L
Dn+3
Dn+2 …Dn-5 …Dn-13
Dn-13
Dn+3
OFF
Dn-13
X
H
____________
__________
Warning: The following conditions, ENABLE=0, LATCH=1, SERIAL-IN=1, cannot be configured at the same time when power is on, or
IS31FL3726A will behave unpredictably.
—————
—————
—————
—————
Note 9: OUT0 to OUT15 =On when Dn = H; OUT0 to OUT15 =Off when Dn = L. In order to ensure that the level of the power supply
voltage is correct, an external resistor must be connected between R-EXT and GND.
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
11
IS31FL3726A
TYPICAL TEST CHARACTERISTICS
ICC
VCC
VCC
Figure 4
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
Test Diagram
12
IS31FL3726A
APPLICATION INFORMATION
ADJUSTING OUTPUT CURRENT
THERMAL CONSIDERATIONS
The output current of each channel is set by an
external resistor REXT, the relationship between IOUT
and REXT is:
The package thermal resistance, θJA, determines the
amount of heat that can pass from the silicon die to
the surrounding ambient environment. The θJA is a
measure of the temperature rise created by power
dissipation and is usually measured in degree
Celsius per watt (°C/W).
I OUT k
V REXT
R EXT
Where VREXT is 1.26V, k is 15, so IOUT is calculated by
Equation (1):
I OUT 15
1 .26 V
R EXT
(1)
When operating the chip at high ambient
temperatures, or when driving maximum load current,
care must be taken to avoid exceeding the package
power dissipation limits. The maximum power
dissipation can be calculated using the following
Equation (2):
As show in the figure below:
PD ( MAX )
60
So, PD ( MAX )
50
125C 25C
3.44W (QFN)
29.1C / W
125C 25C
1.42W (SSOP)
70.3C / W
20
PD ( MAX )
125C 25C
3.56W (eTSSOP)
28.1C / W
10
Figure 7 shows the power derating of the
IS31FL3726A on a JEDEC boards (in accordance
with JESD 51-5 and JESD 51-7) standing in still air.
30
0
0
1000
2000
Figure 5
3000
REXT (Ω)
4000
5000
6000
4
eTSSOP-24
3.5
IOUT vs. REXT
CONSTANT CURRENT OUTPUT
In order to obtain a good performance of
constant-current output, a suitable output voltage is
necessary. Users can get related information about
the minimum output voltage below.
70
3
QFN-24
2.5
2
SSOP-24
1.5
1
REXT=0.315kΩ
60
0.5
50
IOUT (mA)
(2)
JA
PD ( MAX )
Power Dissipation (W)
IOUT (mA)
40
TJ ( MAX ) TA
REXT=0.42kΩ
0
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature (°C)
40
30
REXT=0.75kΩ
Figure 7
Dissipation Curve
20
REXT=1.8kΩ
10
REXT=3.9kΩ
0
0 0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
VOUT (V)
Figure 6
2 2.2 2.4 2.6 2.8 3
IOUT vs. VOUT
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
13
IS31FL3726A
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 8
Classification Profile
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
14
IS31FL3726A
PACKAGE INFORMATION
QFN-24
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
15
IS31FL3726A
SSOP-24
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
16
IS31FL3726A
eTSSOP-24
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
17
IS31FL3726A
RECOMMENDED LAND PATTERN
QFN-24
SSOP-24
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
18
IS31FL3726A
eTSSOP-24
Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use.
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
19
IS31FL3726A
REVISION HISTORY
Revision
Detail Information
Date
0A
Update to Lumissil Logo
2020.01.22
0B
Update typical application circuit, EC table and application information
2020.06.04
A
Release to mass production
2020.06.23
Lumissil Microsystems – www.lumissil.com
Rev. A, 06/23/2020
20
工商网监
湘ICP备2023018690号
