ASNT1011-KMA

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT1011-KMA DC-to-17Gbps Digital Multiplexer / Serializer 16:1or 8:1 Broadband programmable digital serializer 16-to-1 or 8-to-1 LVDS compliant input data buffers Full-rate clock output Selectable LVDS-compliant divided output clock with optional 90°-step phase adjustment Single +3.3V power supply Industrial temperature range Low power consumption of 660mW at the maximum speed Custom 100-pin CQFP package (13mm x 13mm) vee 75 nc 74 d04n 73 d04p 72 vcc 71 d03n 70 d03p 69 vcc 68 d02n 67 d02p 66 vcc 65 d01n 64 d01p 63 vcc 62 d00n 61 d00p 60 nc 59 vee 58 phs1 57 phs2 56 vcc 55 nc 54 nc 53 vcc 52 vee 51         Rev. 3.3.2 ASNT 1011 vee 50 nc 49 nc 48 vcc 47 clop 46 clon 45 vcc 44 nc 43 nc 42 vcc 41 qcmlp 40 qcmln 39 vcc 38 vee 37 vee 36 vcc 35 chop 34 chon 33 vcc 32 nc 31 vee 30 vcc 29 cep 28 cen 27 vcc 26 1 vee 2 nc 3 d13p 4 d13n 5 vcc 6 d14p 7 d14n 8 vcc 9 d15p 10 d15n 11 vcc 12 nc 13 nc 14 vcc 15 vee 16 off16b 17 vee 18 offcho 19 nc 20 nc 21 nc 22 nc 23 vee 24 vcc 25 vcc 76 vcc 77 d05p 78 d05n 79 vcc 80 d06p 81 d06n 82 vcc 83 d07p 84 d07n 85 vcc 86 d08p 87 d08n 88 vcc 89 d09p 90 d09n 91 vcc 92 d10p 93 d10n 94 vcc 95 d11p 96 d11n 97 vcc 98 d12p 99 d12n 100 vcc 1 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION off16b d00 d15 LS DIB x16 16 Data OB MUX 16:1 LVDS COB C16 /16 CPR C8 ce HS CIB HS COB C dcc qcml clo phs1 phs2 offcho cho Fig. 1. Functional Block Diagram ASNT1011-KMA is a low power and high-speed programmable multiplexer (MUX) 16-to-1 (16:1) or 8-to-1 (8:1) IC. The IC shown in Fig. 1 functions seamlessly over data rates (fbit) ranging from DC to maximum. The main function of the chip shown in Fig. 1 is to multiplex/serialize M input parallel data channels running at a bit rate of fbit/M into a high-speed serial bit stream running at fbit. The value of M is selected by the control signal off16b. It provides a high-speed output data channel for point-to-point data transmission over a controlled impedance media of 50Ohm. The transmission media can be a printed circuit board or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation characteristics of the transportation media and the degree of noise coupling to the signaling environment. During normal operation with M=16 (off16b =”0”), the serializer’s low-speed input buffer (LS DIBx16) accepts external 16-bit wide parallel data words d00p/d00n-d15p/d15n through 16 differential LVDS inputs and delivers them to the multiplexer’s core (MUX16:1) for serialization. A full rate clock must be provided by an external source cep/cen to the high-speed clock input buffer (HS CIB) where it is routed to the high speed clock output buffer (HS COB) and the internal divider-by-16 (/16). The divider provides signaling for MUX16:1 and produces a clock divided-by-16 (C16) for the low speed LVDS compliant clock output buffer (LVDS COB).The phase of clop/clon can be modified by 90° increments by utilizing pins phs1 and phs2 and the clock processing block (CPR). During normal operation with M=8 (off16b =”1”), the part operates in a similar way but the serializer’s lowspeed input buffer (LS DIBx16) accepts only l 8-bit wide parallel data words d00p/d00n-d07p/d07n through Rev. 3.3.2 2 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com the first eight differential LVDS inputs. In this mode, the divider (/16) also generates a clock divided-by-8 (C8) that is delivered to LVDS COB. The phs1 and phs2 controls are disabled in this operational mode. The serialized words are transmitted as 2-level signals qcmlp/qcmln by a differential CML output buffer (Data OB). A full-rate clock is transmitted by HS COB in parallel with the high-speed data. The clock and data outputs are well phase matched to each other resulting in very little relative skew over the operating temperature range of the device. Both output stages are back terminated with on-chip 50Ohm resistors. The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C of junction temperature. LS DIBx16 The Low-Speed Data Input Buffer (LS DIBx16) consists of 16 proprietary universal input buffers (UIBs) that exceed the LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is designed to accept differential signals with amplitudes above 60mV peak-to-peak (p-p), DC common mode voltage variation between the negative vee and positive vcc supply rails, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes above 60mVp-p and threshold voltages between vee and vcc. The input termination impedance is set to 100Ohm differential. HS CIB The High-Speed Clock Input Buffer (HS CIB) can accept high-speed clock signals at its differential CML input port cep/cen. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HS CIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended termination of 50Ohm to vcc for each input line. /16 The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed clock C is fed into the first divide-by-2 circuit that generates half rate clock C2. C2 is routed internally to the next divide-by-two circuit and outside of the block to MUX16:1. Other divided down clock signals are formed and routed to MUX16:1 in similar fashion. C16 and/or C8 are passed on to LVDS COB to become the output low speed clock signal clop/clon. MUX16:1 The 16-to-1 Multiplexer (MUX16:1) utilizes a tree type architecture that latches the incoming data on the negative edge of the C16 clock signal that is supplied by /16. The 16-bit wide data word is subsequently multiplexed and delivered to Data OB as a single serial data stream running at a data rate up to specified maximum. The latency of this circuit block is equal to roughly one period of C16 or C8 depending on the mode of operation. The input MSB corresponds to d00p/d00n. Data OB The Data Output Buffer (Data OB) receives high-speed serial data from MUX16:1 and converts it into differential CML output signal qcmlp/qcmln. The buffer requires 50Ohm external termination resistors connected between vcc and each output to match its internal 50Ohm resistors. Rev. 3.3.2 3 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com HS COB The High Speed Clock Output Buffer (HS COB) utilizes the same termination scheme as Data OB. The buffer can be enabled or disabled by the external 2-state control signal offcho. The logic “0” state provides a full-rate clock output signal while the logic “1” state disables the buffer completely to save power. CLK Proc By utilizing the CMOS control pins phs1 and phs2 in the 16-bit operational mode, the phase of clop/clon can be altered in accordance with Table 1. Table 1. Output Clock Phase Selection phs1 phs2 C16 phase vee (default) vee (default) 270° 180° vee vcc 90° vcc vee 0° vcc vcc LVDS COB The LVDS Clock Output Buffer (LVDS COB) receives C16 or C8 and converts it into an LVDS output signal clop/clon. The proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at frequencies up to 2.0GHz with a nominal output current of 3.5mA. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. Output Timing The phase relation between the output data qcmlp/qcmln and the full rate output clock chop/chon is specified in Table 2 and illustrated by Fig. 2. Table 2. Output Data-to-Clock Phase Difference Junction temperature, τ,ps ºC Min. Max. -25 77 80 50 82 86 125 87 91 clk edge Output Data τ Tclk Fig. 2. Output Timing Diagram Rev. 3.3.2 4 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings shown in Table 3 may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vee). Table 3. Absolute Maximum Ratings Parameter Supply Voltage (vcc) Power Consumption RF Input Voltage Swing (SE) Case Temperature Storage Temperature Operational Humidity Storage Humidity Min Max +3.6 0.72 1.0 +90 +100 98 98 -40 10 10 Units V W V ºC ºC % % TERMINAL FUNCTIONS Name vcc vee nc Supply And Termination Voltages Description Pin Number Positive power 5, 8, 11, 14, 24, 25, 26, 29, 32, 35, 38, 41, 44, 47, 52, 55, supply (+3.3V) 62, 65, 68, 71, 76, 79, 82, 85, 88, 91, 94, 97, 100 Negative power 1, 15, 17, 23, 30, 36, 37, 50, 51, 58, 75 supply (GND or 0V) Not connected pins 2, 12, 13, 19, 20, 21, 22, 31, 42, 43, 48, 49, 53, 54, 59, 74 TERMINAL Name No. Type Rev. 3.3.2 cep cen chop chon qcmlp qcmln 28 27 34 33 40 39 phs1 phs2 off16b 57 56 16 offcho 18 DESCRIPTION High-Speed I/Os CML differential external clock inputs with internal SE 50Ohm termination to vcc Output CML differential clock outputs. Require external SE 50Ohm termination to vcc Output CML differential data outputs. Require external SE 50Ohm termination to vcc Controls Low-speed output clock phase selection (default: both low) Input LS In., Multiplexation coefficient M control (active: high, M=8; CMOS default: low, M=16) HS COB control (active: high, buffer is disabled; default: low, full-rate output clock) 5 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com TERMINAL Name No. Type clop clon d00p d00n d01p d01n d02p d02n d03p d03n d04p d04n d05p d05n d06p d06n d07p d07n d08p d08n d09p d09n d10p d10n d11p d11n d12p d12n d13p d13n d14p d14n d15p d15n Rev. 3.3.2 46 45 60 61 63 64 66 67 69 70 72 73 77 78 80 81 83 84 86 87 89 90 92 93 95 96 98 99 3 4 6 7 9 10 DESCRIPTION Low-Speed I/Os Output LVDS clock outputs. Can transmit four different clock phases as defined by phs1 and phs2 Input LVDS data inputs 6 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER vcc vee Ivcc Power consumption Junction temperature Data Rate Differential Swing CM Voltage Level Frequency Swing (Diff or SE) CM Voltage Level Duty Cycle Data Rate Logic “1” level Logic “0” level Jitter Frequency Logic “1” level Logic “0” level Jitter Duty Cycle Frequency Interface Logic “1” level Logic “0” level Rev. 3.3.2 MIN TYP MAX UNIT COMMENTS General Parameters +3.14 +3.3 +3.47 V ±5% 0.0 V External ground 200 mA 660 mW -25 50 125 °C LS Input Data (d00p/d00n-d15p/d15n) 0.0 937.5 1063 Mbps 0.06 0.8 V Peak-to-peak V vee vcc HS Input Clock (cep/cen) 0.0 15 17 GHz 0.2 1.2 V Peak-to-peak vcc -0.8 vcc V 40% 50% 60% HS Output Data (qcmlp/qcmln) 0.0 15 17 Gbps V vcc vcc -0.6 V 12 ps Peak-to-peak @12.5Gb/s HS Output Clock (chop/chon) 0.0 15 17 GHz V vcc vcc -0.6 V 6 ps Peak-to-peak @12.5GHz 50% LS Output Clock (clop/clon) 0.0 937.5 1063 MHz LVDS Meets the IEEE Std. CMOS Control Inputs vcc -0.4 V vee +0.4 V 7 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com PACKAGE INFORMATION Fig. 3. Package Drawing Rev. 3.3.2 8 January 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com The chip die is housed in a custom 100-pin CQFP package shown in Fig. 3. The package’s leads will be trimmed to a length of 1.0mm. After trimming, the package’s leads will be further processed as follows: 1. The lead’s gold plating will be removed per the following sections of J-STD-001D: 3.9.1 Solderability 3.2.2 Solder Purity Maintenance 3.9.2 Solderability Maintenance 3.9.3 Gold Removal 2. The leads will be tinned with Sn63Pb37 solder Even though the package provides a center heat slug located on the back side of the package to be used for heat dissipation, ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer wishes to solder it, it should be connected to the vcc plain that is ground for the negative supply or power for the positive supply. The part’s identification label is ASNT1011-KMA. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten substances. REVISION HISTORY Revision 3.3.2 3.2.2 3.2.1 3.1.1 Date 01-2020 07-2019 08-2018 08-2018 2.3.1 2.2.1 07-2016 05-2015 2.1 2.0 06-2012 01-2012 1.0 01-2011 Rev. 3.3.2 Changes Updated Package Information Updated Letterhead Corrected recommendations for heat slug handling Corrected title Corrected Pin Diagram (pin 16 is off16b) Added description of the 8-bit mode Corrected Terminal Functions table Corrected Package Information section Revised Terminal Functions section Corrected Absolute Maximum Ratings section Revised Package Information section Updated format Corrected package dimensions Revised Electrical Characteristics section Revised Package Information section Added Absolute Maximums Rating table Added Pin Diagram First release 9 January 2020