MPC565CZP40

Product Brief MPC565PB/D Rev. 3, 2/2003 MPC565/MPC566 Product Brief This document provides an overview of the MPC565/MPC566 microcontrollers, including a block diagram showing the major modular components, sections that list the major features, and differences between the MPC565/MPC566 and the MPC555. The MPC565 and MPC566 devices are members of the Motorola MPC500 RISC Microcontroller family. The parts herein will be referred to only as MPC565 unless specific parts need to be referenced. Table 1. MPC565/MPC566 Features 1 Device Flash Code Compression MPC565 1 Mbyte Code compression not supported MPC566 1 Mbyte Code compression supported Introduction The MPC565 device offers the following features: • • • • • • • • PowerPC™ core with a floating point unit (FPU) and a burst buffer controller (BBC) Unified system integration unit (USIU), a flexible memory controller, and improved interrupt controller 1 Mbyte of Flash memory (UC3F) — Typical endurance of 100,000 write/erase cycles @ 25ºC — Typical data retention of 100 years @ 25ºC 36 Kbytes of static RAM (two CALRAM modules) — 8 Kbytes of normal access or overlay access (sixteen 512-byte regions) — 4 Kbytes in CALRAM A, 4 Kbytes in CALRAM B Three time processor units (TPU3) — TPU3 A and TPU3 B are connected to DPTRAM AB (6 Kbytes) — TPU3 C is connected to DPTRAM C (4 Kbytes) A 22-timer channel modular I/O system (MIOS14) — Same as MIOS1 plus a real-time clock sub-module (MRTCSM), 4 counter sub-modules (MCSM), and 4 PWM sub-modules (MPWMSM) Three TouCAN modules (TouCAN_A, TouCAN_B, and TouCAN_C) Two enhanced queued analog to digital converters (QADC64E A, QADC64E B) with analog multiplexers (AMUX) for 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part. Block Diagram • Two queued serial multi-channel modules (QSMCM A, QSMCM B), each of which contains a queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART) • -40°C – 125°C ambient temperature, -40°C – 85°C for suffix C devices, -55°C– 125°C for suffix A devices • Debug features: — A J1850 (DLCMD2) communications module — A Nexus debug port (class 3) – IEEE-ISTO 5001-1999 — JTAG and background debug mode (BDM) • 1.1 Packaging and Electrical Block Diagram Figure 1 is a block diagram of the MPC565. JTAG Burst Buffer Controller 2 512 Kbytes Flash 512 Kbytes Flash U-Bus DECRAM (4Kbytes) PowerPC 4 Kbyte CALRAM B Core + FP E-Bus USIU READI 4 Kbyte Overlay L2U L-Bus 32 Kbyte CALRAM A 28 Kbytes SRAM No Overlay 4 Kbyte Overlay QADC64E w/AMUX QADC64E w/AMUX QSMCM UIMB I/F QSMCM DLCMD2 IMB3 TPU3 6 Kbytes DPTRAM TPU3 TPU3 4 Kbytes DPTRAM Tou CAN Tou CAN Tou CAN MIOS14 Figure 1. MPC565 Block Diagram 2 MPC565/MPC566 Product Brief MOTOROLA Detailed Feature List 1.2 Detailed Feature List The MPC565 key features are explained in the following sections. 1.2.1 • • 1.2.2 • 1.2.3 • • • • • • • • • 1.2.4 • High Performance CPU System Fully static design Four major power saving modes — On, doze, sleep, deep-sleep and power-down RISC MCU Central Processing Unit (RCPU) High-performance core — PowerPC single issue integer core — Precise exception model — Floating point — Code compression (MPC566 only) – Compression reduces usage of internal or external Flash memory – Compression optimized for automotive (non-cached) applications – New compression scheme decreases code size to 40% –50% of source MPC500 System Interface (USIU) MPC500 system interface (USIU, BBC, L2U) Periodic interrupt timer, bus monitor, clocks, decrementer and time base Clock synthesizer, power management, reset controller External bus tolerates 5-V inputs, provides 2.6-V outputs Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40 internal interrupts IEEE 1149.1 JTAG test access port Bus supports multiple master designs USIU supports dual-mapping of Flash to move part of internal Flash memory to external bus for development External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions per memory cycle Burst Buffer Controller (BBC) Module Exception vector table relocation features allow exception table to be relocated to following locations: — 0x0000 0000 - 0x0000 1FFF (normal MPC500 exception table location) — 0x0001 0000 - 0x0001 1FFF (0 + 64 Kbytes; second page of internal Flash) — Second internal Flash module — Internal SRAM — 0x0FFF_0100 (external memory space; normal MPC500 exception table location) MOTOROLA MPC565/MPC566 Product Brief 3 Detailed Feature List 1.2.5 • • • 1.2.6 • • • • • • • • • 1.2.7 • Flexible Memory Protection Unit Flexible memory protection units in BBC (IMPU) and L2U (DMPU) Default attributes available in one global entry Attribute support for speculative accesses Memory Controller Flexible chip selects via memory controller 24-bit address and 32-bit data buses 4- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support Four-beat transfer bursts, two-clock minimum bus transactions Use with SRAM, EPROM, Flash and other peripherals Byte selects or write enables 32-bit address decodes with bit masks Four instruction regions Four data regions 1 Mbyte of CDR3 Flash EEPROM Memory (UC3F) • • • • • 1 Mbyte Flash — Two UC3F modules, 512 Kbytes each Page mode read Block (64-Kbyte) erasable External 4.75- to 5.25-V VPP program and erase power supply Typical endurance of 100,000 write/erase cycles @ 25ºC Typical data retention of 100 years @ 25ºC 1.2.8 36-Kbyte Static RAM (CALRAM) • 36-Kbyte static calibration RAM — Composed of 4-Kbyte and 32-Kbyte CALRAM modules Fast access: one clock Keep-alive power Soft defect detection (SDD) 4 Kbyte calibration (overlay) RAM per module (8 Kbytes total) Eight 512-byte overlay regions per module (16 regions total) • • • • • 1.2.9 • • • • • 4 General Purpose I/O Support (GPIO) General-purpose I/O support Address (24) and data (32) pins can be used as GPIO in single-chip mode 16 GPIO in MIOS14 Many peripheral pins can be used as GPIO when not used as primary functions 5-V outputs with slew rate control MPC565/MPC566 Product Brief MOTOROLA Detailed Feature List 1.2.10 Debug Features • • • • Extensive system debug support On-chip watchpoints and breakpoints Program flow tracking Background debug mode (BDM) 1.2.10.1 Nexus Debug Port (Class 3) • • Nexus/IEEE – ISTO 5001-1999 debug port (Class 3) Nine- or 16-pin interface 1.2.10.2 Message Data Link Controller (DLCMD2) Module • Two pins muxed with QSMCMB pins. Muxing controlled by QSMCMB PCS3 pin assignment register • SAE J1850 Class B data communications network interface compatible and ISO compatible for low-speed (